CN101599693B - Quick response device and method of switching power converter - Google Patents
Quick response device and method of switching power converter Download PDFInfo
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Abstract
The invention provides a quick response device and a method of a switching power converter. The device comprises a detection circuit and a regulating circuit; wherein, the detection circuit is used for detecting the output voltage so as to trigger quick response during instantaneous load; the regulating circuit is used for turning on at least two of a plurality of channels when quick response is triggered and for lessening the quantity of the channels turned on along with the increase of time. The quick response device of the invention has the advantage of avoiding ringback.
Description
Technical field
The present invention relates to a kind of switch type power converter, specifically, is a kind of quick response device and method of switch type power converter.
Background technology
Fig. 1 shows traditional heterogeneous switch type power converter 10, wherein error amplifier 14 produces error signal Vcomp according to the reference voltage Vref that output voltage V core and the reference voltage generator 12 of power supply changeover device 10 provides, sawtooth generator 16 provides sawtooth waveforms Vramp1 and Vramp2, pulse-width modulation (Pulse Width Modulation; PWM) comparator 18 produces signal Vpwm1 with control channel 22 according to error signal Vcomp and sawtooth waveforms Vramp1, and PWM comparator 20 produces signal Vpwm2 with control channel 24 according to error signal Vcomp and sawtooth waveforms Vramp2.Fig. 2 shows the oscillogram of signal among Fig. 1, and wherein waveform 26 is output voltage V core, and waveform 28 is sawtooth waveforms Vramp1, and waveform 30 is sawtooth waveforms Vramp2, and waveform 32 is error signal Vcomp, and waveform 34 is signal Vpwm1, and waveform 36 is signal Vpwm2.When sawtooth waveforms Vramp2 is lower than error signal Vcomp, as time t1, signal Vpwm2 transfers high levle to open (turn on) passage 24, shown in waveform 36, passage 24 will provide electric charge to capacitor C 2 so that output voltage V core rises after being opened, shown in waveform 26, when sawtooth waveforms Vramp2 is higher than error signal Vcomp, as time t2, signal Vpwm2 transfers low level to close (turn off) passage 24.When sawtooth waveforms Vramp1 is lower than error signal Vcomp, as time t3, signal Vpwm1 transfers high levle to open passage 22, shown in waveform 34, passage 22 will provide electric charge to capacitor C 1 so that output voltage V core rises after being opened, when sawtooth waveforms Vramp1 was higher than error signal Vcomp, as time t4, signal Vpwm1 transferred low level to closing passage 22.
Yet, no matter the load current of CPU is to be uprised or by high step-down by low now, its variation is quite quick, the time that changes is within 1us, this switching cycle with power supply changeover device 10 is compared quite and is lacked, when if load instantaneous appears at the pulse of signal Vpwm1 or Vpwm2, as time t1 to t2 or time t3 to t4, because passage 22 or 24 is opened, therefore can relax the speed that output voltage V core descends, but when load instantaneous appears between the pulse of signal Vpwm1 and Vpwm2, as time t2 to t3, because signal Vpwm1 and Vpwm2 are low level, so output voltage V core will break away from control, and, even if load instantaneous is the impulse duration that appears at signal Vpwm1 or Vpwm2, if load variations is too big, output voltage V core still falls sharply, so need to respond (quick response) loop fast can open passage 22 and 24 simultaneously when load instantaneous occurs.Good output voltage V core is arranged, good quick response will be arranged, and will reach good quick response two keys are arranged, one is to trigger the opportunity of response fast, and another is the time length that responds fast.If trigger response fast too slowly, may make output voltage V core be lower than the requirement of regulation, the situation that super (undershoot) namely occur hanging down on the contrary, if too fast the triggering fast responds, may cause output voltage V core sharp wave (spike) to occur.If fast the time of response too short, low super situation still can appear in output voltage V core, if but fast the time of response oversize, output voltage V core will rise excessive and resilience (ringback) situation occur.
Fig. 3 shows a kind of known to realize adaptation phase alignment (the Adaptive Phase Alignment of response fast; APA) circuit 40, it comprises that error amplifier 42 produces error signal Vcomp according to output voltage V core and the difference between the reference voltage Vref of power supply changeover device, low pass filter 44 filtering error signal Vcomp produce signal V2, current source 48 provides electric current I apa to produce voltage Vapa offset error signal Vcomp through resistance R apa and produces signal V1, and comparator 46 produces quick response signal QR according to signal V1 and V2.Fig. 4 is in order to illustrate the operation of known quick response, when supposing that APA circuit 40 among Fig. 3 is applied in N phase switch type power converter, under normal circuit controls, a plurality of channels of described power supply changeover device will be in regular turn by signal Vpwm1, Vpwm2, Vpwm3 and signal VpwmN open, as waveform 52,54, shown in 56 and 58, when load instantaneous takes place when, as time t5, error signal Vcomp will descend, signal V2 also will descend thereupon, because the relation of capacitor C apa, signal V1 can not descend immediately, when signal V2 is lower than signal V1, response signal QR transfers high levle to trigger quick response fast, shown in waveform 50, at quick response duration, all passages of this power supply changeover device all will be opened.
In APA circuit 40, because the triggering of response is to be determined by signal V1 fast, and signal
V1=Vcomp-Iapa * Rapa formula 1
Therefore, can change by the resistance R apa that is adjusted at chip exterior and trigger the time point of response fast, for example, use bigger resistance R apa to postpone the trigger voltage of response fast.Yet in APA circuit 40, the duration of response is to be determined by low pass filter 44 fast, and build in the chip in the low pass filter 44, therefore can't adjust the time of quick response.
In known fast response method, avoid output voltage V core low super situation to occur by opening whole channels, but after being opened, whole passages will provide a large amount of electric charge to output Vcore, therefore, when the width of quick response signal QR because of non-ideal effects during less times greater than theoretical value, to be easy to occur rebound phenomenon, shown in the waveform 60 of Fig. 4, non-ideal effects comprises delay, dead resistance and parasitic capacitance etc., when the peak value of resilience surpasses a critical value, circuit on the power supply changeover device output may be damaged, CPU for example, though the electric capacity that is increased on this power supply changeover device output can suppress rebound phenomenon, this will cause cost to increase.
Therefore known quick response device exists above-mentioned all inconvenience and problem.
Summary of the invention
Purpose of the present invention is to propose a kind of quick response device and the method that can avoid the switch type power converter of rebound phenomenon.
For achieving the above object, technical solution of the present invention is:
A kind of quick response device of switch type power converter comprises a testing circuit and a regulating circuit, and described switch type power converter comprises a plurality of passages so that an output voltage to be provided, wherein:
Described testing circuit detects described output voltage, triggers response fast when load instantaneous takes place;
Described regulating circuit is opened at least two in described a plurality of passage when described quick response triggers, and increases the quantity that reduces the passage of opening along with the time;
Wherein, described regulating circuit comprises a plurality of control circuits, and each described control circuit comprises:
One minimum operating time produced circuit, when described quick response is triggered, provided a quick response signal;
One drive circuit, open the quantity of described a plurality of passages according to the operating time decision of described quick response signal, open in described a plurality of passage at least one in the operating time of described quick response signal, and the quantity difference of the passage that each described control circuit is opened, the operating time of described quick response signal is more long, and the quantity of the passage of opening is more few.
The quick response device of switch type power converter of the present invention can also be further achieved by the following technical measures.
Aforesaid quick response device, wherein said testing circuit comprises:
One resistance;
One current source provides an electric current to described resistance to obtain one second voltage to produce one first voltage in order to be offset described output voltage;
One comparator, more described second voltage and a tertiary voltage trigger described quick response to produce one second quick response signal.
Aforesaid quick response device, the wherein said minimum operating time produces circuit and comprises:
One electric capacity;
One current source when triggering response fast, provides an electric current that described electric capacity is charged;
One logical circuit determines described quick response signal according to output and the voltage on the described electric capacity of described testing circuit.
Aforesaid quick response device, wherein said drive circuit comprise a default pattern, and described drive circuit determines the passage that will open according to described default pattern and quick response signal.
A kind of fast response method of switch type power converter, described switch type power converter comprise a plurality of passages so that an output voltage to be provided, and it is characterized in that, comprise the following steps:
First step: detect described output voltage, when taking place, load instantaneous triggers response fast, at this moment, open at least two in described a plurality of passage, described at least two the step of opening in described a plurality of passage is included in described quick response when triggering, a plurality of signals with different operating time are provided simultaneously, and each described signal is in order to opening at least one in described a plurality of passage, and the quantity difference of the passage opened of each described signal;
Second step: during described quick response, increase the quantity that reduces the passage of opening along with the time, the described step that increase to reduce the quantity of the passage of opening along with the time comprises the quantity that determines the passage that each described signal will be opened according to the operating time length of each described signal, wherein the operating time more long, the quantity of the passage of opening is more few.
The fast response method of switch type power converter of the present invention can also be further achieved by the following technical measures.
Aforesaid fast response method, the step of the described output voltage of wherein said detection comprises:
First step: be offset described output voltage and produce an offset voltage;
Second step: when described offset voltage is lower than a reference voltage, trigger described quick response.
Aforesaid fast response method wherein more comprises according to each described signal and corresponding default pattern thereof determining the passage that will open.
After adopting technique scheme, the quick response device of switch type power converter of the present invention has the advantage of avoiding rebound phenomenon.
Description of drawings
Fig. 1 shows traditional heterogeneous switch type power converter;
Fig. 2 shows the oscillogram of signal among Fig. 1;
Fig. 3 shows a kind of known to realize the adaptation phase alignment circuit of response fast;
Fig. 4 illustrates the operation of known quick response;
Fig. 5 shows the embodiments of the invention schematic diagram;
Fig. 6 shows the first embodiment schematic diagram of regulating circuit among Fig. 5;
The operation of regulating circuit in Fig. 7 key diagram 6;
Fig. 8 shows the second embodiment schematic diagram of regulating circuit among Fig. 5;
Fig. 9 shows the oscillogram of signal among Fig. 8;
Figure 10 shows the embodiment schematic diagram of presetting pattern among Fig. 8 in the drive circuit 7408;
Figure 11 shows the embodiment schematic diagram of presetting pattern among Fig. 8 in the drive circuit 7412;
Figure 12 shows the embodiment schematic diagram of presetting pattern among Fig. 8 in the drive circuit 7418;
Figure 13 shows that the minimum operating time produces the embodiment of circuit schematic diagram;
Figure 14 shows the oscillogram of signal among Figure 13.
Embodiment
Below in conjunction with embodiment and accompanying drawing thereof the present invention is illustrated further.
Owing to cause rebound phenomenon to be because inject big multi-charge to the output of power supply changeover device, and the time of response is difficult to control because of the inherent defect of non-ideal effects or detection method fast, therefore, the present invention proposes the concluding time that a kind of method is blured quick response.
Now see also Fig. 5, Fig. 5 shows the embodiments of the invention schematic diagram, as shown in the figure, in the described 4 phase switch type power converters 70, error amplifier 78 produces error signal Vcomp according to the reference voltage Vref that output voltage V core and the reference voltage generator 76 of power supply changeover device 70 provides, sawtooth generator 80 provides sawtooth waveforms Vramp1, Vramp2, Vramp3 and Vramp4, PWM comparator 82 produces signal Vpwm1 with control channel 90 according to error signal Vcomp and sawtooth waveforms Vramp1, PWM comparator 84 produces signal Vpwm2 with control channel 92 according to error signal Vcomp and sawtooth waveforms Vramp2, PWM comparator 86 produces signal Vpwm3 with control channel 94 according to error signal Vcomp and sawtooth waveforms Vramp3, PWM comparator 88 produces signal Vpwm4 with control channel 96 according to error signal Vcomp and sawtooth waveforms Vramp4, testing circuit 72 detects output voltage V core, it comprises that current source 7202 provides electric current I qr to be offset output voltage V core to resistance R qr with generation voltage Vofs and produces voltage Vcf, comparator 7204 comparative voltage Vcf and reference voltage Vref produce quick response signal Vqr, when voltage Vcf is lower than reference voltage Vref, signal Vqr transfers high levle to trigger quick response, because testing circuit 72 is directly to detect output voltage V core, therefore can trigger quick response accurately, when triggering response fast, regulating circuit 74 is sent signal VQR1, VQR2, VRQ3 and VQR4 are to open passage 90,92, in 94 and 96 at least two, during described quick response, regulating circuit 74 will increase in time and reduce the quantity of the passage of opening, and then reduce the electric charge that injects output Vcore.
See also Fig. 6 again, Fig. 6 shows the first embodiment schematic diagram of regulating circuit 74, as shown in the figure, comprise two control circuits 7402 and 7404, in the described control circuit 7402, the minimum operating time produces circuit 7406 and produces quick response signal QR_all according to signal Vqr, drive circuit 7408 is opened all passages 90 in the operating time of signal QR_all, 92,94 and 96, in control circuit 7404, the minimum operating time produces circuit 7410 and produces quick response signal QR_3rd according to signal Vqr, and drive circuit 7412 is opened passage 90 in the operating time of signal QR_3rd, 92,94 and 96 wherein three.Fig. 7 is in order to the operation of regulating circuit 74 in the key diagram 6, when time t1, the signal Vqr that testing circuit 72 is exported transfers high levle to, shown in waveform 108, the minimum operating time produces circuit 7406 and 7410 and sends quick response signal QR_all and QR_3rd simultaneously respectively, shown in waveform 110 and 112, wherein, the operating time Ton1 of signal QR_all is less than the operating time Ton2 of signal QR_3rd, and therefore, whole quick response was divided into for two stages, during time t1 to t2, signal VQR1, VQR2, VRQ3 and VQR4 are high levle, as waveform 100,102, shown in 104 and 106, so all passages 90,92,94 and 96 all are opened, during time t2 to t3, only open three passages 92,94 and 96, inject the electric charge of output Vcore with minimizing, and then suppress rebound phenomenon.The quick response end point of equivalence is between time t2 and t3, because fast the response end point is by fuzzy, therefore the accurate demand of quick response end point also being become is not very important.In this embodiment, drive circuit 7412 is set at opens three passages simultaneously, but in other embodiments, also can set 7412 of drive circuits and open two or a passage.
For N phase switch type power converter, it can be divided into the N stage with responding fast at most, and the stage is more many, and end point is just more fuzzy, also more can suppress rebound phenomenon.Fig. 8 shows the second embodiment schematic diagram of regulating circuit 74, it is except comprising control circuit 7402 and 7404 equally, also comprise control circuit 7414, in control circuit 7414, the minimum operating time produces circuit 7416 and produces quick response signal QR_2nd according to signal Vqr, and drive circuit 7418 is opened wherein two in passage 90,92,94 and 96 in the operating time of signal QR_2nd.Fig. 9 shows the oscillogram of signal among Fig. 8, and wherein waveform 114 is quick response signal Vqr, and waveform 116 is quick response signal QR_all, and waveform 118 is quick response signal QR_3rd, and waveform 120 is quick response signal QR_2nd.When time t1, signal Vqr transfers high levle to, the minimum operating time produces circuit 7406,7410 and 7416 provide signal QR_all respectively, QR_3rd and QR_2nd, wherein the operating time Ton2 of signal QR_3rd is greater than the operating time Ton1 of QR_all, the operating time Ton3 of signal QR_2nd is greater than the operating time Ton2 of signal QR_3rd, therefore, in this embodiment, whole quick response is divided into three phases, during time t1 to t2, all all passages 90,92,94 and 96 all are opened, during time t2 to t3, only open passage 90,92, in 94 and 96 three during time t3 to t4, only open passage 90,92, in 94 and 96 two.By previous embodiment as can be known, the operating time that produces the signal that circuit provides when the minimum operating time is more long, and the number of channels of opening is just more few.
In drive circuit 7408,7412 and 7418, respectively comprise the passage of a default pattern when signal QR_all, QR_3rd and QR_2nd transfer high levle to, to determine to open.The embodiment schematic diagram of default pattern in Figure 10 display driver circuit 7408, in this default pattern, comprise four signal S1, S2, S3 and S4 be respective channel 90 respectively, 92,94 and 96, as waveform 122,124, shown in 126 and 128, when signal QR_all transfers high levle to, as time t1, drive circuit 7408 is with the signal S1 of this moment, S2, S3 and S4 send to open passage 90,92,94 and 96, because four signal S1, S2, S3 and S4 are high levle at any time, no matter be when to trigger quick response therefore, drive circuit 7408 all will be opened whole passage 90,92,94 and 96.The embodiment schematic diagram of default pattern in Figure 11 display driver circuit 7412, in this default pattern, comprise four signal S5, S6, S7 and S8 be respective channel 90 respectively, 92,94 and 96, as waveform 130,132, shown in 134 and 136, because at any time, four signal S5, S6, there are three among S7 and the S8 and maintain high levle, when trigger quick response as signal QR_3rd no matter therefore be, drive circuit 7412 can be opened channel 90,92,94 and 96 wherein three, for example when time t1, signal S5, S7 and S8 are high levle, if when therefore triggering response fast at this moment, drive circuit 7412 will be opened channel 90,94 and 96.The embodiment schematic diagram of default pattern in Figure 12 display driver circuit 7418, in this default pattern, comprise four signal S9, S10, S11 and S12 be respective channel 90 respectively, 92,94 and 96, as waveform 138,140, shown in 142 and 144, because at any time, four signal S9, S10, there are two among S11 and the S12 and maintain high levle, when trigger quick response as signal QR_2nd no matter therefore be, drive circuit 7418 can be opened channel 90,92,94 and 96 wherein two, for example when time t1, signal S9 and S12 are high levle, if when therefore triggering response fast at this moment, drive circuit 7418 will be opened channel 90 and 96.
See also Figure 13 and Figure 14 at last, Figure 13 shows the embodiment schematic diagram of minimum operating time generation circuit 7406, and Figure 14 shows the oscillogram of signal among Figure 13.As shown in the figure, when the signal Vqr on the input C of described flip-flop 146 transfers high levle to, shown in waveform 154 and time t1, response signal QR_all will transfer high levle to fast, shown in waveform 162, signal Vg on the output QB of flip-flop 146 will transfer low level to close (turn off) switch 148 simultaneously, shown in waveform 156, therefore current source 150 provides electric current I 1 pair of capacitor C charging, so the voltage Vc on the capacitor C begins to rise, shown in waveform 158, between the voltage Vc rising stage, because the signal SL1 that flip-flop 146 is exported maintains high levle, therefore signal QR_all also maintains high levle, when voltage Vc reaches desired value Vtrip, shown in time t2, inverter 152 will be sent the signal of low level, thereby make reset signal Sreset transfer high levle to replacement flip-flop 146, shown in waveform 160, so signal QR_all transfers low level to, and synchronous signal Vg also transfers high levle to open (turn on) switch 152 so that the capacitor C discharge.The minimum operating time produces circuit 7410 and 7416 also as shown in figure 13.
Above embodiment is only for the usefulness that the present invention is described, but not limitation of the present invention, person skilled in the relevant technique under the situation that does not break away from the spirit and scope of the present invention, can also be made various conversion or variation.Therefore, all technical schemes that are equal to also should belong to category of the present invention, should be limited by each claim.
The element numbers explanation
10 power supply changeover devices
12 reference voltage generators
14 error amplifiers
16 sawtooth generators
18 PWM comparators
20 PWM comparators
22 passages
24 passages
The waveform of 26 output voltage V core
The waveform of 28 sawtooth waveforms Vramp1
The waveform of 30 sawtooth waveforms Vramp2
The waveform of 32 error signal Vcomp
The waveform of 34 signal Vpwm1
The waveform of 36 signal Vpwm1
40 adapt to the phase alignment circuit
42 error amplifiers
44 low pass filters
46 comparators
48 current sources
The waveform of 50 quick response signal QR
The waveform of 52 signal Vpwm1
The waveform of 54 signal Vpwm2
The waveform of 56 signal Vpwm3
The waveform of 58 signal Vpwm4
The waveform of 60 output voltage V core
70 power supply changeover devices
72 testing circuits
7202 current sources
7204 comparators
74 regulating circuits
7402 control circuits
7404 control circuits
7406 minimum operating times produced circuit
7408 drive circuits
7410 minimum operating times produced circuit
7412 drive circuits
7414 control circuits
7416 minimum operating times produced circuit
7418 drive circuits
76 reference voltage generators
78 error amplifiers
80 sawtooth generators
82 PWM comparators
84 PWM comparators
86 PWM comparators
88 PWM comparators
90 passages
92 passages
94 passages
96 passages
The waveform of 100 signal VQR1
The waveform of 102 signal VQR2
The waveform of 104 signal VQR3
The waveform of 106 signal VQR4
The waveform of 108 quick response signal Vqr
The waveform of 110 quick response signal QR_all
The waveform of 112 quick response signal QR_3rd
The waveform of 114 quick response signal Vqr
The waveform of 116 quick response signal QR_all
The waveform of 118 quick response signal QR_3rd
The waveform of 120 quick response signal QR_2nd
The waveform of 122 signal S1
The waveform of 124 signal S2
The waveform of 126 signal S3
The waveform of 128 signal S4
The waveform of 130 signal S5
The waveform of 132 signal S6
The waveform of 134 signal S7
The waveform of 136 signal S8
The waveform of 138 signal S9
The waveform of 140 signal S10
The waveform of 142 signal S11
The waveform of 144 signal S12
146 flip-flops
148 switches
150 current sources
152 inverters
The waveform of 154 quick response signal Vqr
The waveform of 156 signal Vg
The waveform of 158 voltage Vc
The waveform of 160 reset signal Sreset
The waveform of 162 quick response signal QR_all
Claims (7)
1. the quick response device of a switch type power converter comprises a testing circuit and a regulating circuit, and described switch type power converter comprises a plurality of passages so that an output voltage to be provided, and it is characterized in that:
Described testing circuit detects described output voltage, triggers response fast when load instantaneous takes place;
Described regulating circuit is opened at least two in described a plurality of passage when described quick response triggers, and increases the quantity that reduces the passage of opening along with the time;
Wherein, described regulating circuit comprises a plurality of control circuits, and each described control circuit comprises:
One minimum operating time produced circuit, when described quick response is triggered, provided a quick response signal;
One drive circuit, open the quantity of described a plurality of passages according to the operating time decision of described quick response signal, open in described a plurality of passage at least one in the operating time of described quick response signal, and the quantity difference of the passage that each described control circuit is opened, the operating time of described quick response signal is more long, and the quantity of the passage of opening is more few.
2. quick response device as claimed in claim 1 is characterized in that, described testing circuit comprises:
One resistance;
One current source provides an electric current to described resistance to obtain one second voltage to produce one first voltage in order to be offset described output voltage;
One comparator, more described second voltage and a tertiary voltage trigger described quick response to produce one second quick response signal.
3. quick response device as claimed in claim 1 is characterized in that, the described minimum operating time produces circuit and comprises:
One electric capacity;
One current source when triggering response fast, provides an electric current that described electric capacity is charged;
One logical circuit determines described quick response signal according to output and the voltage on the described electric capacity of described testing circuit.
4. quick response device as claimed in claim 1 is characterized in that, described drive circuit comprises a default pattern, and described drive circuit determines the passage that will open according to described default pattern and quick response signal.
5. the fast response method of a switch type power converter, described switch type power converter comprises a plurality of passages so that an output voltage to be provided, and it is characterized in that, comprises the following steps:
First step: detect described output voltage, when taking place, load instantaneous triggers response fast, at this moment, open at least two in described a plurality of passage, described at least two the step of opening in described a plurality of passage is included in described quick response when triggering, a plurality of signals with different operating time are provided simultaneously, and each described signal is in order to opening at least one in described a plurality of passage, and the quantity difference of the passage opened of each described signal;
Second step: during described quick response, increase the quantity that reduces the passage of opening along with the time, the described step that increase to reduce the quantity of the passage of opening along with the time comprises the quantity that determines the passage that each described signal will be opened according to the operating time length of each described signal, wherein the operating time more long, the quantity of the passage of opening is more few.
6. fast response method as claimed in claim 5 is characterized in that, the step of the described output voltage of described detection comprises:
First step: be offset described output voltage and produce an offset voltage;
Second step: when described offset voltage is lower than a reference voltage, trigger described quick response.
7. fast response method as claimed in claim 5 is characterized in that, more comprises according to each described signal and corresponding default pattern thereof determining the passage that will open.
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| CN 200810125925 CN101599693B (en) | 2008-06-04 | 2008-06-04 | Quick response device and method of switching power converter |
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| CN102136793B (en) * | 2010-01-21 | 2014-12-03 | 立锜科技股份有限公司 | Frequency generator and phase interleaving frequency synchronization device and method |
| JP5864220B2 (en) * | 2011-11-11 | 2016-02-17 | ルネサスエレクトロニクス株式会社 | Semiconductor integrated circuit |
| TW201445858A (en) * | 2013-05-16 | 2014-12-01 | Upi Semiconductor Corp | Timing generator and timing signal generation method for power converter |
| US9882472B2 (en) | 2014-09-25 | 2018-01-30 | Intel Corporation | Techniques for power supply topologies with capacitance management to reduce power loss associated with charging and discharging when cycling between power states |
| TWI548194B (en) * | 2015-01-22 | 2016-09-01 | Richtek Technology Corp | A control circuit and a method for programming the output voltage of the power converter |
| TWI835200B (en) * | 2022-01-26 | 2024-03-11 | 立錡科技股份有限公司 | Quick response switching power converter and conversion control circuit thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6359796B2 (en) * | 2000-07-28 | 2002-03-19 | 02 Micro International Ltd. | Transient control for converter power supplies |
| CN1477775A (en) * | 2002-07-25 | 2004-02-25 | 株式会社理光 | Power supply method and electric source equipment capable of fast responsing input and output voltage change |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6359796B2 (en) * | 2000-07-28 | 2002-03-19 | 02 Micro International Ltd. | Transient control for converter power supplies |
| CN1477775A (en) * | 2002-07-25 | 2004-02-25 | 株式会社理光 | Power supply method and electric source equipment capable of fast responsing input and output voltage change |
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