CN107039504A - A kind of high hot carrier reliability lateral insulated gate bipolar device - Google Patents
A kind of high hot carrier reliability lateral insulated gate bipolar device Download PDFInfo
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- CN107039504A CN107039504A CN201710168125.9A CN201710168125A CN107039504A CN 107039504 A CN107039504 A CN 107039504A CN 201710168125 A CN201710168125 A CN 201710168125A CN 107039504 A CN107039504 A CN 107039504A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 19
- 229920005591 polysilicon Polymers 0.000 claims abstract description 19
- 238000000407 epitaxy Methods 0.000 claims abstract description 12
- 210000003323 beak Anatomy 0.000 claims abstract description 10
- 230000003139 buffering effect Effects 0.000 claims abstract description 8
- 239000000758 substrate Substances 0.000 claims abstract description 8
- 239000002184 metal Substances 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 15
- 238000000034 method Methods 0.000 claims description 8
- 238000002161 passivation Methods 0.000 claims description 5
- 230000008569 process Effects 0.000 claims description 5
- 230000005684 electric field Effects 0.000 abstract description 10
- 238000010276 construction Methods 0.000 abstract 1
- 230000015556 catabolic process Effects 0.000 description 8
- 238000006731 degradation reaction Methods 0.000 description 6
- 238000009825 accumulation Methods 0.000 description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 4
- 230000000694 effects Effects 0.000 description 4
- 238000002347 injection Methods 0.000 description 4
- 239000007924 injection Substances 0.000 description 4
- 229910052760 oxygen Inorganic materials 0.000 description 4
- 239000001301 oxygen Substances 0.000 description 4
- 230000009467 reduction Effects 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 230000008901 benefit Effects 0.000 description 3
- 238000009826 distribution Methods 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 2
- -1 phosphonium ion Chemical class 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 230000007850 degeneration Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 238000000605 extraction Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052738 indium Inorganic materials 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 230000007246 mechanism Effects 0.000 description 1
- 238000004377 microelectronic Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 230000024241 parasitism Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7393—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET
- H01L29/7394—Insulated gate bipolar mode transistors, i.e. IGBT; IGT; COMFET on an insulating layer or substrate, e.g. thin film device or device isolated from the bulk substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
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- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Thyristors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
A kind of high reliability lateral insulated gate bipolar device, including：P type substrate, buries oxide layer is provided with P type substrate, N-type epitaxy layer is provided with buries oxide layer, in the inside of N-type epitaxy layer provided with N-type buffering Jing HePXing Ti areas, PXing Yang areas are provided with N-type buffering trap, NXing Yin areas and p-type body contact zone are provided with PXing Ti areas, gate oxide and field oxide are provided with the surface of N-type epitaxy layer, polysilicon gate is provided with the surface of gate oxide and extends to field oxide, polysilicon is provided with the right upper of field oxide, it is characterized in that being additionally arranged additional p-type area below at the beak, the ionization by collision that raceway groove electric field reduces channel region is shielded by additional p-type area, therefore new construction device reduces the hot carrier damage of device ON state working stage, extend the life-span of device.
Description
Technical field
It is a kind of effectively reduction specifically the invention mainly relates to the reliability field of high voltage power semiconductor device
Hot carrier damage, improves hot carrier in jection characteristic, improves a kind of transverse direction of high hot carrier reliability of device reliability
Insulated gate bipolar device.Suitable for avionics equipment, satellite communication equipment, plasma display equipment, electronic computer,
The thick film driver IC such as communication system, auto industry.
Background technology
The reliability of integrated circuit is exactly focal issue of concern from integrated circuit is born, wherein hot carry
Stream injection (Hot Carrier Injection, HCI) effect is exactly a very important integrity problem, is also to cause
The one of the main reasons of many electronic product failures.With the increasingly enhancing of energy saving requirement, high-voltage power integrated circuit product
Reliability is received more and more attention, because power integrated circuit is usually operated under conditions of high temperature, high pressure, high current,
The security risk that thus it faces is more than custom integrated circuit sternness.With the reduction of microelectronic technique line width, power
The circuit malfunction that the hot carrier's effect of device is caused has turned into restricts the bottleneck that power integrated circuit further develops, thus with
The research that the HCI characteristics of power device are relevant also turns into the most important thing that researcher pays close attention to.
Lateral insulated gate bipolar device (Lateral Insulated Gate Bipolar Transistor, LIGBT)
With reference to MOS (Metal Oxide Semiconductor) high input impedance and the advantage of bipolar device conductance modulation,
Solve lateral double-diffused metal-oxide semiconductor device (Lateral Double Diffused Metal Oxide
Semiconductor, LDMOS) breakdown voltage and conducting resistance contradiction, it is and compatible with standard CMOS process good, plus
Silicon (Silicon-On-Insulator, SOI) technique isolation effect is good on upper insulating thick film body, capability of resistance to radiation is strong and parasitism is joined
The advantages of number is small, therefore thick film SOI-LIGBT devices receive the favor of power integrated circuit, in high-voltage power integrated circuit
It is widely used, one of core parts as following smart-power IC.
In view of there are the two strands of electric currents in hole and electronics in ON state working stage body in thick film SOI-LIGBT devices, relative to
LDMOS has more complicated carrier and Electric Field Distribution, so hot carrier degradation problem is severe.Research discovery, thick film SOI-
The worst HCI stress of LIGBT devices is that the HCI under high grid voltage stress, the worst stress degenerates mainly by device channel region
Interfacial state is produced and thermoelectron injection is leading, i.e., hot carrier damage now is essentially from the high grid of ON state working stage device
The damage in voltage conditions lower channel area, so reduction device channel region transverse electric field can effectively reduce ionization by collision and reduce device
The hot carrier degradation of part, improves device reliability.Therefore, coming we have proposed a kind of device architecture with additional p-type area
Raceway groove electric field is shielded, reduces the hot carrier degradation of device by reducing the transverse electric field of channel region, is not changing chip area
Do not increase processing step and do not influence to significantly improve device HCI reliabilities on the premise of device performance.
The content of the invention
The present invention provides a kind of high hot carrier reliability lateral insulated gate bipolar device.
The present invention is adopted the following technical scheme that：
A kind of high hot carrier reliability lateral insulated gate bipolar device, including：P type substrate, is provided with P type substrate
Oxygen is buried, N-type epitaxy layer is provided with oxygen is buried, N-type buffering area and PXing Ti areas are provided with the inside of N-type epitaxy layer, in N-type buffering
PXing Yang areas are provided with area, NXing Yin areas and p-type body contact zone are provided with PXing Ti areas, grid oxygen is provided with the surface of N-type epitaxy layer
The one end for changing one end and field oxide of layer and field oxide and gate oxide offsets, and the other end of the gate oxide is to N-type
Cloudy area extends and terminates in the border in NXing Yin areas, and the other end of the field oxide extends to PXing Yang areas and terminates in PXing Yang areas
Border, the upper surface of field oxide, oxygen on the scene are extended to provided with polysilicon gate and polysilicon gate on the surface of the gate oxide
Change floor, p-type body contact zone, NXing Yin areas, polysilicon gate, the surface in PXing Yang areas provided with passivation layer, be connected with PXing Yang areas surface
First metal electrode, the second metal electrode is connected with the surface of polysilicon gate, and the 3rd metal electricity is connected with NXing Yin areas surface
Pole, the 4th metal electrode is connected with p-type body contact zone surface, at the beak that gate oxide connects with field oxide below also
Provided with an extra p type island region.
Compared with prior art, the invention has the advantages that：
(1), device of the present invention at the beak below be additionally arranged additional p-type area 12, in the state of device anode adds high pressure,
The additional p-type area 12 will exhaust and negative space charge is provided in the region, realize the pressure-resistant effect in similar PXing Ti areas, subtract
The pressure-resistant burden in QingPXing Ti areas 18, by a part of electric field shielding beyond channel region.Device channel of the present invention as shown in Figure 3,4
The transverse electric field in area is obviously reduced and surface current density is not changed significantly, and device transverse electric field reduction nature causes device
Channel region impact ionization rate reduces, so as to reduce the HCI damages of device ON state working stage.Fig. 5,6 be device of the present invention and
Traditional devices HCI, which degenerates, compares figure, it is seen that device of the present invention is identical with the HCI degradation trends of traditional devices, and this explanation is originally
The degradation mechanism of invention device is identical with traditional devices, but its amount of degradation is significantly less than traditional devices.
(2), device of the present invention is set up at beak behind additional p-type area, protects the beak of device, so that anode is high
Will not be breakdown because of longitudinal electric field big between anode and grid caused by accumulation area increase at beak under the conditions of pressure.So
Accumulation area can be greatly increased, and the increase of accumulation area as shown in Figure 7,8 can make the I of deviceasat(anode film electric current) and Vth(threshold
Threshold voltage) degeneration substantially reduce.
(3), device of the present invention does not bring subtracting for current capacity while can be obviously improved hot carrier characteristic
It is small, as shown in figure 9, device of the present invention has identical saturation current ability with traditional devices, it is seen that although additional p-type area takes
Device a part of drift region, but do not influence its current capacity.On the contrary, as shown in figure 9, also as having protection at beak
Increase device linearity electric current after accumulation area increase.
(4), device of the present invention changes device original chip area while device reliability is improved, not, also not
The extra processing step of increase, so extra cost will not be increased, while the manufacture craft of device of the present invention can with it is existing
Standard CMOS process is completely compatible, it is easy to prepare.
Brief description of the drawings
Fig. 1 is profile (contain passivation layer and metal level) of the traditional devices along AA ' faces.
Fig. 2 is profile (contain passivation layer and metal level) of the device of the present invention along BB ' faces.
Fig. 3 is that device of the present invention is compared figure with traditional devices channel region transverse electric field distribution.
Fig. 4 is that device of the present invention is compared figure with traditional devices channel region electric current distribution.
Fig. 5 is device of the present invention and traditional devices anode film electric current IasatDegeneration results contrast figure.
Fig. 6 is device of the present invention and traditional devices threshold voltage VthDegeneration results contrast figure.
Fig. 7 is the different anode film electric current I for accumulating section length SOI-LIGBT devicesasatDegenerate Graphs
Fig. 8 is the different threshold voltage V for accumulating section length SOI-LIGBT devicesthDegenerate Graphs
Fig. 9 is device of the present invention and traditional devices current capacity IasatCompare figure.
Embodiment
Below in conjunction with the accompanying drawings 2, the present invention is elaborated, a kind of high hot carrier reliability landscape insulation bar double-pole-type
Device, including：P type substrate 1, is provided with buries oxide layer 2 in P type substrate 1, N-type epitaxy layer 3 is provided with buries oxide layer 2, in N
The inside of type epitaxial layer 3 is provided with N-type buffering area 4 and PXing Ti areas 18, PXing Yang areas 5 is provided with N-type buffering area 4, in PXing Ti areas
NXing Yin areas 15 and p-type body contact zone 17 are provided with 18, gate oxide 13 and field oxide 9 are provided with the surface of N-type epitaxy layer 3
And one end of gate oxide 13 and one end of field oxide 9 offset, the other end of the gate oxide 13 extends to NXing Yin areas 15
And the border in NXing Yin areas 15 is terminated in, the other end of the field oxide 9 extends to PXing Yang areas 5 and terminates in the side in PXing Yang areas 5
Boundary, the surface of field oxide 9, oxidation on the scene are extended to provided with polysilicon gate 10 and polysilicon gate 10 on the surface of gate oxide 13
Floor 9, p-type body contact zone 17, NXing Yin areas 15, polysilicon gate 10, the surface in PXing Yang areas 5 are provided with passivation layer 6, in the He of PXing Yang areas 5
The surface of polysilicon 8 is connected with the first metal electrode 7, and the second metal electrode 11 is connected with the surface of polysilicon gate 10, cloudy in N-type
The surface of area 15 is connected with the 3rd metal electrode 14, is connected to the 4th metal electrode 16 on the surface of p-type body contact zone 17, its feature exists
In, at the beak that gate oxide 13 connects with field oxide 9 below be additionally provided with an extra p type island region 12.
The length of additional p-type area 12 is 3.5~4.5 μm, and apart from 182~3 μm of PXing Ti areas.
The additional p-type area 12 is injected with PXing Ti areas 18 in same process, shares one piece of mask plate.
The present invention adopts with the following method to prepare：
It is that SOI makes first, its epitaxial layers 3 uses n-type doping.Ensuing is lateral insulated gate bipolar device
Make, be included in N-type epitaxy layer 3 by injecting phosphonium ion formation N-type buffering area 4, the He of injection boron ion formation PXing Ti areas 18
Additional p-type area 13, wherein additional p-type area 13 and PXing Ti areas 18 are injected in same process, share one piece of mask plate, followed by
Field oxide 9, followed by the growth of gate oxide 13, depositing polysilicon grid 10, etch and form grid, then make heavy doping afterwards
PXing Yang areas 5, p-type body contact zone 17, and then NXing Yin areas 15 deposit silica, and etching electrode contact deposits gold behind area
Category, then metal and extraction electrode are etched, finally it is passivated processing.
Claims (4)
1. a kind of high hot carrier reliability lateral insulated gate bipolar device, including：P type substrate (1), in P type substrate (1)
Provided with buries oxide layer (2), N-type epitaxy layer (3) is provided with buries oxide layer (2), it is slow provided with N-type in the inside of N-type epitaxy layer (3)
Area (4) and PXing Ti areas (18) are rushed, PXing Yang areas (5) are provided with N-type buffering area (4), it is cloudy provided with N-type in PXing Ti areas (18)
Area (15) and p-type body contact zone (17), gate oxide (13) and field oxide (9) are provided with the surface of N-type epitaxy layer (3), and
One end of gate oxide (13) and one end of field oxide (9) offset, and the other end of the gate oxide (13) is to NXing Yin areas
(15) extend and terminate in the border of NXing Yin areas (15), the other end of the field oxide (9) extends and terminated in PXing Yang areas (5)
The border of the PXing Yang areas (5), is provided with polysilicon gate (10) on the surface of gate oxide (13) and the polysilicon gate (10) prolongs
Extending has polysilicon (8) and the polysilicon (8) and p-type sun on the upper surface of field oxide (9), the surface of field oxide (9)
Area (5) is adjacent, in field oxide (9), p-type body contact zone (17), NXing Yin areas (15), polysilicon gate (10), PXing Yang areas (5)
Surface is provided with passivation layer (6), the first metal electrode (7) is connected with PXing Yang areas (5) and polysilicon (8) surface, in polysilicon gate
(10) surface is connected with the second metal electrode (11), the 3rd metal electrode (14) is connected with NXing Yin areas (15) surface, in P
Type body contact zone (17) surface is connected with the 4th metal electrode (16), it is characterised in that in gate oxide (13) and field oxide
(9) lower section is additionally provided with an extra p type island region (12) at the beak connected.
2. high hot carrier reliability lateral insulated gate bipolar device according to claim 1, it is characterised in that described
Additional p-type area (12) is distributed in area size's approximately equal on both sides at beak.
3. high hot carrier reliability lateral insulated gate bipolar device according to claim 1, it is characterised in that described
Additional p-type area (12) length is 3.5~4.5 μm, and apart from (18) 2~3 μm of PXing Ti areas.
4. high hot carrier reliability lateral insulated gate bipolar device according to claim 1, it is characterised in that described
Additional p-type area (12) and PXing Ti areas (18) are injected in same process, share one piece of mask plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710168125.9A CN107039504A (en) | 2017-03-20 | 2017-03-20 | A kind of high hot carrier reliability lateral insulated gate bipolar device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710168125.9A CN107039504A (en) | 2017-03-20 | 2017-03-20 | A kind of high hot carrier reliability lateral insulated gate bipolar device |
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| CN201710168125.9A Pending CN107039504A (en) | 2017-03-20 | 2017-03-20 | A kind of high hot carrier reliability lateral insulated gate bipolar device |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110047920A (en) * | 2019-04-16 | 2019-07-23 | 西安电子科技大学 | A kind of horizontal junction grid bipolar transistor and preparation method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437181A (en) * | 2011-12-08 | 2012-05-02 | 东南大学 | N type silicon on insulator transverse insulated gate bipolar device |
| CN106298901A (en) * | 2016-10-10 | 2017-01-04 | 东南大学 | A kind of landscape insulation bar double-pole-type transistor of high hot carrier reliability |
-
2017
- 2017-03-20 CN CN201710168125.9A patent/CN107039504A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102437181A (en) * | 2011-12-08 | 2012-05-02 | 东南大学 | N type silicon on insulator transverse insulated gate bipolar device |
| CN106298901A (en) * | 2016-10-10 | 2017-01-04 | 东南大学 | A kind of landscape insulation bar double-pole-type transistor of high hot carrier reliability |
Non-Patent Citations (1)
| Title |
|---|
| 张春伟: "550V厚膜SOI-LIGBT器件可靠性研究", 《中国博士学位论文全文数据库信息科技辑》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110047920A (en) * | 2019-04-16 | 2019-07-23 | 西安电子科技大学 | A kind of horizontal junction grid bipolar transistor and preparation method thereof |
| CN110047920B (en) * | 2019-04-16 | 2021-06-18 | 西安电子科技大学 | Transverse junction type gate bipolar transistor and manufacturing method thereof |
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