CN107039353A - A kind of array base palte and preparation method thereof - Google Patents
A kind of array base palte and preparation method thereof Download PDFInfo
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- CN107039353A CN107039353A CN201710266728.2A CN201710266728A CN107039353A CN 107039353 A CN107039353 A CN 107039353A CN 201710266728 A CN201710266728 A CN 201710266728A CN 107039353 A CN107039353 A CN 107039353A
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- insulating barrier
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
- H01L27/1274—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor
- H01L27/1281—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement using crystallisation of amorphous semiconductor or recrystallisation of crystalline semiconductor by using structural features to control crystal growth, e.g. placement of grain filters
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
Abstract
The invention provides a kind of array base palte and preparation method thereof.Methods described includes：Amorphous silicon layer is formed on underlay substrate, wherein, underlay substrate includes pixel region and peripheral driver area；Antireflection film is formed on the amorphous silicon layer in peripheral driver area；The crystallite dimension that polysilicon layer in crystallization treatment formation polysilicon layer, peripheral driver area is carried out to amorphous silicon layer is more than the crystallite dimension of polysilicon layer in pixel region；Remove antireflection film；Patterned process is carried out to polysilicon layer, the first polysilicon active layer positioned at pixel region and second polysilicon active layer in peripherally located driving area is correspondingly formed；The first insulating barrier, grid, the second insulating barrier, source electrode and drain electrode are sequentially formed in the first polysilicon active layer and the second polysilicon active layer, array base palte is obtained.Setting of the invention based on antireflection film, increases the crystallite dimension of the polysilicon layer in the peripheral driver area of polycrystalline SiTFT, improves the drive efficiency of array base palte.
Description
Technical field
The present invention relates to display technology field, more particularly to a kind of array base palte and preparation method thereof.
Background technology
Low temperature polycrystalline silicon (Low temperature poly-silicon, abbreviation LTPS) Thin Film Transistor-LCD
Traditional amorphous silicon thin film transistor-liquid crystal display is different from, its electron mobility can reach more than 200cm2/V-sec,
The area of film transistor device can be effectively reduced, the aperture opening ratio of display is improved, may be used also while display brightness is promoted
To reduce the overall power of display.Further, since LTPS thin film transistor (TFT)s have higher electron mobility, therefore can be by
The section driving circuit of LTPS thin film transistor (TFT)s is integrated on the glass substrate, so that the space shared by drive circuit is saved,
The reliability of liquid crystal display panel is significantly improved, the manufacturing cost of liquid crystal display panel is reduced.
The process of currently manufactured low-temperature polysilicon film transistor mainly includes being excited without using the traditional of mask
Quasi-molecule laser annealing method (ELA) and the continuous side crystallization method (SLS) that laser-irradiated domain is controlled using mask.Adopt
During with traditional ELA methods, the crystallite dimension for obtaining low temperature polycrystalline silicon is generally below 0.1um；During using SLS methods, crystallization
Change process is internally induced by the end of irradiation area, is finally just irradiated the crystallization in regional center portion, in crystallization
When changing the temperature being in during carrying out below fusing point, if the temperature drop of central part, nucleation can be carried out, causing to obtain
Big crystal grain.
It can be seen that, the crystallite dimension of the polysilicon manufactured using above two process is smaller, low-temperature polysilicon film
When transistor works, the little crystallite size of polysilicon, which limits peripheral drive circuit, can only obtain less electron mobility, enter
And limiting peripheral drive circuit has low drive efficiency.
The content of the invention
The technical problem to be solved in the present invention is to provide a kind of array base palte, the crystal grain of the polysilicon in increase peripheral driver area
Size, improves the drive efficiency in peripheral driver area, improves the drive efficiency of array base palte.
On the one hand there is provided a kind of preparation method of array base palte, methods described includes：
Amorphous silicon layer is formed on underlay substrate, wherein, the underlay substrate includes pixel region and peripheral driver area；
Antireflection film is formed on the amorphous silicon layer in the peripheral driver area；
The crystal grain of polysilicon layer in crystallization treatment formation polysilicon layer, the peripheral driver area is carried out to the amorphous silicon layer
Size is more than the crystallite dimension of polysilicon layer in the pixel region；
Remove the antireflection film；
Patterned process is carried out to the polysilicon layer, the first polysilicon active layer positioned at the pixel region is correspondingly formed
With the second polysilicon active layer positioned at the peripheral driver area；
The first insulating barrier, grid are sequentially formed in first polysilicon active layer and second polysilicon active layer
Pole, the second insulating barrier, source electrode and drain electrode, obtain the array base palte.
Further, the crystallization treatment formation polysilicon layer that carried out to the amorphous silicon layer includes：
Crystallization treatment is carried out to the amorphous silicon layer using quasi-molecule laser annealing method or solid-phase crystallization method.
Further, the thickness of the antireflection film is directly proportional to the wavelength of the laser, with the antireflection film
Refractive index be inversely proportional.
Further, the thickness of the antireflection film is the wavelength and the antireflection film refractive index of the laser
The a quarter of ratio.
Further, the refractive index of the antireflection film is the folding for being located at the amorphous silicon layer below the antireflection film
Penetrate the geometric average of refractive index of the rate with subtracting gas phase media during transmitting film above the antireflection film described in formation
Value.
Further, the material of the antireflection film is one of following：
Alundum (Al2O3), silica, bifluoride magnesium or silicon nitride.
Further, the shape successively on the first polysilicon layer active layer and the second polysilicon layer active layer
Into the first insulating barrier, grid, the second insulating barrier, source electrode and drain electrode, obtaining the array base palte includes：
The first insulating barrier is formed, wherein, first insulating barrier covers the first polysilicon layer active layer and described the
Two polysilicon layer active layers；
Patterning forms the first grid that is located in the pixel region and positioned at described outer on first insulating barrier
Enclose the second grid in drive area；
The second insulating barrier is formed, wherein, second insulating barrier covers the first grid and the second grid；
Source electrode via and drain via are made on first insulating barrier and second insulating barrier, in the source electrode mistake
The first source electrode formed in hole and the drain via in the pixel region and the first drain electrode and the peripheral driver region
The second interior source electrode and the second drain electrode.
On the other hand, a kind of array base palte prepared according to the preparation method of above-mentioned array base palte is additionally provided, it is described
Array base palte includes being formed at the pixel polycrystalline SiTFT being located in pixel region and peripherally located drive on underlay substrate
Driving polycrystalline SiTFT in dynamic area；
It is many that the crystallite dimension of the first polysilicon active layer in the pixel polycrystalline SiTFT is less than the driving
The crystallite dimension of the second polysilicon active layer in polycrystal silicon film transistor.
Further, the pixel polycrystalline SiTFT is additionally included in the pixel region on the underlay substrate Nei and is laminated
The first polysilicon active layer, the first insulating barrier, first grid and the second insulating barrier set, and formed in source electrode via
The source electrode via and the drain via in first source electrode and the first drain electrode formed in drain via, the pixel region
First insulating barrier and second insulating barrier described in equal insertion in pixel region.
Further, the driving polycrystalline SiTFT is additionally included in the peripheral driver area on the underlay substrate
The second polysilicon active layer, the first insulating barrier, second grid and the second insulating barrier being stacked, and formed in source electrode via
The source electrode via in interior the second source electrode and the second drain electrode formed in drain via, the peripheral driver area and described
First insulating barrier and second insulating barrier described in the equal insertion of drain via in peripheral driver area.
Compared with prior art, the present invention includes advantages below：
The invention provides a kind of array base palte and preparation method thereof, the present invention is when preparing array base palte, in periphery drive
Antireflection film is formed on amorphous silicon layer in dynamic area, when carrying out crystallization treatment to amorphous silicon layer, energy is in amorphous silicon surfaces
Reflection significantly slackened, in the case where transmitance is constant, amorphous silicon layer absorb energy increase, so as to effectively carry
The crystallization effect of non-multi crystal silicon in high peripheral driver area, obtains the polysilicon layer of larger crystallite dimension.Therefore the present invention is based on
Antireflection film is formed on amorphous silicon layer in the peripheral driver area of polycrystalline SiTFT, is increased in peripheral driver area
Polysilicon layer crystallite dimension, and then improve the drive efficiency of the peripheral drive circuit of polycrystalline SiTFT, improve
The drive efficiency of array base palte.
If the refractive index of antireflection film is the refractive index for being located at the amorphous silicon layer below antireflection film in the present invention
The geometrical mean of the refractive index of gas phase media during with formation antireflection film above antireflection film, then to amorphous
When silicon layer is crystallized, antireflection film is zero to the refraction value of light, and antireflection film can absorb big energy, so that beneficial
In polysilicon crystal, the polysilicon layer of larger crystallite dimension is obtained.
When the present invention carries out crystallization treatment using laser to amorphous silicon layer, if the thickness of antireflection film is the ripple of laser
The a quarter of the ratio of the long refractive index with antireflection film, then absorption of the antireflection film to incident laser is minimum, is made
The consumption of antireflection film material is minimum, and material cost is minimum.
Brief description of the drawings
Fig. 1 is the flow chart of the preparation method of array base palte provided in an embodiment of the present invention；
Fig. 2-Fig. 8 is the structural representation of array base palte preparation process in embodiment illustrated in fig. 1；
Fig. 9 is the light schematic diagram of array base palte provided in an embodiment of the present invention.
Description of reference numerals：
1st, underlay substrate a, pixel region b, peripheral driver area
2nd, cushion 3, amorphous silicon layer 4, antireflection film
41st, in peripheral driver area antireflection film 5, polysilicon layer
51st, in pixel region polysilicon layer, 52, the polysilicon layer in peripheral driver area
511st, the first polysilicon active layer 522, the second polysilicon active layer
6th, the first insulating barrier 7, the second insulating barrier
8th, first grid 9, second grid
10th, source electrode via 11, drain via 12, gas phase media
Embodiment
In order to facilitate the understanding of the purposes, features and advantages of the present invention, it is below in conjunction with the accompanying drawings and specific real
Applying mode, the present invention is further detailed explanation.
In the description of the invention, unless otherwise indicated, " multiple " are meant that two or more；Term " on ",
" under ", "left", "right", " interior ", the orientation of the instruction such as " outer " or position relationship be based on orientation shown in the drawings or position relationship,
The description present invention and simplified description are for only for ease of, rather than indicates or imply that the machine or element of meaning must be with specific
Orientation, with specific azimuth configuration and operation, therefore be not considered as limiting the invention.
In the description of the invention, it is necessary to illustrate, unless otherwise clearly defined and limited, term " installation ", " phase
Even ", " connection " should be interpreted broadly, for example, it may be being fixedly connected or being detachably connected, or be integrally connected；Can
To be mechanical connection or electrical connection；Can be joined directly together, can also be indirectly connected to by intermediary.For this
For the those of ordinary skill in field, the concrete meaning of above-mentioned term in the present invention can be understood with concrete condition.
The embodiment to the present invention is described in further detail with reference to the accompanying drawings and examples.Following examples
For illustrating the present invention, but it is not limited to the scope of the present invention.
It is right when specifically preparing many process thin film transistor (TFT)s in array base palte when preparing array base palte using existing method
The amorphous silicon layer formed on underlay substrate carries out crystallization treatment, obtains the crystalline substance in the pixel region in crystallizing silicon layer, crystallizing silicon layer
Particle size is identical with the crystallite dimension in peripheral driver area, and crystallite dimension is smaller, the peripheral driver of polycrystalline SiTFT
The drive efficiency of circuit is relatively low, and the drive efficiency of array base palte is relatively low.
The crystallite dimension in peripheral driver area in order to increase polycrystalline SiTFT, improves polycrystalline SiTFT
Peripheral drive circuit drive efficiency, improve array base palte drive efficiency, the embodiments of the invention provide a kind of array base
In the preparation method of plate, the array base palte manufactured using this method, the polycrystalline in the peripheral driver area of polycrystalline SiTFT
Silicon layer has larger crystallite dimension.
Fig. 1 is the method flow diagram of the preparation method of array base palte provided in an embodiment of the present invention, the array base shown in Fig. 1
The preparation method of plate includes：
Step 101, amorphous silicon layer is formed on underlay substrate, wherein, the underlay substrate includes pixel region and periphery is driven
Dynamic area.
When preparing array base palte using method provided in an embodiment of the present invention, the polysilicon membrane of array base palte is specifically prepared
During transistor, choose underlay substrate 1, underlay substrate 1 can for glass substrate or other be applicable the substrate of material.Based on array base
The 26S Proteasome Structure and Function of plate, underlay substrate 1 can be divided into pixel region a and peripheral driver area b.Choose after underlay substrate 1, in substrate
Amorphous silicon layer 3 is formed on substrate 1.Based on the region division of underlay substrate 1, the part of amorphous silicon layer 3 is formed in pixel region a,
A part is formed in peripheral driver area b.
In order to improve the driveability of polycrystalline SiTFT, can be formed on underlay substrate 1 amorphous silicon layer 3 it
Before, cushion 2 is first formed on underlay substrate 1, amorphous silicon layer is formed on the buffer layer 2 afterwards.It can be existed by a variety of methods
Amorphous silicon layer 3 is formed on cushion 2, such as deposits to form amorphous silicon layer 3 on the buffer layer 2 using chemical gaseous phase depositing process.On
The structure of underlay substrate 1 and cushion 2 is stated as shown in Fig. 2 the structure of amorphous silicon layer 3 is as shown in Figure 3.
Step 102, on the amorphous silicon layer in the peripheral driver area form antireflection film.
Antireflection film is also known as anti-reflection film, the transmitting for reducing or eliminating the optical surfaces such as lens, calm, level crossing
Light, so as to increase the light transmission capacity of said elements, reduces or eliminates the veiling glare of system.Simplest antireflection film is individual layer
Film, can plate the relatively low film of one layer of refractive index on optical surfaces.
In order to increase the crystallite dimension of polysilicon layer 5 in peripheral driver area b, the embodiment of the present invention is peripheral driver area b's
Antireflection film 4 is formed on amorphous silicon layer 3.Antireflection film 4 can reduce the anti-of the surface of amorphous silicon layer 3 in crystallization
Energy is penetrated, in the case where transmitance is constant, the absorption energy of amorphous silicon layer 3 can be increased, so as to improve the knot of amorphous silicon layer 3
Structure effect, obtains the polysilicon layer 5 of big crystal grain size.
Antireflection film 4 can be formed on the face of underlay substrate 1 in amorphous silicon layer 3 in preparation process, such as accompanying drawing 4
It is shown, the antireflection film 4 in pixel region is removed afterwards, obtains the antireflection film 41 being formed in peripheral driver area, it is such as attached
Shown in Fig. 5.
Step 103, crystallization treatment formation polysilicon layer, polysilicon in the peripheral driver area are carried out to the amorphous silicon layer
The crystallite dimension of layer is more than the crystallite dimension of polysilicon layer in the pixel region.
3 are formed after antireflection film 4 on peripheral driver area b amorphous silicon layer, and crystallization treatment is carried out to amorphous silicon layer 3,
Amorphous silicon layer 3 is transformed into polysilicon layer 5.Because 3 form antireflection film 4, therefore knot on peripheral driver area b amorphous silicon layer
Peripheral driver area b amorphous silicon layer 3 has obtained many of peripheral driver area b after more absorption energy, crystallization treatment during crystalline substance
Crystal silicon layer 5 has larger crystallite dimension.Due to antireflection film 4, therefore crystallization are not formed on pixel region a amorphous silicon layer 3
Pixel region a polysilicon layer 5 has less crystallite dimension after processing.The structure of polysilicon layer 5 as shown in Figure 6, can by Fig. 6
To find out, the crystallite dimension of the polysilicon layer 5 in peripheral driver area b is more than the crystallite dimension of the polysilicon layer 5 in pixel region a.
A variety of methods can be used to carry out crystallization treatment to amorphous silicon layer 3, quasi-molecule laser annealing (ELA) method is such as used
Or solid-phase crystallization (SPC) method carries out crystallization treatment to amorphous silicon layer 3.Amorphous silicon layer 3 is entered using ELA methods or SPC methods
During row crystallization treatment, reflection of the laser energy on the surface of amorphous silicon layer 3 is significantly slackened, in the situation that transmissivity is constant
Under, the laser energy increase that amorphous silicon layer 3 absorbs, so as to improve the crystallization effect of amorphous silicon layer 3, obtains crystal grain chi
Very little larger polysilicon layer 5.
Fig. 9 is the light schematic diagram of array base palte provided in an embodiment of the present invention.Shown in Fig. 9, in the polycrystalline of array base palte
In the crystallization process of amorphous silicon layer 3 of silicon thin film transistor, some light from vacuum or air transmit to antireflection film 4 and thoroughly
Cross antireflection film 4 to transmit to amorphous silicon layer 3, some light is reflected on the surface of antireflection film 4, and some light is worn
Cross antireflection film 4 and reflected on the surface of amorphous silicon layer 3, finally reflexed in vacuum or air.
If from the surface of amorphous silicon layer 3 reflex to the reflection light on the surface of antireflection film 4 with from the surface of antireflection film 4
The phase of the reflected light of reflection differs 180 °, then the interference effect based on light, and reflection light can be mutual to a certain extent
Offset, weaken reflection light.
In normal incidence light beam, from a layer thickness is covered for d1The surface of antireflection film 4 reflection reflected energy
Proportion is that reflectivity R is：
Wherein, the refractive index r of different layers1、r2It can be drawn with reflection angle θ by following formula：
Wherein, n0For air layer or the refractive index of vacuum layer, n1For the refractive index of antireflection film 4, n2For amorphous silicon layer 3
Refractive index；
When the thickness d of antireflection film 41Meet condition：n1d1=(2x+1) λ/4, wherein, n1For the folding of antireflection film 4
Penetrate rate, λ is the wavelength of the laser used in quasi-molecule laser annealing (ELA) or solid-phase crystallization (SPC) method, x=0,1,2,
3 ..., i.e., the reflection light reflected after antireflection film 4 are penetrated by amorphous silicon layer 3 is anti-with the surface of antireflection film 4
When the phase difference for penetrating light is π, a variety of reflection lights can produce interference effect, and reflection light can be supported mutually to a certain extent
Disappear, amorphous silicon layer 3 is minimum to the reflectivity of light.Based on save material, antireflection film 4 it is minimum to the absorption of incident laser with
And the best principle of anti-reflective effect, it is preferable that d1=λ/4n1；
Work as n1d1During=λ/4, reflectivity has the minimum value to be：
From formula (3), as the refractive index n of antireflection film 41It is the amorphous silicon layer 3 for being located at the lower section of antireflection film 4
Refractive index n2The refractive index n of gas phase media when subtracting transmitting film 4 with being formed above antireflection film 40Geometric average
During value, the reflectivity of light is zero, and preferably, antireflection film 4 is the anti-reflection effect of antireflection film 4 to the refraction value of light
Zero.Wherein gas phase media is vacuum or air.
Because the refractive index of amorphous silicon layer 3 is generally 3~4 or so, the refractive index of vacuum or air is 1, therefore antireflective
Film 4 needs to meet desired property with transmitance height and refractive index.Antireflection film 4 can be various material, such as roll over
The bifluoride magnesium that silica that alundum (Al2O3) that the rate of penetrating is 1.8-1.9, refractive index are 1.4-1.5, refractive index are 1.3-1.4
Or the silicon nitride that refractive index is 1.9.The embodiment of the present invention preferably, selects alundum (Al2O3) Al2O3It is used as antireflection film
4 material, Al2O3It is a kind of new III-VI races semiconductor material with wide forbidden band, Al2O3Film is from ultraviolet to mid and far infrared
Transparency is high in spectral region, absorb small, with good physics and chemical property, is widely used as refractive optical material
Material, by controlling quality of forming film, can make Al2O3Film is minimum to the absorptivity of light, the Al of gained2O3Film has high
Transmitance.
Step 104, the removal antireflection film.
After completing to the crystallization treatment of amorphous silicon layer 3, the antireflection film on peripheral driver area b polysilicon layer 5 is removed
4。
Step 105, to the polysilicon layer carry out patterned process, be correspondingly formed the first polycrystalline positioned at the pixel region
Silicon active layer and the second polysilicon active layer positioned at the peripheral driver area.
Remove after the antireflection film 4 on peripheral driver area b polysilicon layer 5, the polycrystalline in patterned process pixel region
Silicon layer 51, obtains the polysilicon layer 52 in the first polysilicon active layer 511, patterned process peripheral driver area, obtains more than second
Crystal silicon active layer 522.The structure of first polysilicon active layer 511 and the second polysilicon active layer 522 is as shown in Figure 7.
Step 106, in first polysilicon active layer and second polysilicon active layer to sequentially form first exhausted
Edge layer, grid, the second insulating barrier, source electrode and drain electrode, obtain the array base palte.
The embodiment of the present invention is after the first polysilicon active layer 511 and the second polysilicon active layer 522 is formed, more than first
The first insulating barrier 6, grid, the second insulating barrier 7, source electrode are sequentially formed in the polysilicon active layer 522 of crystal silicon active layer 511 and second
And drain electrode, polycrystalline SiTFT is obtained, is further prepared using polycrystalline SiTFT provided in an embodiment of the present invention
Array base palte.In addition to polycrystalline silicon thin film transistor structure prepared by the embodiment of the present invention, the other structures of array base palte are existing
Technology, the present invention will not be repeated here.The structure of the polycrystalline SiTFT of array base palte prepared by the embodiment of the present invention is such as
Shown in accompanying drawing 8.
This step sequentially forms the first insulation in first polysilicon active layer and second polysilicon active layer
Layer, grid, the second insulating barrier, source electrode and the process of drain electrode specifically may comprise steps of：
First, the first insulating barrier 6 is formed, the first insulating barrier 6 covers the first polysilicon layer active layer 511 and the second polysilicon
Layer active layer 522, the first insulating barrier 6 is coated on by the first polysilicon layer active layer 511 and the second polysilicon layer active layer 522
It is interior, various ways the first insulating barrier 6 of formation, such as chemical gaseous phase depositing process can be used.
Secondly, patterning forms grid on the first insulating barrier 6, and specifically patterning forms picture on the first insulating barrier 6
The second grid 9 in first grid 8 and peripheral driver area b in plain area a.
It can be formed in practice using techniques such as magnetron sputtering, photoetching, etchings on the first insulating barrier 6 in pixel region a
Second grid 9 in first grid 8 and peripheral driver area b.
Again, the second insulating barrier 7, the second insulating barrier 7 covering first grid 8 and second grid 9 are formed.It can use a variety of
Mode forms the second insulating barrier 7, such as using chemical gaseous phase depositing process in first grid 8, the insulating barrier of second grid 9 and first
Deposition forms the second insulating barrier 7 on 6.
Finally, via is made on the first insulating barrier 6 and the second insulating barrier 7, specifically in pixel region a and peripheral driver area
Source electrode via 10 and drain via 11 are made in b respectively, in source electrode via 10 and drain via 11, is formed in pixel region a
The first source electrode and first drain electrode and the second source electrode in the b of peripheral driver region and second drain electrode.
Via is made on the first insulating barrier 6 and the second insulating barrier 7, via runs through the first insulating barrier 6 and the second insulating barrier
7, the bottom aperture of via is located at the upper surface of the first polysilicon active layer 511 or the upper surface of the second polysilicon active layer 522.
The first source electrode is formed in pixel region a source electrode via 10 afterwards, the is formed in pixel region a drain via 11
One drain electrode, forms the second source electrode, the shape in peripheral driver area b drain via 11 in peripheral driver area in b source electrode via 10
Into the second drain electrode.When making the polycrystalline SiTFT of array base palte, the formation source in source electrode via 10 and drain via 11
Pole and drain electrode are the state of the art, and the present invention will not be repeated here.
The embodiment of the present invention additionally provides a kind of array base palte, is the system of the array base palte provided according to embodiments of the present invention
Made from Preparation Method.The structure of array base palte is as shown in Figure 8.Array base palte includes being formed at is located at pixel on underlay substrate 1
The driving polycrystalline SiTFT in pixel polycrystalline SiTFT and peripherally located driving area b in area a；
It is thin that the crystallite dimension of the first polysilicon active layer 511 in pixel polycrystalline SiTFT is less than driving polysilicon
The crystallite dimension of the second polysilicon active layer 522 in film transistor.
Because the crystallite dimension of the second polysilicon active layer 522 in driving polycrystalline SiTFT is larger, therefore drive
Dynamic polycrystalline SiTFT has larger drive efficiency, and then array base palte has larger drive efficiency.
First be stacked in the pixel region a that pixel polycrystalline SiTFT is additionally may included on underlay substrate 1
Polysilicon active layer 511, the first insulating barrier 6, the insulating barrier 7 of first grid 81 and second in pixel region, and formed in source electrode
Source electrode via 10 and drain electrode in the first drain electrode of the first source electrode and formation in drain via 11 in via 10, pixel region a
The first insulating barrier 6 and the second insulating barrier 7 in the equal insertion pixel region a of via 11.
It is stacked in the peripheral driver area b that driving polycrystalline SiTFT is additionally may included on underlay substrate 1
Second polysilicon active layer 522, the first insulating barrier 6, the insulating barrier 7 of second grid 9 and second in peripheral driver area, and formed
Source electrode mistake in the second drain electrode of the second source electrode and formation in drain via 11 in source electrode via 10, peripheral driver area b
Hole 10 and the first insulating barrier 6 and the second insulating barrier 7 in the equal insertion peripheral driver area b of drain via 11.
The invention provides a kind of array base palte and preparation method thereof, the present invention is when preparing array base palte, in periphery drive
Antireflection film is formed on amorphous silicon layer in dynamic area, when carrying out crystallization treatment to amorphous silicon layer, energy is in amorphous silicon surfaces
Reflection significantly slackened, in the case where transmitance is constant, amorphous silicon layer absorb energy increase, so as to effectively carry
The crystallization effect of non-multi crystal silicon in high peripheral driver area, obtains the polysilicon layer of larger crystallite dimension.Therefore the present invention is based on
Antireflection film is formed on amorphous silicon layer in the peripheral driver area of polycrystalline SiTFT, is increased in peripheral driver area
Polysilicon layer crystallite dimension, and then improve the drive efficiency of the peripheral drive circuit of polycrystalline SiTFT, improve
The drive efficiency of array base palte.
If the refractive index of antireflection film is the refractive index for being located at the amorphous silicon layer below antireflection film in the present invention
The geometrical mean of the refractive index of gas phase media during with formation antireflection film above antireflection film, then to amorphous
When silicon layer is crystallized, antireflection film is zero to the refraction value of light, and antireflection film can absorb big energy, so that beneficial
In polysilicon crystal, the polysilicon layer of larger crystallite dimension is obtained.
When the present invention carries out crystallization treatment using laser to amorphous silicon layer, if the thickness of antireflection film is the ripple of laser
The a quarter of the ratio of the long refractive index with antireflection film, then absorption of the antireflection film to incident laser is minimum, is made
The consumption of antireflection film material is minimum, and material cost is minimum.
Each embodiment in this specification is described by the way of progressive, what each embodiment was stressed be with
Between the difference of other embodiment, each embodiment identical similar part mutually referring to.
Array base palte provided by the present invention and preparation method thereof is described in detail above, tool used herein
Body example is set forth to the principle and embodiment of the present invention, and the explanation of above example is only intended to help and understands this hair
Bright method and its core concept；Simultaneously for those of ordinary skill in the art, according to the thought of the present invention, specific real
Apply and will change in mode and application, in summary, this specification content should not be construed as the limit to the present invention
System.
Claims (10)
1. a kind of preparation method of array base palte, it is characterised in that methods described includes：
Amorphous silicon layer is formed on underlay substrate, wherein, the underlay substrate includes pixel region and peripheral driver area；
Antireflection film is formed on the amorphous silicon layer in the peripheral driver area；
The crystallite dimension of polysilicon layer in crystallization treatment formation polysilicon layer, the peripheral driver area is carried out to the amorphous silicon layer
More than the crystallite dimension of polysilicon layer in the pixel region；
Remove the antireflection film；
Patterned process is carried out to the polysilicon layer, is correspondingly formed positioned at the first polysilicon active layer of the pixel region and position
The second polysilicon active layer in the peripheral driver area；
The first insulating barrier, grid, are sequentially formed in first polysilicon active layer and second polysilicon active layer
Two insulating barriers, source electrode and drain electrode, obtain the array base palte.
2. according to the method described in claim 1, it is characterised in that described that is formed more to amorphous silicon layer progress crystallization treatment
Crystal silicon layer includes：
Crystallization treatment is carried out to the amorphous silicon layer using quasi-molecule laser annealing method or solid-phase crystallization method.
3. method according to claim 2, it is characterised in that the wavelength of the thickness of the antireflection film and the laser
It is directly proportional, is inversely proportional with the refractive index of the antireflection film.
4. method according to claim 2, it is characterised in that the thickness of the antireflection film is the wavelength of the laser
With a quarter of the ratio of the antireflection film refractive index.
5. method according to claim 4, it is characterised in that the refractive index of the antireflection film is to be located at the anti-reflection
Subtract gas when launching film above the antireflection film described in penetrating the refractive index of the amorphous silicon layer below film and being formed
The geometrical mean of the refractive index of phase medium.
6. according to the method described in claim 1, it is characterised in that the material of the antireflection film is one of following：
Alundum (Al2O3), silica, bifluoride magnesium or silicon nitride.
7. according to the method described in claim 1, it is characterised in that described in the first polysilicon layer active layer and described
The first insulating barrier, grid, the second insulating barrier, source electrode and drain electrode are sequentially formed on two polysilicon layer active layers, the array is obtained
Substrate includes：
The first insulating barrier is formed, wherein, first insulating barrier covers the first polysilicon layer active layer and described more than second
Crystal silicon layer active layer；
Patterning forms the first grid being located in the pixel region and driven positioned at the periphery on first insulating barrier
Second grid in dynamic region；
The second insulating barrier is formed, wherein, second insulating barrier covers the first grid and the second grid；
Source electrode via and drain via are made on first insulating barrier and second insulating barrier, in the source electrode via and
In the drain via, formed in the first source electrode in the pixel region and the first drain electrode and the peripheral driver region
Second source electrode and the second drain electrode.
8. array base palte prepared by a kind of preparation method of array base palte according to any one of claim 1~7, its feature
It is, the array base palte includes being formed at the pixel polycrystalline SiTFT being located in pixel region and position on underlay substrate
In the driving polycrystalline SiTFT in peripheral driver area；
The crystallite dimension of the first polysilicon active layer in the pixel polycrystalline SiTFT is less than the driving polysilicon
The crystallite dimension of the second polysilicon active layer in thin film transistor (TFT).
9. array base palte according to claim 8, it is characterised in that the pixel polycrystalline SiTFT is additionally included in
The first polysilicon active layer for being stacked in pixel region on the underlay substrate, the first insulating barrier, first grid and second
Insulating barrier, and the first source electrode formed in source electrode via and the first drain electrode formed in drain via, the pixel region
First insulating barrier described in the interior source electrode via and the equal insertion of the drain via in pixel region and described second exhausted
Edge layer.
10. array base palte according to claim 8, it is characterised in that the driving polycrystalline SiTFT also includes
The second polysilicon active layer for being stacked in peripheral driver area on the underlay substrate, the first insulating barrier, second grid
Drained with the second insulating barrier, and the second source electrode formed in source electrode via with second formed in drain via, it is described
First insulation described in the source electrode via and the equal insertion of the drain via in peripheral driver area in peripheral driver area
Layer and second insulating barrier.
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| CN108663863A (en) * | 2018-06-25 | 2018-10-16 | 深圳市华星光电技术有限公司 | Array substrate |
| CN111081633A (en) * | 2020-01-07 | 2020-04-28 | Tcl华星光电技术有限公司 | Preparation method of array substrate and array substrate |
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| CN1629708A (en) * | 2004-02-26 | 2005-06-22 | 友达光电股份有限公司 | LCD device and method for manufacturing same |
| CN104538310A (en) * | 2015-01-16 | 2015-04-22 | 京东方科技集团股份有限公司 | Preparation method of low-temperature polycrystalline silicon film, TFT, array base plate and display device |
| CN105374882A (en) * | 2015-12-21 | 2016-03-02 | 武汉华星光电技术有限公司 | Low-temperature polycrystalline silicon thin film transistor and preparation method thereof |
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| CN1629708A (en) * | 2004-02-26 | 2005-06-22 | 友达光电股份有限公司 | LCD device and method for manufacturing same |
| CN104538310A (en) * | 2015-01-16 | 2015-04-22 | 京东方科技集团股份有限公司 | Preparation method of low-temperature polycrystalline silicon film, TFT, array base plate and display device |
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