CN107039242A - A kind of nucleocapsid heterojunction structure germanium silicon nanowires and its controllable method for preparing and application - Google Patents
A kind of nucleocapsid heterojunction structure germanium silicon nanowires and its controllable method for preparing and application Download PDFInfo
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- CN107039242A CN107039242A CN201710140216.1A CN201710140216A CN107039242A CN 107039242 A CN107039242 A CN 107039242A CN 201710140216 A CN201710140216 A CN 201710140216A CN 107039242 A CN107039242 A CN 107039242A
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Abstract
The invention discloses a kind of nucleocapsid heterojunction structure germanium silicon nanowires and its controllable method for preparing and application, position and the size of nano wire are defined using high-precision beamwriter lithography and dry etching, it is to avoid the problem of random nucleation in conventional growth method grows；Make the method that silicon nanowires reduces invention introduces high temperature oxygen SiClx, realize the further diminution of germanium silicon nanowires lateral dimension；By adjust germanium/silicon deposition rates than method, can be achieved germanium component arbitrarily adjusted in the range of 0~100%, the sedimentation rate of silicon is faster, and the component of germanium is lower；Conversely, the component of germanium is higher；The controllable method for preparing for the nucleocapsid heterojunction structure germanium silicon nanowires that the present invention is provided has the advantages that controllability is good, processing step is simple, repeatable high, and there is good application prospect in the direction such as nano wire nodeless mesh body tube device, si-based light-emitting device, single-electron device device in the art of semiconductor manufacturing.
Description
Technical field
The present invention relates to semiconductor devices technical field of nano-processing, more particularly to a kind of nucleocapsid heterojunction structure germanium silicon nanometer
Line and its controllable method for preparing and application.
Background technology
Germanium silicon nanowires has the nano-scale structures of two-dimentional quantum confinement, is increasingly becoming integrated opto-electronic in recent years
The study hotspot in field.Germanium silicon nanowires has the light transmitting of unique communication band with optical absorption characteristics, with quantum confinement
Effect, Coulomb blockade effect, good carrier mobility and can be compatible with CMOS technology the advantages of, possess very wide
Application prospect.For example, germanium silicon nanowires can may be used also for making integrated optical source, photo-detector and single-electronic transistor on piece
For making the Primary Component of the following integrated electro subdomains such as no junction nanowire transistor, integrated array sensor.
The preparation of traditional germanium silicon nanowires is prepared by vapour phase epitaxy sedimentation.Under the catalysis of nanogold particle,
It is passed through the proportioning and reaction temperature of silane and germane to realize the growth of nano wire by control.It is characterized in the section of nano wire
Size is determined by the size of gold grain, can realize the coaxial heterogeneous nano thread structure of high-quality germanium silicon multilayer nest.This germanium
Silicon nanowires usually grows vertically upward, and the direction of growth and position are often than more random, therefore the germanium silicon nanometer grown out
Line is difficult compatible with the planar technology of semiconductor micro-nano technology.
In a word, although the comparative maturity that the growth preparation technology of existing germanium silicon nanowires develops, can not be realized
The fully controllable preparation of germanium silicon nanowires, it is impossible to be accurately controlled the key ginseng such as position, size and component of each nano wire
Number, the processing to the semiconductor devices based on germanium silicon nanowires brings very big technology difficulty.
The content of the invention
In view of this, it is an object of the invention to provide a kind of controllable preparation side of nucleocapsid heterojunction structure germanium silicon nanowires
Method, can accurately control the size and location of nano wire, effectively reduce lateral dimension and improve germanium component, controllability is good, technique
Step is simple, and repeatability is high, convenient accurately to prepare the semiconductor devices based on germanium silicon nanowires.
The technical proposal of the invention is realized in this way：On the one hand, the invention provides a kind of nucleocapsid heterojunction structure germanium silicon
The controllable method for preparing of nano wire, it comprises the following steps,
A. silicon substrate is cleaned；
B. one layer of electronic corrosion-resistant is coated in surface of silicon, is exposed by electron beam lithography on electron sensitive resist
Silicon nanowire structure figure needed for light；
C. sample will be obtained in silicon nanowire structure pattern transfer to silicon substrate using dry etching；
D. the electronic corrosion-resistant remained on sample is removed；
E. aoxidize and anneal so that oxygen and pasc reaction formation silica；
F. in removing step e oxidized formation silica, make silicon nanowires center section hanging, cleaning sample；
G. the one layer of germanium-silicon alloy of silicon nanowires outer wrapping obtained in step f, forms germanium silicon nanowires nucleocapsid heterojunction structure；
H. the germanium-silicon alloy deposited on oxygen buried layer is removed, nucleocapsid heterojunction structure germanium silicon nanowires is obtained.
On the basis of above technical scheme, it is preferred that SOI silicon substrates are used in the step a, it includes from top to bottom
Silicon base, oxygen buried layer and top layer silicon three-decker.
On the basis of above technical scheme, it is preferred that electronic corrosion-resistant in the step b using SAL601, HSQ,
PMMA or ZEP520.
On the basis of above technical scheme, it is preferred that the silicon nanowire structure pattern cross section shape in the step b
In the barbell shape that middle thin, two ends are thick.
On the basis of above technical scheme, it is preferred that the dry etching in the step c uses CCl4、BC13、CHF3、
SF6Or C4F8For etching gas, etched using reactive ion etching RIE, inductively coupled plasma ICP etching or electron cyclotron ECR
Method.
On the basis of above technical scheme, it is preferred that the oxidation in the step e uses dry-oxygen oxidation or wet method oxygen
Change, annealing is carried out in nitrogen environment, oxidation and annealing temperature are 700 DEG C -1200 DEG C.
On the basis of above technical scheme, it is preferred that hydrofluoric acid is respectively adopted in the step f and step h and erodes
The germanium-silicon alloy deposited on the silica and oxygen buried layer of oxidized formation.
On the basis of above technical scheme, it is preferred that using molecular beam epitaxial growth method MBE or super in the step e
High vacuum vapor deposition method UHV-CVD wraps up germanium-silicon alloy.
Second aspect, the invention provides a kind of nucleocapsid heterojunction structure germanium silicon nanowires, it uses first aspect present invention
It is prepared by described method.
Second aspect, nucleocapsid heterojunction structure germanium silicon nanowires prepared by the method described in first aspect present invention is in semiconductor
Application in device.
The nucleocapsid heterojunction structure germanium silicon nanowires and its controllable method for preparing of the present invention and application are relative to prior art tool
There is following beneficial effect：
(1) position and the size of nano wire are defined using high-precision beamwriter lithography and dry etching, it is to avoid pass
The problem of random nucleation in system growth method grows；Make the method that silicon nanowires reduces invention introduces high temperature oxygen SiClx, it is real
The further diminution of germanium silicon nanowires lateral dimension is showed；By adjust germanium/silicon deposition rates than method, germanium component can be achieved
Arbitrarily adjusted in the range of 0~100%, the sedimentation rate of silicon is faster, the component of germanium is lower；Conversely, the component of germanium is higher；
(2) as optimization, the silica of surface of silicon nanowires must all be eroded by hydrofluoric acid, can either so ensured
The nucleocapsid heterojunction structure germanium silicon nanowires prepared has very high lattice quality, can guarantee that silicon nanowires surrounding by germanium again
Silicon alloy is wrapped up；
(3) generally speaking, the controllable method for preparing for the nucleocapsid heterojunction structure germanium silicon nanowires that the present invention is provided has controllable
The good, processing step of property is simple, it is repeatable high the advantages of, nano wire nodeless mesh body tube device in the art of semiconductor manufacturing,
There is good application prospect in the directions such as si-based light-emitting device, single-electron device device.
Brief description of the drawings
Fig. 1 is the implementing procedure figure of the nucleocapsid heterojunction structure germanium silicon nanowires controllable method for preparing of the present invention；
Fig. 2-1 is the SOI substrate structural representation of embodiment 1；
Fig. 2-2 is the sample left view structural representation that the step a of embodiment 1 is obtained；
Fig. 2-3 is the sample left view structural representation that the step b of embodiment 1 is obtained；
Fig. 2-4 is the sample left view structural representation that the step c of embodiment 1 is obtained；
Fig. 2-5 is the sample overlooking the structure diagram that the step d of embodiment 1 is obtained；
Fig. 2-6 is the sample positive structure diagram that the step d of embodiment 1 is obtained；
Fig. 2-7 is the sample left view structural representation that the step e of embodiment 1 is obtained；
Fig. 2-8 is the sample positive structure diagram that the step f of embodiment 1 is obtained；
Fig. 2-9 is the sample positive structure diagram that the step g of embodiment 1 is obtained；
Fig. 2-10 is the sample positive structure diagram that the step h of embodiment 1 is obtained.
Embodiment
Below in conjunction with embodiment of the present invention, technical solution of the present invention is clearly and completely described, it is clear that institute
The embodiment of description is only a part of embodiment of the invention, rather than whole embodiments.Based in the present invention
Embodiment, the every other embodiment party that those of ordinary skill in the art are obtained under the premise of creative work is not made
Formula, belongs to the scope of protection of the invention.
Embodiment 1
Various sizes of nucleocapsid heterojunction structure germanium silicon nanowires is prepared on soi substrates.
As shown in Fig. 2-1, the present embodiment selection SOI substrate, from top to bottom successively by silicon base (not knowing in figure),
Oxygen buried layer thick 2000nm and the thick top layer silicon three-decker compositions of 70nm, substrate is cleaned up with RCA techniques.
Step a, as shown in Fig. 2-2, applies the HSQ glue that concentration is 3.6%, coating rotating speed is on soi substrates
4000rpm, and 4min is dried at 150 DEG C using hot plate.
Step b, as Figure 2-3, using e-beam direct-writing exposure, be developed in HSQ formed shape of cross section in centre
Carefully, the silicon nanowire structure figure of the thick barbell shape in two ends.With reference to shown in Fig. 2-5, silicon nanowire structure figure center section
It is respectively 30nm, 40nm, 50nm and 60nm to design width, and the silicon nanowire structure figure of each width has different length
Degree, respectively 0.5 μm, 1 μm, 1.5 μm and 2 μm.The area of the square of silicon nanowire structure figure two end portions is 20*20 μm2。
Electron beam exposure uses the EBPG5000+ electron-beam lithography systems of VISTEC companies, using 100KeV accelerating potentials, 130pa electricity
Beamlet stream, 800 μ C/cm2Exposure dose.Developed at room temperature 180s using ZX238 developer solutions.
Step c, as in Figure 2-4, by the use of HSQ electronic corrosion-resistants figure as mask, using C4F8/SF6Etching gas,
Inductively coupled plasma (ICP) lithographic method etches the top layer silicon of SOI substrate, etching depth 65nm, so that by pattern transfer
Onto SOI top layer silicons.
Step d, removes the electronic corrosion-resistant remained on sample, obtains the sample as shown in Fig. 2-5 and Fig. 2-6.
Step e, sample is placed in 900 DEG C of high temperature process furnances, is passed through oxygen and sample surfaces are aoxidized, then be passed through nitrogen
Gas is annealed to sample surfaces, and oxidization time is 30min, and annealing time is 20min.Then tube furnace is down to room temperature, obtained
To sample as illustrated in figs. 2-7.
Step f, by SOI substrate immersion in a solution of hydrofluoric acid, erodes the silica of surface of silicon nanowires, and silicon is received
Rice noodles center section is hanging, obtains sample as illustrated in figs. 2 through 8.Soak time is unsuitable long, in case silicon nanowires two ends are used for
Oxygen buried layer below the square of support is also all corroded.The silica of surface of silicon nanowires must all be corroded by hydrofluoric acid
Fall, can either so ensure that the nucleocapsid heterojunction structure germanium silicon nanowires prepared has very high lattice quality, can guarantee that again
Silicon nanowires surrounding is wrapped up by germanium-silicon alloy.
Step g, substrate is cleaned up with RCA techniques, then sends into SOI substrate in molecular beam epitaxial growth system,
10nm silicon is first grown at 450 DEG C as cushion, then epitaxial growth Ge0.1Si0.9 SQWs, thickness is 15nm, finally
5nm silicon is covered again, obtains sample as shown in figs. 2-9.Molecular beam epitaxy system is divided using the Eva-32 of Riber companies of France
Beamlet epitaxial system.
Step h, by the SOI substrate grown immersion in a solution of hydrofluoric acid, makes the germanium silicon directly grown on oxygen buried layer
Alloy is stripped, and obtains sample as shown in figs. 2-10.Similarly, soak time is unsuitable long, in order to avoid silicon nanowires two
The oxygen buried layer below the square for support is held also all to be corroded.
By above-mentioned steps, the germanium silicon nanowires of nucleocapsid heterojunction structure just can be prepared.
Embodiment 2
Various sizes of nucleocapsid heterojunction structure germanium silicon nanowires is prepared on soi substrates.
The SOI substrate of the present embodiment selection, from top to bottom successively by silicon base, the oxygen buried layer of 2000nm thickness and 70nm thickness
Top layer silicon three-decker is constituted, and substrate is cleaned up with RCA techniques.
Step a, applies the HSQ glue that concentration is 3.6%, coating rotating speed is 4000rpm, and uses hot plate on soi substrates
4min is dried at 150 DEG C.
Step b, using e-beam direct-writing exposure, is developed in HSQ and forms shape of cross section in the thick thick stick in middle thin, two ends
Bell-shaped silicon nanowire structure figure.The design width of silicon nanowire structure figure center section is respectively 30nm, 40nm, 50nm
And 60nm, the silicon nanowire structure figure of each width has different length, respectively 0.5 μm, 1 μm, 1.5 μm and 2 μm.
The area of the square of silicon nanowire structure figure two end portions is 20*20 μm2.Electron beam exposure is using VISTEC companies
EBPG5000+ electron-beam lithography systems, using 100KeV accelerating potentials, 130pa electronic beam currents, 800 μ C/cm2Exposure dose.Adopt
Developed at room temperature 180s with ZX238 developer solutions.
Step c, by the use of HSQ electronic corrosion-resistants figure as mask, using CCl4Etching gas, electron cyclotron ECR etchings
Method etches the top layer silicon of SOI substrate, etching depth 65nm, so that by pattern transfer to SOI top layer silicons.
Step d, removes the electronic corrosion-resistant remained on sample.
Step e, sample is placed in 700 DEG C of high temperature process furnances, is passed through oxygen and sample surfaces are aoxidized, then be passed through nitrogen
Gas is annealed to sample surfaces, and oxidization time is 30min, and annealing time is 20min.Then tube furnace is down to room temperature.
Step f, by SOI substrate immersion in a solution of hydrofluoric acid, erodes the silica of surface of silicon nanowires, and silicon is received
Rice noodles center section is hanging.
Step g, substrate is cleaned up with RCA techniques, then sends into SOI substrate in molecular beam epitaxial growth system,
10nm silicon is first grown at 450 DEG C as cushion, then epitaxial growth Ge0.1Si0.9 SQWs, thickness is 15nm, finally
5nm silicon is covered again.Molecular beam epitaxy system uses the Eva-32 molecular beam epitaxy systems of Riber companies of France.
Step h, by the SOI substrate grown immersion in a solution of hydrofluoric acid, makes the germanium silicon directly grown on oxygen buried layer
Alloy is stripped.
By above-mentioned steps, the germanium silicon nanowires of nucleocapsid heterojunction structure just can be prepared.
Embodiment 3
Various sizes of nucleocapsid heterojunction structure germanium silicon nanowires is prepared on soi substrates.
The SOI substrate of the present embodiment selection, from top to bottom successively by silicon base, the oxygen buried layer of 2000nm thickness and 70nm thickness
Top layer silicon three-decker is constituted, and substrate is cleaned up with RCA techniques.
Step a, applies the HSQ glue that concentration is 3.6%, coating rotating speed is 4000rpm, and uses hot plate on soi substrates
4min is dried at 150 DEG C.
Step b, using e-beam direct-writing exposure, is developed in HSQ and forms shape of cross section in the thick thick stick in middle thin, two ends
Bell-shaped silicon nanowire structure figure.The design width of silicon nanowire structure figure center section is respectively 30nm, 40nm, 50nm
And 60nm, the silicon nanowire structure figure of each width has different length, respectively 0.5 μm, 1 μm, 1.5 μm and 2 μm.
The area of the square of silicon nanowire structure figure two end portions is 20*20 μm2.Electron beam exposure is using VISTEC companies
EBPG5000+ electron-beam lithography systems, using 100KeV accelerating potentials, 130pa electronic beam currents, 800 μ C/cm2Exposure dose.Adopt
Developed at room temperature 180s with ZX238 developer solutions.
Step c, by the use of HSQ electronic corrosion-resistants figure as mask, using BC13Etching gas, reactive ion etching RIE
Method etches the top layer silicon of SOI substrate, etching depth 65nm, so that by pattern transfer to SOI top layer silicons.
Step d, removes the electronic corrosion-resistant remained on sample.
Step e, sample is placed in 1200 DEG C of high temperature process furnances, is passed through oxygen and sample surfaces are aoxidized, then be passed through
Nitrogen is annealed to sample surfaces, and oxidization time is 30min, and annealing time is 20min.Then tube furnace is down to room temperature.
Step f, by SOI substrate immersion in a solution of hydrofluoric acid, erodes the silica of surface of silicon nanowires, and silicon is received
Rice noodles center section is hanging.
Step g, substrate is cleaned up with RCA techniques, then sends into SOI substrate in molecular beam epitaxial growth system,
10nm silicon is first grown at 450 DEG C as cushion, then epitaxial growth Ge0.1Si0.9 SQWs, thickness is 15nm, finally
5nm silicon is covered again.Molecular beam epitaxy system uses the Eva-32 molecular beam epitaxy systems of Riber companies of France.
Step h, by the SOI substrate grown immersion in a solution of hydrofluoric acid, makes the germanium silicon directly grown on oxygen buried layer
Alloy is stripped.
By above-mentioned steps, the germanium silicon nanowires of nucleocapsid heterojunction structure just can be prepared.
The better embodiment of the present invention is the foregoing is only, is not intended to limit the invention, it is all the present invention's
Within spirit and principle, any modification, equivalent substitution and improvements made etc. should be included in the scope of the protection.
Claims (10)
1. a kind of controllable method for preparing of nucleocapsid heterojunction structure germanium silicon nanowires, it is characterised in that：It comprises the following steps,
A. silicon substrate is cleaned；
B. one layer of electronic corrosion-resistant is coated in surface of silicon, exposes institute on electron sensitive resist by electron beam lithography
The silicon nanowire structure figure needed；
C. sample will be obtained in silicon nanowire structure pattern transfer to silicon substrate using dry etching；
D. the electronic corrosion-resistant remained on sample is removed；
E. aoxidize and anneal so that oxygen and pasc reaction formation silica；
F. in removing step e oxidized formation silica, make silicon nanowires center section hanging, cleaning sample；
G. the one layer of germanium-silicon alloy of silicon nanowires outer wrapping obtained in step f, forms germanium silicon nanowires nucleocapsid heterojunction structure；
H. the germanium-silicon alloy deposited on oxygen buried layer is removed, nucleocapsid heterojunction structure germanium silicon nanowires is obtained.
2. the controllable method for preparing of nucleocapsid heterojunction structure germanium silicon nanowires as claimed in claim 1, it is characterised in that：The step
SOI silicon substrates are used in rapid a, it includes silicon base, oxygen buried layer and top layer silicon three-decker from top to bottom.
3. the controllable method for preparing of nucleocapsid heterojunction structure germanium silicon nanowires as claimed in claim 1, it is characterised in that：The step
Electronic corrosion-resistant in rapid b uses SAL601, HSQ, PMMA or ZEP520.
4. the controllable method for preparing of nucleocapsid heterojunction structure germanium silicon nanowires as claimed in claim 1, it is characterised in that：The step
Silicon nanowire structure pattern cross section shape in rapid b is in the thick barbell shape in middle thin, two ends.
5. the controllable method for preparing of nucleocapsid heterojunction structure germanium silicon nanowires as claimed in claim 1, it is characterised in that：The step
Dry etching in rapid c uses CCl4、BC13、CHF3、SF6Or C4F8For etching gas, using reactive ion etching RIE, inductance
Coupling plasma ICP is etched or electron cyclotron ECR lithographic methods.
6. the controllable method for preparing of nucleocapsid heterojunction structure germanium silicon nanowires as claimed in claim 1, it is characterised in that：The step
Oxidation in rapid e uses dry-oxygen oxidation or wet oxidation, and annealing is carried out in nitrogen environment, and oxidation and annealing temperature be 700 DEG C-
1200℃。
7. the controllable method for preparing of nucleocapsid heterojunction structure germanium silicon nanowires as claimed in claim 1, it is characterised in that：The step
Hydrofluoric acid is respectively adopted in rapid f and step h and erodes the germanium-silicon alloy deposited on the silica and oxygen buried layer of oxidized formation.
8. the controllable method for preparing of nucleocapsid heterojunction structure germanium silicon nanowires as claimed in claim 1, it is characterised in that：The step
Using molecular beam epitaxial growth method MBE or ultrahigh vacuum vapour deposition process UHV-CVD parcel germanium-silicon alloys in rapid e.
9. a kind of nucleocapsid heterojunction structure germanium silicon nanowires, it uses the side as described in claim 1~8 any one claim
It is prepared by method.
10. the nucleocapsid heterojunction structure germanium silicon nanowires prepared such as the method as described in claim 1~8 any one claim
Application in the semiconductor device.
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| CN108394859A (en) * | 2018-02-01 | 2018-08-14 | 南京大学 | A kind of silicon substrate wide spectrum absorbs optical-thermal conversion material and preparation method thereof |
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| US20120302027A1 (en) * | 2011-05-26 | 2012-11-29 | Ru Huang | Method for Fabricating Silicon Nanowire Field Effect Transistor Based on Wet Etching |
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| CN103928297A (en) * | 2013-12-28 | 2014-07-16 | 华中科技大学 | Controllable preparation method of germanium-silicon nano lower-dimension structure and germanium-silicon nano lower-dimension structure |
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| CN103444164A (en) * | 2010-12-21 | 2013-12-11 | 立那工业股份有限公司 | Vertically structured passive pixel arrays and methods for fabricating the same |
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| CN108394859A (en) * | 2018-02-01 | 2018-08-14 | 南京大学 | A kind of silicon substrate wide spectrum absorbs optical-thermal conversion material and preparation method thereof |
| CN108394859B (en) * | 2018-02-01 | 2021-09-10 | 南京大学 | Silicon-based wide-spectrum absorption photothermal conversion material and preparation method thereof |
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