CN107039060A - Follow the trail of circuit and static RAM - Google Patents
Follow the trail of circuit and static RAM Download PDFInfo
- Publication number
- CN107039060A CN107039060A CN201610079638.8A CN201610079638A CN107039060A CN 107039060 A CN107039060 A CN 107039060A CN 201610079638 A CN201610079638 A CN 201610079638A CN 107039060 A CN107039060 A CN 107039060A
- Authority
- CN
- China
- Prior art keywords
- circuit
- nmos pass
- bit cell
- pass transistor
- signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/12—Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Static Random-Access Memory (AREA)
Abstract
One kind follows the trail of circuit, and for static RAM, the static RAM includes：Sense amplifier and at least one static random-access bit cell circuit, the static random-access bit cell circuit leak electricity under word-line signal control；Including：The multiple enable time analog circuits being mutually in parallel, the input of the multiple enable time analog circuit receives the image signal of the word-line signal of the static RAM, the multiple enable time analog circuit is suitable to the electric leakage for simulating the static random-access bit cell circuit, to obtain the time-tracking signal that leaks electricity；Drive circuit, the input of the drive circuit connects the output end of the enable time analog circuit, and according to the enable signal of the electric leakage time-tracking signal generation sense amplifier.The present invention follows the trail of the variation interval that circuit simulates obtained sense amplifier enable time by reducing, and can improve the operating rate of static RAM.
Description
Technical field
The present invention relates to electronic technology field, follow the trail of circuit more particularly, to one kind and static random-access is deposited
Reservoir.
Background technology
With developing rapidly for electronic information technology, people propose higher want to the speed of electronic product
Ask, meanwhile, speed also has become one of most important index in circuit, and this is carried to circuit designer
Higher challenge is gone out, circuit designer needs to optimize the existing functional circuit in part, is allowed to
With faster speed.
Static RAM (Static Random Access Memory, SRAM) is the most frequently used
One of memory, using static storage mode, be used as storage single using static random-access bit cell circuit
Member.The characteristics of SRAM is that read or write speed is fast, and needs less supply voltage, and power consumption is relatively low, and
Memory refresh circuit need not be coordinated, which to improve data after operating efficiency, but power down, to be preserved.SRAM is general
Including：The storage array that is made up of the memory cell, sense amplifier (Sensitive Amplifier,
SA), decoding circuit, control circuit and sequential control circuit etc., wherein, the sense amplifier is suitable to
The data that the storage array is stored are read, and are amplified.Also include following the trail of in SRAM circuit
(Tracking) circuit, is commonly used for the enable signal for producing sense amplifier, generally comprises：During enable
Between analog circuit and drive circuit.Because the tracking circuit is to simulate static random in SRAM storage arrays
The electric leakage of bit cell circuit is accessed, to obtain suitable sense amplifier enable time t, then, to ensure
The stabilization of SRAM operations, it is necessary to ensure the constant interval of the sense amplifier enable time t in the design
(Variation) as far as possible small, this constant interval is smaller, it is possible to caused by the matched design of external circuit
SRAM operating rate is faster.
But, in the SRAM of prior art, follow the trail of the enable time that circuit follows the trail of obtained sense amplifier
Variation interval it is larger, limit SRAM operating rate.
The content of the invention
Present invention solves the technical problem that being the fluctuation zone for reducing the sense amplifier enable time that simulation is obtained
Between, so as to improve SRAM operating rate.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of tracking circuit, for static random
Memory is accessed, the static RAM includes：Sense amplifier and at least one it is static with
Machine accesses bit cell circuit, and the static random-access bit cell circuit leaks electricity under word-line signal control；
Including：
The multiple enable time analog circuits being mutually in parallel, the input of the multiple enable time analog circuit
End receives the image signal of the word-line signal of the static RAM, the multiple enable time
Analog circuit is suitable to the electric leakage for simulating the static random-access bit cell circuit, is chased after with obtaining the electric leakage time
Track signal；
Drive circuit, the input of the drive circuit connects the output end of the enable time analog circuit,
And the enable signal of the sense amplifier is produced according to the electric leakage time-tracking signal.
Alternatively, the enable time analog circuit includes：
Bit cell circuit is followed the trail of, the input of the tracking bit cell circuit connects the enable time simulation
The input of circuit, the tracking bit cell circuit exports the first logical signal；
Load bit cell circuit, the input connection tracking bit location electricity of the load bit cell circuit
The output end on road, the load bit cell circuit is suitable for the tracking bit cell circuit and provided equivalent to institute
The load of static random-access bit cell circuit is stated, the tracking bit cell circuit is in the word-line signal
The image signal control lower driving load bit cell circuit, to simulate the static random-access bit location
The electric leakage of circuit.
Alternatively, the enable time analog circuit also includes：Negative circuit, the negative circuit it is defeated
Enter the end connection output end for following the trail of bit cell circuit, the output end of the negative circuit exports the leakage
Electric time-tracking signal.
Alternatively, the static random-access bit cell circuit has the first latch point and the second latch point,
Including：First nmos pass transistor, the second nmos pass transistor, the first PMOS transistor, second
PMOS transistor, the 3rd nmos pass transistor and the 4th nmos pass transistor；Wherein,
The grid of first nmos pass transistor connects the grid of first PMOS transistor, and even
Connect the drain electrode of second nmos pass transistor and the drain electrode of second PMOS transistor, described
The source ground of one nmos pass transistor, the drain electrode connection described first of first nmos pass transistor
The drain electrode of PMOS transistor, and connect the grid and described second of second nmos pass transistor
The grid of PMOS transistor；
The source ground of second nmos pass transistor；The source electrode connection of first PMOS transistor
Power supply；The source electrode connection power supply of second PMOS transistor；The leakage of first nmos pass transistor
Pole connects first latch point；The drain electrode of second nmos pass transistor connects second latch point；
The drain electrode of 3rd nmos pass transistor connects first latch point；4th nmos pass transistor
Drain electrode connect second latch point.
Alternatively, the tracking bit cell circuit includes at least one described static random-access bit location electricity
Road, wherein, the first latch point connection power supply or ground in the static random-access bit cell circuit；Or
The second latch point connection power supply or ground in person, the static random-access bit cell circuit；
The grid of 3rd nmos pass transistor connects the image signal of the word-line signal, the described 3rd
The drain electrode of nmos pass transistor exports first logical signal；Or, the 4th nmos pass transistor
Grid connect the image signal of the word-line signal, the drain electrode output institute of the 4th nmos pass transistor
State the first logical signal.
Alternatively, the load bit cell circuit includes at least one described static random-access bit location electricity
Road, wherein, the grounded-grid of the 3rd nmos pass transistor, the leakage of the 3rd nmos pass transistor
Pole inputs first logical signal；Or, the grounded-grid of the 4th nmos pass transistor is described
The drain electrode of 4th nmos pass transistor inputs first logical signal.
Alternatively, the negative circuit includes：3rd PMOS transistor and the 5th nmos pass transistor,
Wherein, the source electrode of the 3rd PMOS transistor connects power supply, the grid of the 3rd PMOS transistor
Connect the grid of the 5th nmos pass transistor and connect the input of the negative circuit, the described 3rd
The drain electrode of drain electrode connection the 5th nmos pass transistor of PMOS transistor simultaneously connects the negative circuit
Output end；The source ground of 5th nmos pass transistor.
Alternatively, the drive circuit includes：
Logic circuit, the input of the logic circuit connects the input of the drive circuit, for pair
The electric leakage time-tracking signal carries out logical operation, obtains the second logical signal；
Driving enhancing circuit, the driving force for strengthening second logical signal, the driving enhancing
The output end of circuit exports the enable signal of the sense amplifier.
In order to solve the above technical problems, the embodiment of the present invention also provides a kind of static RAM,
Including above-described tracking circuit.
Compared with prior art, the technical scheme of the embodiment of the present invention has the advantages that：
Tracking circuit provided in an embodiment of the present invention includes：The multiple enable time analog circuits being mutually in parallel,
The input of the multiple enable time analog circuit receives the image signal of SRAM word-line signal, institute
The electric leakage that multiple enable time analog circuits are suitable to simulate the static random-access bit cell circuit is stated, with
Obtain the time-tracking signal that leaks electricity；The tracking circuit also includes：Drive circuit, suitable for according to the leakage
Electric time-tracking signal produces the enable signal of the sense amplifier.It is logical that the embodiment of the present invention follows the trail of circuit
The electric leakage of simulation static random-access bit cell circuit is crossed, the enable signal phase of the sense amplifier can be obtained
Enabled for the delay t of the image signal of the word-line signal, and using the delay t as sense amplifier
Time, still, there is error due to following the trail of the manufacturing process of each device in circuit so that described sensitive to put
The signal that enables of big device has certain do not know relative to the delay t of the image signal of the word-line signal
Property, showing as delay t has constant interval Δ t, in sram, and the enable time of sense amplifier is needed
It is defined by t+ Δs t, constant interval Δ t is smaller, SRAM operating rate is faster.Compared to prior art
Tracking circuit, the embodiment of the present invention employs the multiple enable time analog circuits being mutually in parallel with common
Simulate the electric leakage of static random-access bit cell circuit so that the constant interval Δ t of the delay t is effective
Reduction, so as to improve SRAM speed.
Furthermore, the tracking bit cell circuit in the present embodiment can be included described at least one
Static random-access bit cell circuit, it is described quiet that the load bit cell circuit can also include at least one
State arbitrary access bit cell circuit, makes the present embodiment be more easy to implementation.
Brief description of the drawings
Fig. 1 is a kind of existing schematic block diagram for following the trail of circuit；
Fig. 2 is the schematic block diagram that the embodiment of the present invention follows the trail of circuit；
Fig. 3 is the schematic block diagram of enable time analog circuit of the embodiment of the present invention；
Fig. 4 is the circuit diagram that the embodiment of the present invention follows the trail of bit cell circuit；
Fig. 5 is the circuit diagram that the embodiment of the present invention loads bit cell circuit；
Fig. 6 is the circuit diagram of negative circuit of the embodiment of the present invention；
Fig. 7 is the schematic block diagram of drive circuit of the embodiment of the present invention；
Fig. 8 is the illiteracy of the existing enable signal for following the trail of sense amplifier in circuit with the embodiment of the present invention
Special Caro simulation comparison figure；
Fig. 9 is existing relative with the enable signal for following the trail of sense amplifier in circuit of the embodiment of the present invention
In the delay profiles versus figure of the image signal of word-line signal.
Embodiment
As described in the background section, in the prior art, the tracking breadboardin in SRAM is obtained
The variation interval of the enable time of sense amplifier is larger, limits SRAM operating rate.
Present inventor is analyzed prior art.As shown in figure 1, existing tracking circuit 100
Generally comprise：Enable time analog circuit 10 and drive circuit 20, wherein, the enable time simulation electricity
Road 10 receives the image signal DMWL of the word-line signal of SRAM (not shown)s, suitable for simulation
The electric leakage of the static random-access bit cell circuit, to obtain the time-tracking signal that leaks electricity
Tracking_Signal, the drive circuit 20 is suitable to the electric leakage time-tracking signal
Tracking_Signal carries out logical operation and driving force enhancing, and produces sense amplifier (in figure not
Show) enable signal SAE.The tracking circuit 100 is by simulating static random-access bit location electricity
The electric leakage on road, can obtain mirror images of the enable signal SAE relative to the word-line signal of the sense amplifier
Signal DMWL delay t, delay t has constant interval Δ t, making using t+ Δs t as sense amplifier
The energy time, in the tracking circuit 100 of prior art, the constant interval Δ t depends primarily on described make
Energy time simulation circuit 10 so that the constant interval Δ t is larger, makes SRAM operating rate slower.
For above technical problem, circuit is followed the trail of the embodiments of the invention provide one kind, including：Mutually simultaneously
Multiple enable time analog circuits of connection, the input of the multiple enable time analog circuit receives described
The image signal of the word-line signal of static RAM, the multiple enable time analog circuit is fitted
In the electric leakage for simulating the static random-access bit cell circuit, reducing simulated sense amplifier makes
Can the time standard deviation, that is, the constant interval of the simulated sense amplifier enable time of reduction value,
So as to improve SRAM operating rate.
It is understandable to enable above-mentioned purpose, feature and beneficial effect of the invention to become apparent, with reference to
Accompanying drawing is described in detail to the specific embodiment of the present invention.
Fig. 2 is the schematic block diagram that the embodiment of the present invention follows the trail of circuit.
It is used for as shown in Fig. 2 the embodiment of the present invention follows the trail of circuit 200 in SRAM, the SRAM can
With including：Sense amplifier (not shown) and at least one static random-access bit cell circuit (figure
Not shown in), the static random-access bit cell circuit leaks electricity under word-line signal control；Follow the trail of circuit
200 can include：The multiple enable time analog circuits 10 being mutually in parallel, Fig. 4 is with four enables
Exemplified by the parallel connection of time simulation circuit 10, the input of four enable time analog circuits 10 and output
End is connected, and the input of four enable time analog circuits 10 receives SRAM word-line signal
Image signal DMWL, four enable time analog circuits 10 are suitable to the simulation static random and deposited
The electric leakage of bit cell circuit, to obtain electric leakage time-tracking signal Tracking_Signal.
Following the trail of circuit 200 can also include：Drive circuit 20, the input connection of the drive circuit 20
The output end of the enable time analog circuit 10, and according to the electric leakage time-tracking signal
Tracking_Signal produces the enable signal SAE of the sense amplifier.
Fig. 3 is the schematic block diagram of enable time analog circuit of the embodiment of the present invention；As shown in figure 3,
Enable time analog circuit 10 in the embodiment of the present invention can include：
Bit cell circuit 101 is followed the trail of, when the input for following the trail of bit cell circuit 101 connects the enable
Between analog circuit 10 input, the tracking bit cell circuit 101 exports the first logical signal DBL.
Bit cell circuit 102 is loaded, bit location is followed the trail of in the input connection of the load bit cell circuit 102
The output end of circuit 101, image signal DMWL of the tracking bit cell circuit 101 in word-line signal
The lower driving load bit cell circuit 102 of control, to simulate the electric leakage of static random-access bit cell circuit, i.e.,
It is equal to read operation process of the simulation to static random-access bit cell circuit institute data storage,
In SRAM, when sense amplifier reads the data that static random-access bit cell circuit is stored, in word
Under the driving of line signal, part static random-access bit cell circuit will be as electric leakage load, in this implementation
In example, the load bit cell circuit 102 is suitable for tracking bit cell circuit 101 and provided equivalent to quiet
The load of state arbitrary access bit cell circuit, with reach with existing SRAM to static random-access position
The equivalent process that the data that element circuit is stored are read out, wherein, the tracking bit location electricity
Road 101 is adapted to provide for the leakage path of electric leakage process described above.In fact, the tracking bit location electricity
When the electric leakage of static random-access bit cell circuit is simulated in road 101 with the load bit cell circuit 102,
It is general it cannot be guaranteed that the time complete phase spent with the electric leakage of actual static random-access bit cell circuit
Together, still, in order to ensure SRAM work stability, should ensure that in its acceptable error range
It is advisable.
In embodiments of the present invention, the enable time analog circuit 10 can also include：Negative circuit 103,
The input connection output end for following the trail of bit cell circuit 101 of the negative circuit 103, it is described anti-
The output end output electric leakage time-tracking signal Tracking_Signal of circuitry phase 103.
Fig. 4 is the circuit diagram that the embodiment of the present invention follows the trail of bit cell circuit；As shown in figure 4, specific real
Shi Zhong, the static random-access bit cell circuit can have the first latch point P1 and the second latch point P2,
And it can include：First nmos pass transistor MN1, the second nmos pass transistor MN2, the first PMOS
Transistor MP1, the second PMOS transistor MP2, the 3rd nmos pass transistor MN3 and the 4th
Nmos pass transistor MN4.
Wherein, the grid of the first nmos pass transistor MN1 connects first PMOS transistor
MP1 grid, and connect the drain electrode of the second nmos pass transistor MN2 and the 2nd PMOS
Transistor MP2 drain electrode, the source ground VSS of the first nmos pass transistor MN1, described
One nmos pass transistor MN1 drain electrode connection the first PMOS transistor MP1 drain electrode, and even
Connect the grid of the second nmos pass transistor MN2 and the grid of the second PMOS transistor MP2
Pole, the source ground VSS of the second nmos pass transistor MN2, first PMOS transistor
MP1 source electrode connection power vd D, the second PMOS transistor MP2 source electrode connection power vd D,
The drain electrode of the first nmos pass transistor MN1 connects the first latch point P1, the 2nd NMOS
Transistor MN2 drain electrode connects the second latch point P2, the 3rd nmos pass transistor MN3
Drain electrode connect the first latch point P1, the drain electrode connection of the 4th nmos pass transistor N4 is described
Second latch point P2.
In specific implementation, the bit cell circuit 101 of following the trail of is suitable to believe in the mirror image of the word-line signal
Under number DMWL driving, leakage path is formed together with the load bit cell circuit 102 as load,
In actual circuit design, as long as the tracking bit cell circuit 101 and load bit cell circuit 102
The time that the electric leakage for simulating SRAM static random-access bit cell circuit in practice can be coordinated to be spent,
There can be numerous embodiments, the load provided as load bit cell circuit 102, and chase after
The leak channel quantity that track bit cell circuit 101 is provided, can be in circuit design, depending on actual conditions
Fixed, the present embodiment does not do specifically limited.
And in order that the present embodiment is more easy to implement, the tracking bit cell circuit 101 can include at least one
Individual static random-access bit cell circuit described above.
, can be by the static random-access in the tracking bit cell circuit 101 with continued reference to Fig. 4
The first latch point P1 connection power vd D or ground VSS in bit cell circuit, or, can will be described
The second latch point P2 connection power vd D or ground VSS in static random-access bit cell circuit；Can be with
The grid of the 3rd nmos pass transistor MN3 is made to connect the image signal DMWL of the word-line signal,
The drain electrode of the 3rd nmos pass transistor MN3 exports the first logical signal DBL, or, can
The image signal of the word-line signal is connected with the grid for making the 4th nmos pass transistor MN4
DMWL, the 4th nmos pass transistor MN4 drain electrode export the first logical signal DBL.
Fig. 5 is the circuit diagram that the embodiment of the present invention loads bit cell circuit；As shown in figure 5, for the purposes of
The present embodiment is set to be more easy to implementation, the load bit cell circuit 102 can include at least one described static state
Arbitrary access bit cell circuit.
Wherein it is possible to make the grounded-grid VSS of the 3rd nmos pass transistor MN3, the described 3rd
Nmos pass transistor MN3 drain electrode inputs the first logical signal DBL；Or, it can make described
4th nmos pass transistor MN4 grounded-grid VSS, the 4th nmos pass transistor MN4's
Drain electrode input the first logical signal DBL.
Fig. 6 is the circuit diagram of negative circuit of the embodiment of the present invention；In specific implementation, the negative circuit
103 can use circuit structure well-known to those skilled in the art, i.e., described negative circuit 103 can be wrapped
Include：3rd PMOS transistor MP3 and the 5th nmos pass transistor MN5, wherein, the 3rd PMOS
Transistor MP3 source electrode meets power vd D, the 3rd PMOS transistor MP3 grid connection institute
State the 5th nmos pass transistor MN5 grid and connect the input of the negative circuit 103, it is described
3rd PMOS transistor MP3 drain electrode connection the 5th nmos pass transistor MN5 drain electrode and company
Connect the output end of the negative circuit 103；The source ground VSS of the 5th nmos pass transistor MN5.
Fig. 7 is the schematic block diagram of drive circuit of the embodiment of the present invention；It is described in specific implementation
Drive circuit 20 can include：
Logic circuit 201, the input of the logic circuit 201 connects the input of the drive circuit 20
End, for carrying out logical operation to the electric leakage time-tracking signal Tracking_Signal, obtains second
Logical signal Tracking_Signal_Logic；In specific implementation, the logic circuit 201 can basis
Make sense amplifier enable effective logic requirement to be designed.
Driving enhancing circuit 202, for strengthening the second logical signal Tracking_Signal_Logic's
Driving force, the output end of the driving enhancing circuit 202 exports the enable signal of the sense amplifier
SAE。
Fig. 8 is the illiteracy of the existing enable signal for following the trail of sense amplifier in circuit with the embodiment of the present invention
Special Caro simulation comparison figure, as can be drawn from Figure 8, by existing and embodiment of the present invention tracking
The Multi simulation running for enabling signal SAE of sense amplifier in circuit, it is found that the embodiment of the present invention
The constant interval for following the trail of the enable time for the sense amplifier simulated in circuit is smaller, so as to improve
SRAM operating rate.Furthermore, the present embodiment is electric using the enable time simulation of multi-channel parallel
The electric leakage of SRAM bit cell is simulated on road, system of its general performance closer to enable time analog circuit
Meter performance, rather than single enable time analog circuit it is the same caused due to the error of internal components performance
Deviation it is larger, therefore, it can effectively reduce the constant interval of sense amplifier enable time.Fig. 9 is
The enable signal of sense amplifier is relative to word-line signal in the existing tracking circuit with the embodiment of the present invention
Image signal delay profiles versus figure, as shown in figure 9, the existing and embodiment of the present invention can be drawn
Follow the trail of circuit in sense amplifier enable signal relative to the delay of the image signal of word-line signal mark
Quasi- difference is respectively 2.70 and 1.56, and the sensitive amplification that the tracking circuit of the embodiment of the present invention is simulated can be explained
The constant interval of the enable time of device is smaller.
In order to solve the problems, such as techniques discussed above, the embodiment of the present invention also provides a kind of SRAM, including
Above-described tracking circuit 200.
It should be noted that tracking circuit 200 provided in an embodiment of the present invention should be not limited to certain process node,
It is also not limited to be applied in SRAM, may be equally applicable for the circuit beyond SRAM.
Although present disclosure is as above, the present invention is not limited to this.Any those skilled in the art,
Without departing from the spirit and scope of the present invention, it can make various changes or modifications, therefore the guarantor of the present invention
Shield scope should be defined by claim limited range.
Claims (9)
1. one kind follows the trail of circuit, for static RAM, the static RAM includes：
Sense amplifier and at least one static random-access bit cell circuit, the static random-access bit location
Circuit leaks electricity under word-line signal control；It is characterised in that it includes：
The multiple enable time analog circuits being mutually in parallel, the input of the multiple enable time analog circuit
End receives the image signal of the word-line signal of the static RAM, the multiple enable time
Analog circuit is suitable to the electric leakage for simulating the static random-access bit cell circuit, is chased after with obtaining the electric leakage time
Track signal；
Drive circuit, the input of the drive circuit connects the output end of the enable time analog circuit,
And the enable signal of the sense amplifier is produced according to the electric leakage time-tracking signal.
2. circuit is followed the trail of as claimed in claim 1, it is characterised in that the enable time analog circuit includes：
Bit cell circuit is followed the trail of, the input of the tracking bit cell circuit connects the enable time simulation
The input of circuit, the tracking bit cell circuit exports the first logical signal；
Load bit cell circuit, the input connection tracking bit location electricity of the load bit cell circuit
The output end on road, the load bit cell circuit is suitable for the tracking bit cell circuit and provided equivalent to institute
The load of static random-access bit cell circuit is stated, the tracking bit cell circuit is in the word-line signal
The image signal control lower driving load bit cell circuit, to simulate the static random-access bit location
The electric leakage of circuit.
3. circuit is followed the trail of as claimed in claim 2, it is characterised in that the enable time analog circuit is also wrapped
Include：
Negative circuit, the input connection output end for following the trail of bit cell circuit of the negative circuit,
The output end output electric leakage time-tracking signal of the negative circuit.
4. circuit is followed the trail of as claimed in claim 2, it is characterised in that the static random-access bit location electricity
Road has the first latch point and the second latch point, including：First nmos pass transistor, the 2nd NMOS are brilliant
Body pipe, the first PMOS transistor, the second PMOS transistor, the 3rd nmos pass transistor and the 4th
Nmos pass transistor；Wherein,
The grid of first nmos pass transistor connects the grid of first PMOS transistor, and even
Connect the drain electrode of second nmos pass transistor and the drain electrode of second PMOS transistor, described
The source ground of one nmos pass transistor, the drain electrode connection described first of first nmos pass transistor
The drain electrode of PMOS transistor, and connect the grid and described second of second nmos pass transistor
The grid of PMOS transistor；
The source ground of second nmos pass transistor；
The source electrode connection power supply of first PMOS transistor；
The source electrode connection power supply of second PMOS transistor；
The drain electrode of first nmos pass transistor connects first latch point；
The drain electrode of second nmos pass transistor connects second latch point；
The drain electrode of 3rd nmos pass transistor connects first latch point；
The drain electrode of 4th nmos pass transistor connects second latch point.
5. circuit is followed the trail of as claimed in claim 4, it is characterised in that the tracking bit cell circuit is included extremely
A few static random-access bit cell circuit, wherein,
The first latch point connection power supply or ground in the static random-access bit cell circuit；
Or, the second latch point connection power supply or ground in the static random-access bit cell circuit；
The grid of 3rd nmos pass transistor connects the image signal of the word-line signal, the described 3rd
The drain electrode of nmos pass transistor exports first logical signal；
Or, the grid of the 4th nmos pass transistor connects the image signal of the word-line signal, institute
The drain electrode for stating the 4th nmos pass transistor exports first logical signal.
6. circuit is followed the trail of as claimed in claim 4, it is characterised in that the load bit cell circuit is included extremely
A few static random-access bit cell circuit, wherein,
The grounded-grid of 3rd nmos pass transistor, the drain electrode input of the 3rd nmos pass transistor
First logical signal；
Or, the grounded-grid of the 4th nmos pass transistor, the leakage of the 4th nmos pass transistor
Pole inputs first logical signal.
7. circuit is followed the trail of as claimed in claim 3, it is characterised in that the negative circuit includes：3rd
PMOS transistor and the 5th nmos pass transistor, wherein,
The source electrode of 3rd PMOS transistor connects power supply, and the grid of the 3rd PMOS transistor connects
Connect the grid of the 5th nmos pass transistor and connect the input of the negative circuit, the described 3rd
The drain electrode of drain electrode connection the 5th nmos pass transistor of PMOS transistor simultaneously connects the negative circuit
Output end；
The source ground of 5th nmos pass transistor.
8. circuit is followed the trail of as claimed in claim 1, it is characterised in that the drive circuit includes：
Logic circuit, the input of the logic circuit connects the input of the drive circuit, for pair
The electric leakage time-tracking signal carries out logical operation, obtains the second logical signal；
Driving enhancing circuit, the driving force for strengthening second logical signal, the driving enhancing
The output end of circuit exports the enable signal of the sense amplifier.
9. a kind of static RAM, it is characterised in that including the tracking electricity described in 1 to 8 any one
Road.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610079638.8A CN107039060B (en) | 2016-02-03 | 2016-02-03 | Track circuit and static random access memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610079638.8A CN107039060B (en) | 2016-02-03 | 2016-02-03 | Track circuit and static random access memory |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN107039060A true CN107039060A (en) | 2017-08-11 |
| CN107039060B CN107039060B (en) | 2019-05-28 |
Family
ID=59532566
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201610079638.8A Active CN107039060B (en) | 2016-02-03 | 2016-02-03 | Track circuit and static random access memory |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN107039060B (en) |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100468573C (en) * | 2002-12-17 | 2009-03-11 | 富士通微电子株式会社 | Semiconductor storage apparatus |
| US8467257B1 (en) * | 2011-12-20 | 2013-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit and method for generating a sense amplifier enable signal based on a voltage level of a tracking bitline |
| CN103474093A (en) * | 2012-06-07 | 2013-12-25 | 中芯国际集成电路制造(上海)有限公司 | Tracking path for controlling opening of sense amplifier and static random access memory (SRAM) using tracking path |
| CN103632713A (en) * | 2012-08-29 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | Static random access memory and improving method for storage performance thereof |
-
2016
- 2016-02-03 CN CN201610079638.8A patent/CN107039060B/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100468573C (en) * | 2002-12-17 | 2009-03-11 | 富士通微电子株式会社 | Semiconductor storage apparatus |
| US8467257B1 (en) * | 2011-12-20 | 2013-06-18 | Taiwan Semiconductor Manufacturing Company, Ltd. | Circuit and method for generating a sense amplifier enable signal based on a voltage level of a tracking bitline |
| CN103474093A (en) * | 2012-06-07 | 2013-12-25 | 中芯国际集成电路制造(上海)有限公司 | Tracking path for controlling opening of sense amplifier and static random access memory (SRAM) using tracking path |
| CN103632713A (en) * | 2012-08-29 | 2014-03-12 | 中芯国际集成电路制造(上海)有限公司 | Static random access memory and improving method for storage performance thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN107039060B (en) | 2019-05-28 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| Pal et al. | 9-T SRAM cell for reliable ultralow-power applications and solving multibit soft-error issue | |
| Chun et al. | A 667 MHz logic-compatible embedded DRAM featuring an asymmetric 2T gain cell for high speed on-die caches | |
| Birla et al. | Static noise margin analysis of various SRAM topologies | |
| CN103474093B (en) | Control following the trail of circuit and using the SRAM following the trail of circuit of sense amplifier unlatching | |
| CN103871461B (en) | A kind of be applicable to SRAM write duplicate circuit | |
| Wang et al. | Charge recycling 8T SRAM design for low voltage robust operation | |
| TW201001432A (en) | Methods for providing core supply voltage, and related memory arrays and integrated circuits | |
| TW201721649A (en) | Static random access memory comprising a memory array, a plurality of control circuits, a plurality of pre-charge circuits, a standby start circuit, a plurality of word line voltage level conversion circuits and a plurality of high-voltage level control circuits | |
| Mishra et al. | Analytical modelling and design of 9T SRAM cell with leakage control technique | |
| CN101877243B (en) | Static RAM | |
| Rahman et al. | Design and verification of low power SRAM using 8T SRAM cell approach | |
| CN203799670U (en) | Write copy circuit applicable to static RAM (random access memory) | |
| Huang et al. | Single bit‐line 8T SRAM cell with asynchronous dual word‐line control for bit‐interleaved ultra‐low voltage operation | |
| Prasad et al. | Statistical (MC) and static noise margin analysis of the SRAM cells | |
| Singhal et al. | Comparative study of power reduction techniques for static random access memory | |
| Enachescu et al. | Low-leakage 3D stacked hybrid NEMFET-CMOS dual port memory | |
| CN107039060A (en) | Follow the trail of circuit and static RAM | |
| Moradi et al. | 8T-SRAM cell with Improved Read and Write Margins in 65 nm CMOS Technology | |
| CN104050994A (en) | Asymmetric Sensing Amplifier, Memory Device And Designing Method | |
| Pal et al. | A single ended write double ended read decoupled 8-T SRAM cell with improved read stability and writability | |
| Apollos | Design Principles of SRAM Memory in Nano-CMOS Technologies | |
| CN107818801A (en) | Sensitive amplifier circuit and memory | |
| Mazreah et al. | A novel zero-aware four-transistor SRAM cell for high density and low power cache application | |
| Tomar et al. | Static noise margin analysis during read operation of 7t sram cells in 45nm technology for increase cell stability | |
| Amat et al. | Modem gain-cell memories in advanced technologies |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |