CN107017013A - Memory device writes auxiliary circuit and method - Google Patents
Memory device writes auxiliary circuit and method Download PDFInfo
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- CN107017013A CN107017013A CN201611114381.1A CN201611114381A CN107017013A CN 107017013 A CN107017013 A CN 107017013A CN 201611114381 A CN201611114381 A CN 201611114381A CN 107017013 A CN107017013 A CN 107017013A
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- Prior art keywords
- phase inverter
- operating voltage
- write
- voltage
- memory cell
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1078—Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
- G11C7/1084—Data input buffers, e.g. comprising level conversion circuits, circuits for adapting load
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Abstract
Disclose a kind of including memory cell and the device for writing auxiliary circuit.Memory cell include the first phase inverter and with cross-linked second phase inverter of the first phase inverter.Write auxiliary circuit and be connected to memory cell.During the write operation of memory cell, write auxiliary circuit and be configured the voltage level that the operating voltage for being supplied to the first phase inverter or the second phase inverter is adjusted by bias voltage difference.The present invention also provides a kind of method.
Description
The cross reference of related application
This application claims the excellent of the U.S. Provisional Patent Application of No. 62/271,960 submitted on December 28th, 2015
Rights and interests are selected, the entire disclosure is combined in the text by reference.
Technical field
The present invention relates to semiconductor applications, in particular it relates to which memory device writes auxiliary circuit and method
Background technology
Memory is a kind of significant components in computer, and deposited for different application and developments is many different
Storage structure.For example, storage organization comprising dynamic random access memory (DRAM), static RAM (SRAM), only
Read memory (ROM) and flash memory etc..The conventional structure of sram cell is six transistor (6T) units.Sram cell bag
The phase inverter coupled containing a pair of cross.The numeric bit data that sram cell can be used between storage phase inverter.
The content of the invention
According to an aspect of the present invention there is provided a kind of device, including：Memory cell, including the first phase inverter and with
Cross-linked second phase inverter of one phase inverter；And coupled with memory cell write auxiliary circuit, and in memory cell
During write operation, write auxiliary circuit and be configured at least one operating voltage by the first phase inverter or the second phase inverter is supplied to
Voltage level adjusts bias voltage difference.
According to another aspect of the present invention there is provided a kind of method, including：During the write operation of memory cell, regulation to
The voltage level of a few operating voltage；And during the write operation of memory cell, be memory cell the first phase inverter and
Second phase inverter provides the operating voltage with adjusted voltage level.
According to another aspect of the invention there is provided a kind of device, including：Memory cell, including the first phase inverter and with
Cross-linked second phase inverter of one phase inverter, the first phase inverter includes the first P-type transistor and the first N-type transistor, second
Phase inverter includes the second P-type transistor and the second N-type transistor, and the first operating voltage is provided to the first P-type transistor, the second behaviour
There is provided as voltage to the first N-type transistor, the 3rd operating voltage is provided to the second P-type transistor, and the 4th operating voltage is carried
It is supplied to the second N-type transistor；And coupled to the auxiliary circuit of writing of memory cell, and during the write operation of memory cell,
Auxiliary circuit is write to be configured in the first operating voltage of regulation, the second operating voltage, the 3rd operating voltage and the 4th operating voltage
At least one voltage level.
Brief description of the drawings
When reading in conjunction with the accompanying drawings, the aspect of the present invention can be best understood by according to the following detailed description.Should
This is, it is emphasized that standard practices in industry, all parts are not drawn on scale.In fact, in order to clearly discuss, respectively
The size of individual part can be increasedd or decreased arbitrarily.
Fig. 1 is schematic diagram of the illustration according to the memory device of some embodiments of the present disclosure.
Fig. 2A is signal of the illustration according to the memory cell in Fig. 1 during write operation of some embodiments of the present disclosure
With the schematic diagram of voltage.
Fig. 2 B is illustrate the letter of the memory cell in Fig. 1 during the write operations of some other embodiments of the disclosure
Number and voltage waveform diagram.
Fig. 3 A for illustrate the memory cell in Fig. 1 during the write operations of some embodiments of the present disclosure signal and
The waveform diagram of voltage.
Fig. 3 B for illustrate the memory cell in Fig. 1 during the write operations of some embodiments of the present disclosure signal and
The waveform diagram of voltage.
The flow chart of control methods of the Fig. 4 for illustration in accordance with an embodiment of the present disclosure.
Embodiment
In the following description, detail is presented to provide the detailed understanding of embodiment of the disclosure.But.In this area
Those of ordinary skill will realize that the disclosure can be combined in neither one or multiple above-mentioned details or with miscellaneous part
In the case of put into practice.Do not implement or operation progress specifically displaying or description to knowing, to avoid each embodiment for making the present invention
Aspect it is unclear.
The term used in this specification generally has it in the art and is using the specific of each term
Its ordinary meaning in content.The example used in this specification, includes the example of any term discussed in this article, is only example
Property, and it is in no way intended to limit the present invention or any exemplary term scope and meaning.Similarly, the invention is not restricted to this
Each embodiment provided in specification.
It should be appreciated that, although first, second grade term description each element can be used herein, but these elements should
It should be limited by these terms.These terms are used to distinguish an element and another element.For example, without departing substantially from the present invention's
In the case of spirit and scope, the first element is properly termed as the second element, also, similarly, the second element is properly termed as first
Element.As employed herein, term "and/or" includes any and whole group of one or more relevant objects listed
Close.
As it is used herein, term "comprising", " comprising ", " having ", " containing ", " being related to " etc. are construed as opening
Formula, i.e. expression includes but do not limited.
Throughout the specification, represent special with reference to described by the embodiment with reference to " one embodiment " or " embodiment "
Part, structure, embodiment or feature include at least one embodiment of the present invention in.Therefore, in entire disclosure
The use of phrase " in one embodiment " or " in embodiment " in multiple places is not necessarily to refer to identical reality
Apply example.In addition, in one or more embodiments, special part, structure, embodiment party can be combined in any suitable manner
Formula or feature.
Fig. 1 is schematic diagram of the illustration according to the memory device 100 of some embodiments of the present disclosure.Memory device 100 is included
Memory cell 120 and write auxiliary circuit 140.Write auxiliary circuit 140 and be coupled to memory cell 120, as shown in Figure 1.
In certain embodiments, memory device 100 includes some memory cell 120, and memory cell 120 is set in rows and columns
Put in memory cell array and (be not shown).A memory cell 120 is illustrate only in purpose, Fig. 1 to illustrate.
The varying number of memory cell 120 is all within the desired extent of the disclosure.
In certain embodiments, memory cell 120 includes the first phase inverter 121 and the second phase inverter 122.First phase inverter
121 and the cross-couplings of the second phase inverter 122.In fact, the first phase inverter 121 and the second phase inverter 122 are used as data latches
Operation.In order to illustrate, the input node of the output node of the first phase inverter 121 and the second phase inverter 122 is in the node shown in Fig. 1
Linked together at LQ.The output node of the input node of first phase inverter 121 and the second phase inverter 122 is in the section shown in Fig. 1
Linked together at point LQB.
To carry out operating instruction, the data latches comprising the first phase inverter 121 and the second phase inverter 122 can be in node
Some data are stored at LQ.In order to illustrate, the voltage level on node LQ can be configured to different voltage levels.Node LQ's
Voltage level represents the logical one or logical zero corresponding with storage logical data in the storage unit 120.Node LQB has
There is the logical level opposite with node LQ.For ease of being described below, logical zero indicates low-level, and logical one indicates Gao Shui
It is flat.Indicate for illustration purposes.Various instructions are all within the desired extent of the disclosure.
In certain embodiments, the memory cell 120 shown in Fig. 1 is static RAM (SRAM) unit, is gone out
In the purpose of explanation, it includes six transistors TN1-TN4 and TP1-TP2.Transistor TP1 and TN1 are configured and as first
Phase inverter 121 is operated.Transistor TP2 and TN2 are configured and operated as the second phase inverter 122.In certain embodiments, crystal
Pipe TN1-TN4 is N-type transistor, and transistor TP1-TP2 is P-type transistor.
In certain embodiments, transistor TN3 is configured as the first write transistor, and transistor TN4 is configured as
Second write transistor.In order to illustrate, transistor TN3 and transistor TN4 are controlled by character line signal WL.First phase inverter 121
The input node of output node and the second phase inverter 122, i.e. node LQ, by transistor TN3 coupled to carrying bit line signal BL
Bit line.The output node of the input node of first phase inverter 121 and the second phase inverter 122, i.e. node LQB, passes through transistor
TN4 is coupled to the paratope line for carrying paratope line signal BLB.
In certain embodiments, memory device 100 includes multiple memory cell (not shown), and utilizes bit line signal WL
Select and trigger at least one in memory cell, for example, memory cell 120, it is used for the write/read operation of memory device 100.
When the non-selected memory cell 120 in response to character line signal WL, memory cell 120 is maintained on node LQ and node LQB
Identical voltage level.
In certain embodiments, write auxiliary circuit 140 and auxiliary unit 140a and write auxiliary unit 140b comprising writing.In order to say
It is bright, the transistor TP1 that auxiliary unit 140a is coupled to the first phase inverter 121 is write, and coupled to the crystal of the second phase inverter 122
Pipe TP2.The transistor TN1 that auxiliary unit 140b is coupled to the first phase inverter 121 is write, and coupled to the second phase inverter 122
Transistor TN2.Write auxiliary unit 140a and be configured reception reference voltage VDD, and operating voltage VDD1 is provided for memory cell 120
With operating voltage VDD2.Write auxiliary unit 140b and be configured reception reference voltage VSS, and operation electricity is provided for memory cell 120
Press VSS1 and operating voltage VSS2.In certain embodiments, reference voltage VDD is relatively higher than reference voltage VSS.In some realities
Apply in example, operating voltage VDD1 and VDD2 is relatively higher than operating voltage VSS1 and VSS2.
As illustrated in fig. 1, operating voltage VDD1 is supplied to transistor TP1.Operating voltage VSS1 is supplied to transistor
TN1.Operating voltage VDD2 is supplied to transistor TP2.Operating voltage VSS2 is supplied to transistor TN2.
In certain embodiments, reference voltage VDD be supply voltage, and for example from about 0.5V to about 0.75V model
In enclosing.In certain embodiments, reference voltage VSS is ground voltage.In some other embodiments, reference voltage VSS is through matching somebody with somebody
Put from e.g., from about -0.5V to about -0.75V.
In certain embodiments, operating voltage VDD1 and VDD2 are equal to or are approximately equal to reference voltage VDD.In some implementations
In example, operating voltage VSS1 and VSS2 are equal to or are approximately equal to reference voltage VSS.
During the write operation of memory cell 120, mark is to write auxiliary circuit in Fig. 2A, Fig. 2 B, Fig. 3 A and Fig. 3 B
140 are configured at least one voltage that operating voltage VDD1, VDD2, VSS1 and VSS2 are selectively adjusted by bias voltage difference
Level.The operating voltage of regulation is supplied to the first phase inverter 121 and/or the second writing with ASU auxiliary storage unit 120 of phase inverter 122
Operation.The details of foregoing regulation operation is being discussed on such as Fig. 2A, Fig. 2 B, Fig. 3 A and Fig. 3 B as follows.
Fig. 2A is illustration according to the memory cell 120 in Fig. 1 during write operation WR of some embodiments of the present disclosure
The waveform diagram of signal and voltage.On the embodiment in Fig. 1, for ease of understanding, the element in similar Fig. 2A is designated
Identical Ref. No..To illustrate in fig. 2, write operation WR is performed together with modification operating voltage VSS2, will be with reference to figure
1 discussed below.
As illustrated in Fig. 2A, before time T1, node LQ is set to logical one and node LQB is set to logical zero.
To illustrate in fig. 2, write operation WR starts from time T1.Write operation WR is performed to write logic one data
To node LQB, and logic zero data is written to the node LQ in Fig. 1.
In certain embodiments, during write operation WR, auxiliary unit 140b is write from time T1 by operating voltage in Fig. 1
VSS2 improves bias voltage difference dV1 as shown in Figure 2 A.
During identical write operation WR, operating voltage VSS1 is held equal to or is approximately equal to the reference voltage shown in Fig. 2A
VSS.During identical write operation WR in certain embodiments, operating voltage VDD1 and VDD2 are equal to or are approximately equal to reference to electricity
Press VDD.
To carry out operating instruction, the transistor TN2 being set in the node LQ, Fig. 1 of logical one is responded before time T1 and is beaten
Open.When performing write operation WR in time T1, write auxiliary unit 140b and start to improve operating voltage VSS2.
In time T2, writing auxiliary unit 140b makes operating voltage VSS2 improve bias voltage difference dV1.Therefore, the behaviour of raising
Make voltage VSS2 equal to (VSS+dV1).In response to the operating voltage VSS2 of raising, pass through the transistor TN2 of opening, node LQB
On voltage level also time T2 improve.Compared with not improving the operation of the voltage level on node LQB in advance, node LQB
The voltage level of upper raising causes transistor TP1 quickly to close, and causes transistor TN1 quickly to open.
In time T3, bit line signal BL is through transmitting to logical zero, and paratope line signal BLB is maintained at logical one.
Correspondingly, at time T3, character line signal WL is through transmitting to logical one.In response to character line signal WL, transistor TN3 and
TN4 is opened.Therefore, transistor TN3s of the bit line signal BL of logical zero through opening is provided to node LQ, and logical one
Transistor TN4s of the paratope line signal BLB through opening provide to node LQB.
In response to the bit line signal BL of logical zero, the voltage level on node LQ starts to be discharged to the voltage of logical zero
Level.Start to be charged to logical one in response to the voltage level on paratope line the signal BLB, node LQB of logical one
Voltage level.
As discussed above, the operating voltage VSS2 of raising improves the voltage level on node LQB.Improved on node LQB
Voltage level causes transistor TN1 quickly to open.As transistor TN1 is quickly opened, the voltage level on node LQ
Operating voltage VSS1 is quickly pulled low to, this causes the voltage level on node LQ to be faster discharged to the voltage of logical zero
Level.
Correspondingly, the voltage level of the raising on node LQB causes transistor TP1 quickly to be closed.With transistor
TP1 is quickly closed, and node LQ quickly can disconnect from operating voltage VDD1.
After time T3, logical zero is quickly discharged in response to node LQ voltage level, transistor TP2 is faster
Ground is opened and transistor TN2 is quickly closed.Therefore, compared with not improving the operation of the voltage level on node LQB in advance,
Node LQB voltage level can faster be charged to logical one by operating voltage VDD2.In addition, with the operation of raising
Voltage VSS2, reduces by transistor TP2 and TN2 drain electrode to source leakage.
Fig. 2 B believe for the memory cell 120 in Fig. 1 during the write operation WR according to some other embodiments of the disclosure
Number and voltage waveform diagram.On the embodiment in Fig. 1 and Fig. 2A, for ease of understanding, the element in similar Fig. 2 B is referred to
Identical Ref. No. is determined.To illustrate in fig. 2b, write operation WR is performed together with modification operating voltage VSS1, will be joined
Fig. 1 and Fig. 2 B are examined discussed below.
As shown in Figure 2 B, before time T1, node LQ is pre-set to logical zero and node LQB is set to logic
“1”。
To illustrate in fig. 2b, write operation WR is since time T1.Write operation WR is performed to write logic one data
Enter to node LQ, and the node LQB that logic zero data is write into Fig. 1.
In certain embodiments, during write operation WR, the auxiliary unit 140b that writes in Fig. 1 makes operating voltage from time T1
VSS1 improves bias voltage difference dV1, as shown in Figure 2 B.
During identical write operation WR, operating voltage VSS2 is held equal to or is approximately equal to reference voltage VSS, such as Fig. 2 B institutes
Diagram.During identical write operation WR in certain embodiments, operating voltage VDD1 and VDD2 are equal to or are approximately equal to reference to electricity
Press VDD.
To carry out operating instruction, the transistor before time T1 in response to being set in the node LQB, Fig. 1 of logical one
TN1 is opened.When performing write operation WR in time T1, write auxiliary unit 140b and start to improve operating voltage VSS1.
In time T2, writing auxiliary unit 140b makes operating voltage VSS1 improve bias voltage difference dV1.Therefore, the behaviour of raising
Make voltage VSS1 equal to (VSS+dV1).In response to the operating voltage VSS1 of raising, by the transistor TN1 of opening, on node LQ
Voltage level also at time T2 improve.Compared with not improving the operation of voltage level on node LQ in advance, on node LQ
The voltage level of raising cause transistor TP2 quickly to close, and cause transistor TN2 quickly to open.
In time T3, paratope line signal BLB is through transmitting to logical zero, and bit line signal BL is maintained at logical one.Phase
Ying Di, in time T3, character line signal WL is through transmitting to logical one.In response to character line signal WL, transistor TN3 and TN4 is equal
It is opened.Therefore, transistor TN3s of the bit line signal BL of logical one through opening is provided to node LQ, and logical zero is mutual
Transistor TN4s of the bit line signal BLB through opening is mended to provide to node LQB.
After time T3, in response to the bit line signal BL of logical one, the voltage level on node LQ, which starts to be charged to, patrols
Collect the voltage level of " 1 ".Start to be discharged in response to the voltage level on paratope line the signal BLB, node LQB of logical zero
To the voltage level of logical zero.
As discussed above, the operating voltage VSS1 of raising improves the voltage level on node LQ.The voltage improved on node LQ
Level causes transistor TN2 quickly to be opened.As transistor TN2 is quickly opened, the voltage level energy on node LQB
Enough to be quickly pulled low to operating voltage VSS2, this will cause the voltage level on node LQB to be quickly discharged to logical zero
Voltage level.
Correspondingly, the voltage level improved on node LQ causes transistor TP2 quickly to be closed.With transistor TP2
Quickly closed, node LQB quickly can disconnect from operating voltage VDD2.
After time T3, logical zero is quickly discharged in response to node LQB voltage level, transistor TP1 is by more
Open soon and transistor TN1 is quickly closed.Therefore, with the advance operation phase for improving the voltage level on node LQ
Than node LQ voltage level can quickly be charged to logical one by operating voltage VDD1.In addition, passing through raising
Operating voltage VSS1, reduces by transistor TP1 and TN1 drain electrode to source leakage.
Fig. 2A and Fig. 2 B embodiment, which is illustrated, to be write auxiliary unit 140b and makes operation during the write operation of memory cell 120
Voltage VSS1 or operating voltage VSS2 improve bias voltage difference dV1.
In certain embodiments, bias voltage difference dV1 absolute value is less than transistor TN1-TN4 and TP1-TP2 threshold value
The absolute value of voltage, i.e., | dV1 |<| Vth |, and Vth is one of transistor TN1-TN4 or TP1-TP2 threshold voltage, is so saved
The voltage level of raising on point LQ/LQB will not result in TN1-TN4 and TP1-TP2 is unlocked.In certain embodiments, partially
Put about 10% to about the 30% of the reference voltage VDD that voltage difference dV1 is memory device 100.In certain embodiments, bias voltage
Poor dV1 is 100mV.
Fig. 3 A are the letter of the memory cell 120 during write operation WR in Fig. 1 according to some embodiments of the present disclosure
Number and voltage waveform diagram.On the embodiment in Fig. 1, for ease of understanding, phase is designated in the element in similar Fig. 3 A
Same Ref. No..To illustrate in figure 3 a, write operation WR is performed together with modification operating voltage VDD1, will refer to Fig. 1
It is discussed below with Fig. 3 A.
As shown in Figure 3A, before time T1, node LQ is pre-set to logical one and node LQB is set to logic
“0”。
To illustrate in figure 3 a, write operation WR starts from time T1.Write operation WR is performed to write logic zero data
Enter to node LQ, and the node LQB that logic one data is write into Fig. 1.
In certain embodiments, during write operation WR, the auxiliary unit 140a that writes in Fig. 1 makes operating voltage from time T1
VDD1 reduces bias voltage difference dV2, as shown in Figure 3A.
During identical write operation WR, operating voltage VDD2 is held equal to or is approximately equal to reference voltage VDD, such as Fig. 3 A institutes
Diagram.In certain embodiments, during identical write operation WR, operating voltage VSS1 and VSS2 are equal to or are approximately equal to reference
Voltage VSS.
To carry out operating instruction, response is set to the transistor TP1 in the node LQB, Fig. 1 of logical zero before time T1
It is opened.When performing write operation WR in time T1, write auxiliary unit 140a and start to reduce operating voltage VDD1.
In time T2, writing auxiliary unit 140a makes operating voltage VDD1 reduce bias voltage difference dV2.Therefore, the behaviour of reduction
Make voltage VDD1 equal to (VDD-dV2).In response to the operating voltage VDD1 of reduction, by the transistor TP1 of opening, on node LQ
Voltage level also time T2 reduce.Compared with not reducing the operation of voltage level on node LQ in advance, subtract on node LQ
Small voltage level causes transistor TN2 quickly to be closed, and causes transistor TP2 quickly to be opened.
In time T3, bit line signal BL is through transmitting to logical zero, and paratope line signal BLB is maintained at logical one.
Correspondingly, in time T3, character line signal WL is through transmitting to logical one.In response to character line signal WL, transistor TN3 and TN4
It is opened.Correspondingly, transistor TN3s of the bit line signal BL of logical zero through opening is provided to node LQ, and logical one
Transistor TN4s of the paratope line signal BLB through opening provide to node LQB.
After time T3, in response to the bit line signal BL of logical zero, the voltage level on node LQ, which starts to be discharged to, patrols
Collect the voltage level of " 0 ".Start to be discharged in response to the voltage level on paratope line the signal BLB, node LQB of logical one
To the voltage level of logical one.
As discussed above, the operating voltage VDD1 of reduction reduces the voltage level on node LQ.The voltage reduced on node LQ
Level causes transistor TP2 quickly to be opened.As transistor TP2 is quickly opened, the voltage level energy on node LQB
Enough quickly to be drawn high to operating voltage VDD2, this will cause the voltage level on node LQB quickly to be charged to logical one
Voltage level.
Correspondingly, the voltage level of the reduction on node LQ causes transistor TN2 quickly to be closed.Due to transistor
TN2 is quickly closed, and node LQB quickly can disconnect from operating voltage VSS2.
After time T3, logical one is quickly charged in response to node LQB voltage level, transistor TN1 is by more
Open soon and transistor TP1 is quickly closed.Therefore, with the not advance operation phase for reducing voltage level on node LQ
Than node LQ voltage level can be faster discharged to logical zero by operating voltage VSS1.Further, since the behaviour reduced
Make voltage VDD1, reduce by transistor TP1 and TN1 drain electrode to source leakage.
Fig. 3 B are the signal of the memory cell 120 in Fig. 1 during the write operation WR of some embodiments of the present disclosure
With the waveform diagram of voltage.On the embodiment in Fig. 1 and Fig. 3 A, for ease of understanding, the element in similar Fig. 3 B is designated
Identical Ref. No..To illustrate in figure 3b, write operation WR is performed together with modification operating voltage VDD2, will be referred to
Fig. 1 and Fig. 3 B carry out discussed below.
As illustrated in fig. 3b, before time T1, node LQ is pre-set to logical zero and node LQB is set to logic
“1”。
To illustrate in figure 3b, write operation WR starts from time T1.Write operation WR is performed to write logic one data
To node LQ, and logic zero data is written to the node LQB in Fig. 1.
In certain embodiments, during write operation WR, the auxiliary unit 140a that writes in Fig. 1 makes operating voltage from time T1
VDD2 reduces bias voltage difference dV2, as shown in Figure 3 B.
During identical write operation WR, operating voltage VDD1 is held equal to or is approximately equal to reference voltage VDD, such as Fig. 3 B institutes
Show.In certain embodiments, during identical write operation WR, operating voltage VSS1 and VSS2 are equal to or are approximately equal to reference to electricity
Press VSS.
To carry out operating instruction, response is set to the transistor TP2 quilts in the node LQ, Fig. 1 of logical zero before time T1
Open.When performing write operation WR in time T1, write auxiliary unit 140a and start to reduce operating voltage VDD2.
In time T2, writing auxiliary unit 140a makes operating voltage VDD2 reduce bias voltage difference dV2.Therefore, the behaviour of reduction
Make voltage VDD2 equal to (VDD-dV2).In response to the operating voltage VDD2 of reduction, pass through the transistor TP2 of opening, node LQB
On voltage level also time T2 reduce.Compared with not reducing the operation of the voltage level on node LQB in advance, node LQB
The voltage level of upper reduction causes transistor TN1 quickly to be closed, and causes transistor TP1 quickly to be opened.
In time T3, paratope line signal BLB is through transmitting to logical zero, and bit line signal BL is maintained at logical one.Phase
Ying Di, in time T3, character line signal WL is through transmitting to logical one.In response to character line signal WL, transistor TN3 and TN4 is equal
It is opened.Therefore, transistor TN3s of the bit line signal BL of logical one through opening is provided to node LQ, and logical zero is mutual
Transistor TN4s of the bit line signal BLB through opening is mended to provide to node LQB.
After time T3, in response to the bit line signal BL of logical one, the voltage level on node LQ, which starts to be charged to, patrols
Collect the voltage level of " 1 ".Start to be discharged in response to the voltage level on paratope line the signal BLB, node LQB of logical zero
To the voltage level of logical zero.
As discussed above, the operating voltage VDD2 of reduction reduces the voltage level on node LQB.The electricity reduced on node LQB
Voltage levels cause transistor TP1 quickly to be opened.Because transistor TP1 is quickly opened, the voltage level on node LQ
Can quickly it be drawn high to operating voltage VDD1, this will cause the operating voltage on node LQ quickly to be charged to logic
The voltage level of " 1 ".
Correspondingly, the voltage level reduced on node LQB causes transistor TN1 quickly to be closed.Due to transistor TN1
Quickly closed, node LQ quickly can disconnect from operating voltage VSS1.
After time T3, logical one is quickly charged in response to node LQ voltage level, transistor TN2 is by more
Open soon and transistor TP2 is quickly closed.Therefore, with the advance operation for reducing the voltage level on node LQB
Compare, node LQB voltage level can be quickly discharged to logical zero by operating voltage VSS2.In addition, by reducing
Operating voltage VDD2, by transistor TP2 and TN2 drain electrode to source leakage reduce.
Fig. 3 A and Fig. 3 B embodiment, which are illustrated, to be write auxiliary unit 140a and makes operation during the write operation of memory cell 120
Voltage VDD1 or operating voltage VDD2 reduces bias voltage difference dV2.
In certain embodiments, bias voltage difference dV2 is similar to or equal to bias voltage difference dV1.In certain embodiments,
Bias voltage difference dV2 is higher than (VDD-Vth), and wherein Vth is transistor TN1-TN4 or TP1-TP2 threshold voltage, such node
The voltage level reduced on LQ/LQB will not result in TN1-TN4 and TP1-TP2 is unlocked.In certain embodiments, biased electrical
Pressure difference dV2 is about 10% to about the 30% of the universal reference voltage VDD of memory device 100.In certain embodiments, bias voltage
Poor dV2 is 100mV.
In certain embodiments, using write auxiliary unit 140b improve operating voltage VSS1 or operating voltage VSS2, without
Adjust operating voltage VDD1 and VDD2.In certain embodiments, operating voltage VDD1 or behaviour are reduced using writing auxiliary unit 140a
Make voltage VDD2, without adjusting operating voltage VSS1 and VSS2.
In certain embodiments, for example, writing auxiliary circuit according to the embodiment shown in Fig. 2A, Fig. 2 B, Fig. 3 A and Fig. 3 B
Combination perform write operation.In other words, logic zero data is being written to node LQ and logic one data is written to node LQB
Write operation during, writing auxiliary circuit 140 makes operating voltage VDD1 reduce bias voltage difference dV2, and/or makes operating voltage VSS2
Bias operation voltage difference dV1 is improved, as shown in Fig. 2A and Fig. 3 A.On the other hand, logic one data is being written to node LQ and incited somebody to action
During logic zero data is written to node LQB write operation, writing auxiliary circuit 140 makes operating voltage VDD2 reduce bias voltage difference
DV2, and/or operating voltage VSS1 is improved bias operation voltage difference dV1, as seen in figs. 2 b and 3b.
With reference to Fig. 4, it is the flow chart of the control method 200 according to embodiment of the disclosure.Control method 200 is suitable for
The write operation of memory device of the management for example shown in Fig. 1.
As illustrated in Fig. 1 and Fig. 4, in response to the write operation performed in the memory cell 120 of memory device 100, perform
The operation S202 of control method 200 with determine write operation whether the node LQ of rewriteable memory cell 120, for example from logical one to
Logical zero or from logical zero to logical one.
Control method 200 is further used for adjusting the voltage of at least one operating voltage during the write operation of memory cell
Level.In response to the node LQ for the memory cell 120 for being rewritten to logical zero from logical one, perform operation S204a to adjust behaviour
Make voltage VDD1, as shown in Figure 3A, and/or to adjust operating voltage VSS2, as shown in Figure 2 A.In response to being rewritten from logical zero
To the node LQ of the memory cell 120 of logical one, operation S204b is performed to adjust operating voltage VDD2, as shown in Figure 3 B, and/
Or to adjust operating voltage VSS1, as shown in Figure 2 B.
In certain embodiments, performing operation S204a makes operating voltage VDD1 reduce bias voltage difference dV2, i.e. VDD1=
(VDD-dV2), as shown in Figure 3A.As shown in Fig. 1 and Fig. 3 A, compared with the voltage level for the node LQ that discharged from VDD, due to node
LQ voltage level is dragged down in the time T2 operating voltage VDD1 being reduced, and the voltage level of the reduction on node LQ causes crystal
TN2 is quickly closed and is caused transistor TN2 quickly to be opened.Therefore, with the voltage level phase for the node LQ that discharged from VDD
Than node LQ voltage level will be quickly discharged to logical zero.Because operating voltage VDD1 reduces, as illustrated in Fig. 3 A,
Reduce by transistor TP1 and TN1 drain electrode to source leakage.
In certain embodiments, performing operation S204a makes operating voltage VSS2 reduce bias voltage difference, i.e. VSS2=(VSS
+ dV1), as shown in Figure 2 A.As shown in figure 1 and 2 a, compared with the voltage level from VSS charge nodes LQB, due to node LQB
The operating voltage VSS2 chargings that are enhanced at time T2 of voltage level, the voltage level improved on node LQB causes crystal
TP1 is quickly closed and is caused transistor TN1 quickly to be opened.In addition, the voltage level on node LQ passes through transistor
TN3 is quickly discharged.Therefore, compared with the voltage level from VSS charge nodes LQB, node LQB voltage level will be by more
Charging quickly is to logical one.Because the second operating voltage VSS2 is improved, as illustrated in Fig. 2A, by transistor TP2 and TN2 leakage
Best source leakage reduces.
More than being based on, operation S204a is performed to adjust operating voltage VDD1, as shown in Figure 3A, and/or regulation operating voltage
VSS2, as shown in Figure 2 A.
Operation S206a is performed to provide the operating voltage VDD1 of regulation, as illustrated in Fig. 3 A, and/or is the crystal in Fig. 1
Pipe TP1 or TN2 provide the operating voltage VSS2 of regulation, as shown in Figure 2 A.In certain embodiments, in the section of memory cell 120
During point LQ is rewritten to the write operation WR of logical zero from logical one, as illustrated in Fig. 2A, perform operation S206a to provide regulation
Operating voltage VSS2.In some other embodiments, from logical one logical zero is rewritten in the node LQ of memory cell 120
Write operation WR during, as illustrated in Fig. 3 A, perform operation S206a to provide the operating voltage VDD1 of regulation.
Logical one is rewritten to from logical zero in response to the memory cell 120 in Fig. 1, operation S204b is performed so that operation
Voltage VDD2 reduction bias voltage differences, i.e. VDD2=(VDD-dV2), as illustrated in fig. 3b.As illustrated in Fig. 1 and Fig. 3 B, due to
Voltage level on operating voltage VDD2 reduction, node LQB reduces at time T2.As shown in Figure 3 B, saved with being discharged from VDD
Point LQB voltage level is compared, due to the operating voltage VDD2 electric discharges that node LQB voltage level is reduced at time T2,
The voltage level of reduction on node LQB causes crystal TN1 quickly to be closed and causes transistor TP1 quickly to be opened.
In addition, the voltage level on node LQ is charged faster by transistor TN3.Therefore, node LQ voltage level will be by more
Charging quickly is to logical one.Due to operating voltage VDD2 reduce, as illustrated in fig. 3b, by transistor TP2 and TN2 drain electrode extremely
Source leakage reduces.
In certain embodiments, performing operation S204b makes operating voltage VSS1 reduce bias voltage difference, i.e. VSS1=(VSS
+ dV1), as illustrated in Fig. 2 B.As illustrated in Fig. 1 and Fig. 2 B, due to operating voltage VSS1 reduction, the voltage water on node LQ
Put down and improved at time T2.As shown in Figure 2 B, compared with the voltage level from VSS charge nodes LQ, due to node LQ voltage
The voltage level improved on the operating voltage VSS1 chargings that level is enhanced at time T2, node LQ causes crystal TP2 by more
Close soon and cause transistor TN2 quickly to be opened.In addition, the voltage level on node LQB passes through transistor TN4 by more
Fast electric discharge.Therefore, compared with the voltage level from VSS charge nodes LQ, node LQ voltage level will be charged to faster
Logical one.Because operating voltage VSS1 is improved, as illustrated in Fig. 2 B, by transistor TP1 and TN1 drain electrode to source leakage
Electric current reduces.
More than being based on, operation S204b is performed to adjust operating voltage VDD2, as illustrated in fig. 3b, and/or regulation operation electricity
VSS1 is pressed, as illustrated in Fig. 2 B.
Operation S206b is performed to provide the operating voltage VDD2 of regulation, as illustrated in fig. 3b, and/or is the crystal in Fig. 1
Pipe TP2 or TN1 provide the operating voltage VSS1 of regulation, as illustrated in Fig. 2 B.In certain embodiments, in memory cell 120
During node LQ is rewritten to the write operation WR of logical one from logical zero, as illustrated in Fig. 2 B, performs operation S206ab and tune is provided
The operating voltage VSS1 of section.In some other embodiments, from logical zero logic is rewritten in the node LQ of memory cell 120
During the write operation WR of " 1 ", as illustrated in fig. 3b, perform operation S206a to provide the operating voltage VDD2 of regulation.
In certain embodiments, disclosed device is comprising memory cell and writes auxiliary circuit.It is anti-that memory cell includes first
Phase device and with cross-linked second phase inverter of the first phase inverter.Auxiliary circuit is write to couple with memory cell.In memory cell
Write operation during, write auxiliary circuit be configured by bias voltage difference adjust for the first phase inverter or the second phase inverter to
The voltage level of a few operating voltage.
And disclosed method includes following operation.During the write operation of memory cell, an at least operating voltage is adjusted
Voltage level.During the write operation of memory cell, it should be provided to an at least operating voltage for regulation voltage level
One of first phase inverter and the second phase inverter of memory cell.
Invention additionally discloses a kind of device, it is comprising memory cell and writes auxiliary circuit.Memory cell is anti-phase comprising first
Device and with the second phase inverter.Second phase inverter and the first phase inverter cross-couplings.First phase inverter includes the first P-type transistor
With the first N-type transistor.Second phase inverter includes the second P-type transistor and the second N-type transistor.First operating voltage is used for the
One P-type transistor.Second operating voltage is used for the first N transistors.3rd operating voltage is used for the second P-type transistor.4th behaviour
Making voltage is used for the second N-type transistor.Auxiliary circuit is write to couple with memory cell.During the write operation of memory cell, write auxiliary
Circuit is helped to be configured at least the one of the first operating voltage of regulation, the second operating voltage, the 3rd operating voltage and the 4th operating voltage
Voltage level.
According to an aspect of the present invention there is provided a kind of device, including：Memory cell, including the first phase inverter and with
Cross-linked second phase inverter of one phase inverter；And coupled with memory cell write auxiliary circuit, and in memory cell
During write operation, write auxiliary circuit and be configured at least one operating voltage by the first phase inverter or the second phase inverter is supplied to
Voltage level adjusts bias voltage difference.
According to one embodiment of present invention, the first operating voltage is supplied to the first phase inverter, and the second operating voltage is provided
To the second phase inverter, and during the write operation of memory cell, writing auxiliary circuit and being configured makes the first operating voltage and second
At least one in operating voltage reduces bias voltage difference.
According to one embodiment of present invention, write auxiliary circuit and be configured in and write first data into the defeated of the first phase inverter
Reduce the first operating voltage during the write operation of the input node of egress and the second phase inverter, and write auxiliary circuit and be configured
Reduce the during the output node and the write operation of the input node of the second phase inverter that the second data are write to the first phase inverter
Two operating voltages.
According to one embodiment of present invention, the first operating voltage is supplied to the first phase inverter, and the second operating voltage is provided
To the second phase inverter, and during the write operation of memory cell, write auxiliary circuit and be configured the first operating voltage and second
At least one in operating voltage improves bias voltage difference.
According to one embodiment of present invention, write auxiliary circuit and be configured in and write first data into the defeated of the first phase inverter
The second operating voltage is improved during the write operation of the input node of egress and the second phase inverter, and writes auxiliary circuit and is configured
The is improved during the output node and the write operation of the input node of the second phase inverter that the second data are write to the first phase inverter
One operating voltage.
According to one embodiment of present invention, the first operating voltage signal is supplied to the first phase inverter, the second operating voltage
The second phase inverter is supplied to, and in the input section for writing first data into the output node of the first phase inverter and the second phase inverter
Point write operation during, write auxiliary circuit be configured reduction the first operating voltage signal and improve the second operating voltage signal and
4th operating voltage signal.
According to one embodiment of present invention, the 3rd operating voltage signal is supplied to the first phase inverter, the 4th operating voltage
Signal is supplied to the second phase inverter, and the second data are being write to the defeated of the output node of the first phase inverter and the second phase inverter
During the write operation of ingress, write auxiliary circuit and be configured the 4th operating voltage signal of reduction and improve the 3rd operating voltage letter
Number.
According to one embodiment of present invention, memory cell includes the first write transistor and the second write transistor, and first is anti-
The input node of the output node of phase device and the second phase inverter by the first write transistor be coupled to bit line, the first phase inverter it is defeated
The output node of ingress and the second phase inverter is coupled to paratope line by the second write transistor.
According to one embodiment of present invention, bias voltage difference is about 10% to the 30% of reference voltage.
According to one embodiment of present invention, bias voltage difference is less than the transistor of the first phase inverter or the second phase inverter
Threshold voltage.
According to another aspect of the present invention there is provided a kind of method, including：During the write operation of memory cell, regulation to
The voltage level of a few operating voltage；And during the write operation of memory cell, be memory cell the first phase inverter and
Second phase inverter provides the operating voltage with adjusted voltage level.
According to one embodiment of present invention, the first operating voltage is provided for the first phase inverter, is provided for the second phase inverter
Second operating voltage, and during the write operation of memory cell, the voltage level of regulation operating voltage includes：Make the first operation
A reduction bias voltage difference in voltage or the second operating voltage.
According to one embodiment of present invention, it is anti-phase in the output node and second for writing first data into the first phase inverter
During the write operation of the input node of device, the first operating voltage is set to reduce bias voltage difference, and by the second data write-in the
During the write operation of the input node of the output node of one phase inverter and the second phase inverter, the second operating voltage is set to reduce biased electrical
Pressure difference.
According to one embodiment of present invention, the first operating voltage is provided for the first phase inverter, is provided for the second phase inverter
Second operating voltage, during the write operation of memory cell, the voltage level of regulation operating voltage includes：By the first operating voltage
Or a second raising bias voltage difference in operating voltage.
According to one embodiment of present invention, it is anti-phase in the output node and second for writing first data into the first phase inverter
During the write operation of the input node of device, the second operating voltage is improved into bias voltage difference, and by the second data write-in the
During the write operation of the input node of the output node of one phase inverter and the second phase inverter, the first operating voltage is improved into biased electrical
Pressure difference.
According to one embodiment of present invention, the first operating voltage signal is provided for the first phase inverter, is the second phase inverter
The second operating voltage signal is provided, the voltage level of regulation operating voltage includes：Reduce the first operating voltage；And improve second
Operating voltage.
According to one embodiment of present invention, the 3rd operating voltage signal is provided for the first phase inverter, is the second phase inverter
The 4th operating voltage signal is provided, the voltage level of regulation operating voltage includes：Reduce the 4th operating voltage；And improve the 3rd
Operating voltage.
According to another aspect of the invention there is provided a kind of device, including：Memory cell, including the first phase inverter and with
Cross-linked second phase inverter of one phase inverter, the first phase inverter includes the first P-type transistor and the first N-type transistor, second
Phase inverter includes the second P-type transistor and the second N-type transistor, and the first operating voltage is provided to the first P-type transistor, the second behaviour
There is provided as voltage to the first N-type transistor, the 3rd operating voltage is provided to the second P-type transistor, and the 4th operating voltage is carried
It is supplied to the second N-type transistor；And coupled to the auxiliary circuit of writing of memory cell, and during the write operation of memory cell,
Auxiliary circuit is write to be configured in the first operating voltage of regulation, the second operating voltage, the 3rd operating voltage and the 4th operating voltage
At least one voltage level.
According to one embodiment of present invention, write auxiliary circuit and be configured in and write first data into the defeated of the first phase inverter
During the write operation of the input node of egress and the second phase inverter, reduce the first operating voltage, and write auxiliary circuit through matching somebody with somebody
Put during the output node and the write operation of the input node of the second phase inverter that the second data are write to the first phase inverter, reduce
3rd operating voltage.
According to one embodiment of present invention, write auxiliary circuit and be configured in and write first data into the defeated of the first phase inverter
During the write operation of the input node of egress and the second phase inverter, the 4th operating voltage is improved, and write auxiliary circuit through matching somebody with somebody
Put during the output node and the write operation of the input node of the second phase inverter that the second data are write to the first phase inverter, improve
Second operating voltage.
The above outlines the feature of several embodiments, so that those of ordinary skill in the art can be best understood from
The each side of the disclosure.It will be recognized by one of ordinary skill in the art that it can be easily by based on the disclosure, for designing
Or other techniques or structure are changed, so as to reach the identical purpose introduced with embodiment hereof and/or realize identical advantage.
Those of ordinary skill in the art will also be appreciated that this equivalent structure without departing from spirit and scope of the present disclosure, and it can
To carry out various changes, replacement and change without departing from spirit and scope of the present disclosure.
Claims (10)
1. a kind of device, including：
Memory cell, including the first phase inverter and with cross-linked second phase inverter of first phase inverter；And
What is coupled with the memory cell writes auxiliary circuit, and during the write operation of the memory cell, it is described to write auxiliary
Circuit is configured the voltage level of at least one operating voltage by first phase inverter or second phase inverter is supplied to
Adjust bias voltage difference.
2. device according to claim 1, wherein, the first operating voltage is supplied to first phase inverter, the second operation
Voltage is supplied to second phase inverter, and during the write operation of the memory cell, it is described to write auxiliary circuit warp
Configuration makes at least one described bias voltage difference of reduction in first operating voltage and second operating voltage.
3. device according to claim 2, wherein, it is described write auxiliary circuit and be configured in write first data into described
Reduce first operation during the write operation of the input node of the output node of one phase inverter and second phase inverter
Voltage, and the auxiliary circuit of writing is configured in the output node and the institute that the second data are write to first phase inverter
Reduce second operating voltage during the write operation for the input node for stating the second phase inverter.
4. device according to claim 1, wherein, the first operating voltage is supplied to first phase inverter, the second operation
Voltage is supplied to second phase inverter, and during the write operation of the memory cell, it is described to write auxiliary circuit warp
Configure and at least one in first operating voltage and second operating voltage is improved into the bias voltage difference.
5. device according to claim 4, wherein, it is described write auxiliary circuit and be configured in write first data into described
Second operation is improved during the write operation of the input node of the output node of one phase inverter and second phase inverter
Voltage, and the auxiliary circuit of writing is configured in the output node and the institute that the second data are write to first phase inverter
First operating voltage is improved during the write operation for the input node for stating the second phase inverter.
6. device according to claim 1, wherein, the first operating voltage signal is supplied to first phase inverter, second
Operating voltage is supplied to second phase inverter, and is writing first data into the output node of first phase inverter and institute
During the write operation for the input node for stating the second phase inverter, the auxiliary circuit of writing is configured reduction the first operation electricity
Press signal and improve the second operating voltage signal and the 4th operating voltage signal.
7. device according to claim 1, wherein, the 3rd operating voltage signal is supplied to first phase inverter, the 4th
Operating voltage signal is supplied to second phase inverter, and in the output node that the second data are write to first phase inverter
During the write operation of the input node of second phase inverter, the auxiliary circuit of writing is configured reduction the 4th behaviour
Make voltage signal and improve the 3rd operating voltage signal.
8. device according to claim 1, wherein, the memory cell writes crystal including the first write transistor and second
The input node of pipe, the output node of first phase inverter and second phase inverter is coupled by first write transistor
To bit line, the output node of the input node of first phase inverter and second phase inverter passes through second write transistor
Coupled to paratope line.
9. a kind of method, including：
During the write operation of memory cell, the voltage level of at least one operating voltage is adjusted；And
During the write operation of the memory cell, provided for the first phase inverter and the second phase inverter of the memory cell
The operating voltage with the adjusted voltage level.
10. a kind of device, including：
Memory cell, including the first phase inverter and with cross-linked second phase inverter of first phase inverter, described first is anti-
Phase device includes the first P-type transistor and the first N-type transistor, and second phase inverter includes the second P-type transistor and the second N-type
Transistor, the first operating voltage is provided to first P-type transistor, and the second operating voltage is provided to the first N-type crystal
Pipe, the 3rd operating voltage is provided to second P-type transistor, and the 4th operating voltage is provided to the second N-type crystal
Pipe；And
It is described to write auxiliary coupled to the auxiliary circuit of writing of the memory cell, and during the write operation of the memory cell
Circuit is configured regulation first operating voltage, second operating voltage, the 3rd operating voltage and the 4th behaviour
Make at least one voltage level in voltage.
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| CN202211241894.4A CN115482846A (en) | 2015-12-28 | 2016-12-07 | Write assist circuit and method for memory device |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US201562271960P | 2015-12-28 | 2015-12-28 | |
| US62/271,960 | 2015-12-28 | ||
| US15/202,387 | 2016-07-05 | ||
| US15/202,387 US10269418B2 (en) | 2015-12-28 | 2016-07-05 | Write assist circuit of memory device |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI625724B (en) | 2018-06-01 |
| US20170186482A1 (en) | 2017-06-29 |
| US10964381B2 (en) | 2021-03-30 |
| CN115482846A (en) | 2022-12-16 |
| US20200111527A1 (en) | 2020-04-09 |
| US20200372953A1 (en) | 2020-11-26 |
| US10770136B2 (en) | 2020-09-08 |
| US10102901B2 (en) | 2018-10-16 |
| US10269418B2 (en) | 2019-04-23 |
| US20190252018A1 (en) | 2019-08-15 |
| US10510404B2 (en) | 2019-12-17 |
| TW201735033A (en) | 2017-10-01 |
| US20180061488A1 (en) | 2018-03-01 |
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Application publication date: 20170804 |