CN106328191B - Negative voltage bit line writes auxiliary SRAM circuit and method - Google Patents
Negative voltage bit line writes auxiliary SRAM circuit and method Download PDFInfo
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- CN106328191B CN106328191B CN201510374001.7A CN201510374001A CN106328191B CN 106328191 B CN106328191 B CN 106328191B CN 201510374001 A CN201510374001 A CN 201510374001A CN 106328191 B CN106328191 B CN 106328191B
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Abstract
The present invention relates to electronic technology fields, and in particular to a kind of Static RAM.Negative voltage bit line writes auxiliary SRAM circuit, including, N number of SRAM memory cell, each SRAM memory cell connects one first bit line and one second bit line；The first transistor, the first bit line of on or off and ground voltage under the action of the first write enable signal；Second transistor, the second bit line of on or off and ground voltage under the action of the second write enable signal；Comparing unit, compares the voltage difference of the first bit line and the second bit line under the action of enable signal, and exports the first signal and the second signal；One first coupled capacitor is connected between first signal and the first bit line, one second coupled capacitor is connected between second signal and the second bit line, the first signal couples generation negative voltage on the first bit line or second signal couples on the second bit line and generates negative voltage.The present invention is not necessarily to be the individually designed control circuit of bit line negative electricity volt circuit, and circuit is simple and saves circuit area.
Description
Technical field
The present invention relates to electronic technology fields, and in particular to a kind of Static RAM.
Background technique
Fig. 1 show the most common SRAM memory cell being made of six transistors of Static RAM, works as node
N1 voltage is high and node N0 voltage when being low, and the value stored in the storage unit is known as logic 1, otherwise is logical zero.Work as needs
When rewriting the data stored in SRAM memory cell, such as the value 1 of storage being rewritten as 0, corresponding operation step are as follows: first will
Wordline WL (Word Line) is charged as high voltage (generally equivalent to supply voltage VDD), by bit line BL (Bit Line) voltage by electricity
Voltage VDD drop-down in source is ground voltage VSS, and the voltage of the anti-BLB of bit line is maintained supply voltage VDD；Due to SRAM memory cell
The driving capability of middle PMOS transistor ML1 is weaker than the driving capability of NMOS transistor MPG1, and node N1 can be pulled down to by bit line BL
One lower voltage, node N1 voltage will drive the rising of node N0 voltage after reducing, and the rising meeting of node N0 voltage
Further promote the decline of node N1 voltage；Such a positive feedback process can always pull down node N1 voltage for ground voltage
VSS, node N0 voltage pull-up are supply voltage VDD；Just realize in this way the logic state that is stored in SRAM memory cell from 1 to
0 transformation, the waveform diagram of above-mentioned write operation is as shown in Fig. 2, realize the normal reversion of node N1 voltage Yu node N0 voltage.
However as the continuous diminution of integrated circuit technology size, after especially process develops to 16nm, processing procedure
The reduction of deviation further increased with supply voltage is so as to carry out write operation, i.e., static random access memory cell is increasingly difficult to
The data of sram memory storage are difficult to be modified.One kind that write operation has difficulties, which takes the form of, to be takeed a long time completion and writes
Enter operation, another form of expression is then even more serious, i.e., can not rewrite the data in storage unit completely.As shown in figure 3, to write
The waveform diagram of operation failure, SRAM memory cell interior joint N1 and node N0 remain unfulfilled reversion after wordline becomes low from height,
The value of SRAM memory cell reverts to original state again under the action of self feed back later.
In order to solve the problems, such as it is above-mentioned write difficulty, bit line negative voltage technology is invented and is applied in the design of SRAM,
However, existing bit line negative voltage technology there are control circuits complicated, circuit the defects of occupied area is larger in the chips, it cannot
It satisfies the use demand.
Summary of the invention
The object of the present invention is to provide a kind of negative voltage bit lines to write auxiliary SRAM circuit and method, overcomes the prior art
Bit line negative voltage technical controlling circuit is complicated, the circuit biggish defect of occupied area in the chips.
Technical problem solved by the invention can be realized using following technical scheme:
Negative voltage bit line writes auxiliary SRAM circuit, wherein including,
N number of SRAM memory cell, each SRAM memory cell connect one first bit line and one second bit line；
One the first transistor, under the action of the first write enable signal of Yu Yi the first bit line described on or off with
Ground voltage；
One second transistor, under the action of the second write enable signal of Yu Yi the second bit line described on or off with
The ground voltage；
One comparing unit, the voltage of first bit line and second bit line under the action of an enable signal
Difference, and export the first signal and the second signal；
One first coupled capacitor, the second signal and described the are connected between first signal and first bit line
One second coupled capacitor is connected between two bit lines, first signal couples on first bit line under imposing a condition in first
It generates to couple on second bit line under a negative voltage or the second signal impose a condition in second and generates a negative voltage.
Negative voltage bit line of the invention writes auxiliary SRAM circuit, and it is corresponding that N number of SRAM memory cell is separately connected one
Wordline, wherein carrying out write operation to the corresponding SRAM memory cell when wordline is selected.
Negative voltage bit line of the invention writes auxiliary SRAM circuit, and the voltage of first bit line is higher than second bit line
When voltage, the first signal output HIGH voltage, the second signal exports low-voltage；The voltage of second bit line is higher than institute
When stating the voltage of the first bit line, first signal exports low-voltage, the second signal output HIGH voltage.
Negative voltage bit line of the invention writes auxiliary SRAM circuit, and the comparing unit uses sense amplifier, described sensitive
Amplifier has first input end and the second input terminal and the first output end and a second output terminal, the first input end with it is described
The connection of first bit line, second input terminal are connect with second bit line, and first output end is for exporting described first
Signal, the second output terminal is for exporting the second signal.
Negative voltage bit line of the invention writes auxiliary SRAM circuit, and each SRAM memory cell includes,
One first switch device controllably connects first bit line to a first segment under a corresponding wordline effect
Point；
One second switch device controllably connects second bit line to one second section under the action of Yu Suoshu wordline
Point；
One basic unit of storage, when Yu Suoshu first node is high voltage and the second node is low-voltage, storage
Data are 1；Or when the first node is low-voltage and the second node is high voltage, the data of storage are 0.
Negative voltage bit line of the invention writes auxiliary SRAM circuit, and the basic unit of storage includes,
First PMOS tube, selectively turn-on power voltage and the first segment under the voltage effect of a second node
Point；
The supply voltage and described the is selectively connected under the voltage effect of Yu Suoshu first node in second PMOS tube
Two nodes；
The first node and ground electricity is selectively connected under the voltage effect of Yu Suoshu second node in first NMOS tube
Pressure；
The second node and the ground electricity is selectively connected in second NMOS tube under the effect of Yu Suoshu first node voltage
Pressure.
Negative voltage bit line of the invention writes auxiliary SRAM circuit, and first bit line is along N number of SRAM memory cell
Orientation is arranged and is located at same one side of the SRAM memory cell；Second bit line is along N number of SRAM memory cell
Orientation on opposite with first bit line another side setting.
The present invention also provides a kind of method that negative voltage bit line writes auxiliary, applied in above-mentioned SRAM circuit, including write
The step of entering data 0:
Step 11, first bit line is pulled down to ground voltage；
Step 12, the voltage difference of first bit line and second bit line and the first signal of output and the second letter
Number；
Step 13, the connection of first bit line and the ground voltage is disconnected, first signal passes through first coupling
Conjunction capacitor couples on first bit line obtains a negative voltage；
Step 14, the wordline of a SRAM memory cell is selected, and first bit line is connected to the first node, described
First node is low-voltage and the second node is pulled to high voltage.
The method that negative voltage bit line of the invention writes auxiliary includes the steps that data 1 are written:
Step 21, second bit line is pulled down to ground voltage；
Step 22, the voltage difference of first bit line and second bit line and the first signal of output and the second letter
Number；
Step 23, the connection of second bit line and the ground voltage is disconnected, the second signal passes through second coupling
Conjunction capacitor couples on second bit line obtains a negative voltage；
Step 24, the wordline of a SRAM memory cell is selected, and second bit line is connected to the second node, described
Second node is low-voltage and the first node is pulled to high voltage.
The method that negative voltage bit line of the invention writes auxiliary, the voltage of the first bit line described in step 2 are higher than described second
When the voltage of bit line, the first signal output HIGH voltage, the second signal exports low-voltage；The voltage of second bit line
Higher than first bit line voltage when, first signal exports low-voltage, the second signal output HIGH voltage.
The utility model has the advantages that due to using the technology described above, the present invention is not necessarily to be the individually designed control of bit line negative electricity volt circuit
Circuit, circuit is simple and saves circuit area.
Detailed description of the invention
Fig. 1 is SRAM memory cell circuit diagram conventional in the prior art；
Fig. 2 is the waveform diagram of the normal write operation of the prior art；
Fig. 3 is the waveform diagram for writing difficulty of the prior art；
Fig. 4 is a kind of improved SRAM circuit structure chart.
Fig. 5 is the waveform diagram of the write operation of Fig. 4；
Fig. 6 is SRAM circuit structure chart of the invention；
Fig. 7 is the waveform diagram of write operation of the invention；
Fig. 8 is the flow chart for writing data 0 of the invention；
Fig. 9 is the flow chart for writing data 1 of the invention.
Specific embodiment
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, instead of all the embodiments.It is based on
Embodiment in the present invention, those of ordinary skill in the art without creative labor it is obtained it is all its
His embodiment, shall fall within the protection scope of the present invention.
It should be noted that in the absence of conflict, the feature in embodiment and embodiment in the present invention can phase
Mutually combination.
The present invention will be further explained below with reference to the attached drawings and specific examples, but not as the limitation of the invention.
In Fig. 1 influence SRAM memory cell write operation key factor first is that the driving of PMOS transistor ML1 (or ML0)
The driving capability ratio of ability and NMOS transistor MPG1 (or MPG0), the smaller then write capability of ratio is stronger, partly leads advanced
In system journey, due to the reduction of transistor size, process deviation is increased accordingly, and the SRAM actually manufactured is difficult to protect always
Demonstrate,prove the above-mentioned driving capability ratio requirement of satisfaction to write operation as design expectation in all storage units.Bit line negative voltage
(Negative Bit Line, NBL) can solve the above problem, and its implementation is: in write operation, the voltage of bit line BL is not
It pulled down to ground voltage VSS again, but voltage more lower than ground voltage VSS, the voltage value of general ground voltage VSS is 0, then one
Voltage more lower than VSS is a negative voltage.The voltage of bit line BL is negative value, the MOS transistor MPG1 when wordline WL is opened
The driving capability of (or MPG0) will be greater than the case where BL voltage is 0, be easier to realize in this way to SRAM memory cell write operation.
As shown in figure 4, the SRAM storage array circuit structure being made of 1 column SRAM memory cell of n row, only indicated in figure
Storage unit CELL [0] and storage unit CELL [n-1], remaining is indicated with ellipsis.Bit line BL passes through drop-down MOS transistor
MN0 is connect with ground voltage VSS, and the anti-BLB of bit line is connect by pulling down MOS transistor MN1 with ground voltage VSS, while in order to avoid
A possibility that writing unsuccessfully, capacitor C0 is connected on bit line BL, is connected on the other end connection signal NBST0 of capacitor C0, the anti-BLB of bit line
Meet capacitor C1, the other end connection signal NBST1 of capacitor C1.
The specific work process of foregoing circuit are as follows: when needing to write 0, signal WT0 first is got higher, and pulls down MOS transistor MN0
Open, signal NBST0 maintains high potential in the process that bit line BL is pulled down, when bit line BL pulled down to ground voltage (VSS,
It is believed that voltage value be 0) after, signal WT0 by height be lower will drop-down MOS transistor MN0 close, later signal NBST0 by height become
Low, due to capacitance coupling effect, the voltage of bit line BL is coupled on a voltage more lower than 0 voltage, is thereby realized
Bit line BL voltage is by 0 to negative voltage transformation, if certain wordline WL is opened at this time, data 0 are easily written into corresponding SRAM
In storage unit.Conversely, signal WT1 first is got higher when needing to write 1, drop-down MOS transistor MN1 is opened, the anti-BLB quilt of bit line
Signal NBST1 maintains high potential in the process of drop-down, when the anti-BLB of bit line pulls down to ground voltage (VSS, it is believed that electricity by MN1
Pressure value be 0) after, signal WT1 can be lower by height will drop-down MOS transistor MN1 close, signal NBST1 is lower by height later, due to
Capacitance coupling effect, the voltage of the anti-BLB of bit line are coupled on a voltage more lower than 0 voltage, thereby realize BLB electricity
It presses by 0 to negative voltage transformation, so that data 1 are easier to be written into SRAM memory cell.Fig. 5 is the signal of above-mentioned write operation
Waveform diagram, foregoing circuit have the drawback that: control circuit is complicated, needs the control electricity of individually designed signal NBST0/NBST1
Road with guarantee the rising of signal NBST0/NBST1 after the decline of signal WT0/WT1, and need extra logic circuitry according to
Storage unit write-in 0 or write-in 1 go judgement to need to pull down NBST0 or pull down NBST1.
Referring to Fig. 6, negative voltage bit line provided by the invention writes auxiliary SRAM circuit, including,
N number of SRAM memory cell, each SRAM memory cell connect one first bit line BL and one second bit line BLB；In figure
Storage unit CELL [0] and storage unit CELL [n-1] are only indicated, remaining is indicated with ellipsis；
One the first transistor MN0, Yu Yi first on or off the first bit line BL and one under the action of write enable signal WT0
Ground voltage VSS；
One second transistor MN1, Yu Yi second on or off the second bit line BL and ground under the action of write enable signal WT1
Voltage VSS；
One comparing unit compares the voltage difference of the first bit line BL and the second bit line BLB under the action of an enable signal, and
Export the first signal SA_OUT0 and second signal SA_OUT1；
Between first signal SA_OUT0 and the first bit line BL connect one first coupled capacitor C0, second signal SA_OUT1 with
It is connected between second bit line BLB under one second coupled capacitor C1, the first signal SA_OUT0 imposes a condition in first in the first bit line
Coupling is generated to couple on the second bit line BLB under a negative voltage or second signal SA_OUT1 impose a condition in second and be generated on BL
One negative voltage.
The present invention compares the voltage difference of the first bit line BL and the second bit line BLB, the electricity of the first bit line BL by comparing unit
When pressure is higher than the voltage of the second bit line BLB, the first signal SA_OUT0 output HIGH voltage, second signal SA_OUT1 exports low electricity
Pressure；When the voltage of second bit line BLB is higher than the voltage of the first bit line BL, the first signal SA_OUT0 exports low-voltage, second signal
SA_OUT1 output HIGH voltage.According to needing to be written data 1 or data 0, pass through the first signal SA_OUT0 or second signal SA_
OUT1 is coupled on the first bit line BL or the second bit line BLB generates a negative voltage, so that data are easier to be written into SRAM
In storage unit.
NMOS tube can be used in above-mentioned the first transistor, and NMOS tube can also be used in above-mentioned second transistor, writes in first
Enable signal WT0 or the second write enable signal WT1 is connected when being high voltage.
Negative voltage bit line of the invention writes auxiliary SRAM circuit, and comparing unit can use sense amplifier SA (Sense
Amplifier), sense amplifier SA has first input end and the second input terminal and the first output end and second output terminal, the
One input terminal is connect with the first bit line BL, the second input terminal and the second bit line BLB connection, under the action of an enable signal SAE
Compare the voltage difference of the first bit line BL and the second bit line BLB, and the first signal SA_OUT0 is exported by the first output end and is passed through
Second output terminal exports second signal SA_OUT1；Connection one first couples electricity between first signal SA_OUT0 and the first bit line BL
Hold C0；One second coupled capacitor C1 is connected between second signal SA_OUT1 and the second bit line BLB；First signal SA_OUT0 is in
One impose a condition under on the first bit line BL coupling generate under a negative voltage or second signal SA_OUT1 impose a condition in second
Coupling generates a negative voltage on second bit line BLB.
In traditional SRAM write operating process, sense amplifier SA not will start, and only need to read SRAM number
According to when just open it, present invention sense amplifier SA in write operation is also started up, and by sense amplifier SA's
A pair of of difference output SA_OUT0 and SA_OUT1 is connected respectively on bit line negative voltage coupled capacitor C0 and coupled capacitor C1, as
Bit line negative voltage coupling control signal.The enable signal of sense amplifier SA is SAE, the table when enable signal SAE is high voltage
Show that sense amplifier SA starting judges the voltage difference on the first bit line BL and the second bit line BLB, if the voltage of the first bit line BL is high
In the voltage of the second bit line BLB, then sense amplifier SA output 1, i.e. the first signal SA_OUT0 is equal to 1, second signal SA_
OUT1 is equal to 0；If the voltage of the first bit line BL is lower than the voltage of the second bit line BLB, sense amplifier SA exports 0, i.e., first
Signal SA_OUT0 is equal to 0 second signal SA_OUT1 and is equal to 1.During write operation, the first bit line BL or the second bit line BLB meeting
It is first pulled down to ground voltage VSS, the first bit line BL and the second bit line BLB will have voltage difference at this time, and voltage difference is equal to electricity
The size of source voltage VDD, enable signal SAE gets higher starting sense amplifier SA, the output SA_ of sense amplifier SA by low later
First bit line BL or the second bit line BLB are coupled to negative voltage by coupled capacitor C0/C1 by OUT0/SA_OUT1, and realization is write auxiliary
It helps.Fig. 7 is timing diagram of the invention.The present invention shares induction amplifier circuit by reading with SRAM, without being bit line negative electricity
The individually designed control circuit of volt circuit, the circuit area of occupancy are smaller.
Negative voltage bit line of the invention writes auxiliary SRAM circuit, and each SRAM memory cell can use as shown in Figure 1
SRAM memory cell, including,
One first switch device MPG1 controllably connects the first bit line BL to 1 first under a corresponding wordline effect
Node N1；
The second bit line BLB to 1 second is controllably connected under the action of one second switch device MPG0, Yu Tongyi wordline
Node N0；
One basic unit of storage, when first node N1 is high voltage and second node N0 is low-voltage, the data of storage
It is 1；Or when first node N1 is low-voltage and second node N0 is high voltage, the data of storage are 0.
Negative voltage bit line of the invention writes auxiliary SRAM circuit, and basic unit of storage includes,
First PMOS tube ML1, the selectively turn-on power voltage VDD and first under the voltage effect of a second node N0
Node N1；
Second PMOS tube ML0, selectively turn-on power voltage VDD and the second section under the voltage effect of first node N1
Point N0；
First node N1 and ground voltage VSS is selectively connected under the voltage effect of second node N0 in first NMOS tube；
Second node N0 and ground voltage VSS is selectively connected under the effect of first node N1 voltage in second NMOS tube.
SRAM memory cell of the invention is not limited to above-mentioned structure.
Negative voltage bit line of the invention writes auxiliary SRAM circuit, and the first above-mentioned bit line BL is along N number of SRAM memory cell
Orientation is arranged and is located at same one side of SRAM memory cell；Row of the second above-mentioned bit line BLB along N number of SRAM memory cell
The another side opposite with the first bit line BL setting on column direction.
The method that negative voltage bit line provided by the invention writes auxiliary, applied in above-mentioned SRAM circuit, such as Fig. 7, Fig. 8 institute
Show, include the steps that data 0 are written:
Step 11, the first bit line BL is pulled down to ground voltage VSS；
Step 12, compare the voltage difference of the first bit line BL and the second bit line BLB and export the first signal SA_OUT0 and second
Signal SA_OUT1；
Step 13, the connection of the first bit line BL and ground voltage VSS is disconnected, the first signal SA_OUT0 passes through the first coupling electricity
Appearance C0 is coupled on the first bit line BL obtains a negative voltage；
Step 14, the wordline WL of a SRAM memory cell is selected, and the first bit line BL is connected to first node N1, first segment
Point N1 is low-voltage and second node N0 is pulled to high voltage.
The method that negative voltage bit line of the invention writes auxiliary, as shown in figure 9, further including the steps that data 1 are written:
Step 21, the second bit line BL is pulled down to ground voltage VSS；
Step 22, compare the voltage difference of the first bit line BL and the second bit line BLB and export SA_OUT0 and second signal SA_
OUT1；
Step 23, the connection of the second bit line BLB and ground voltage VSS is disconnected, second signal SA_OUT1 passes through the second coupling electricity
Appearance C0 is coupled on the second bit line BLB obtains a negative voltage；
Step 24, the wordline WL of a SRAM memory cell is selected, and the second bit line is connected to second node, and second node is
Low-voltage and first node is pulled to high voltage.
The method that negative voltage bit line of the invention writes auxiliary, the voltage of the first bit line is higher than the second bit line in above-mentioned steps 2
Voltage when, the first signal output HIGH voltage, second signal export low-voltage；The voltage of second bit line is higher than the electricity of the first bit line
When pressure, the first signal exports low-voltage, second signal output HIGH voltage.
Referring to Fig. 7, for data 0 are written, concrete methods of realizing is as follows: the first write enable signal WT0 is become by low-voltage
For high voltage, the first bit line BL is connected with ground voltage VSS, and the first bit line BL is pulled down to ground voltage VSS；As enable signal SAE
To indicate that sense amplifier SA starting judges the voltage difference on the first bit line BL and the second bit line BLB, the first bit line when high voltage
The voltage of BL should be lower than the voltage of the second bit line BLB, and sense amplifier SA output at this time 0, i.e. the first signal SA_OUT0 is equal to
0 second signal SA_OUT1 is equal to 1；First write enable signal WT0 is lower voltage by high voltage, and the first signal SA_OUT0 passes through coupling
Conjunction capacitor couples on the first bit line BL obtains a negative voltage, when the wordline WL of a SRAM memory cell is selected, the first bit line
BL is connected to first node N1, and first node N1 is low-voltage and second node N0 is pulled to high voltage, realizes write-in data
0。
The foregoing is merely preferred embodiments of the present invention, are not intended to limit embodiments of the present invention and protection model
It encloses, to those skilled in the art, should can appreciate that all with made by description of the invention and diagramatic content
Equivalent replacement and obviously change obtained scheme, should all be included within the scope of the present invention.
Claims (10)
1. negative voltage bit line writes auxiliary SRAM circuit, which is characterized in that including,
N number of SRAM memory cell, each SRAM memory cell connect one first bit line and one second bit line；
One the first transistor, the first bit line and ground voltage described on or off under the action of the first write enable signal of Yu Yi；
One second transistor, the second bit line described on or off and the ground electricity under the action of the second write enable signal of Yu Yi
Pressure；
One comparing unit, the voltage difference of first bit line and second bit line under the action of an enable signal, and
Export the first signal and the second signal；
One first coupled capacitor, the second signal and the second are connected between first signal and first bit line
One second coupled capacitor is connected between line, first signal is coupled on first bit line under imposing a condition in first and generated
One negative voltage or the second signal couple on second bit line under imposing a condition in second and generate a negative voltage.
2. negative voltage bit line according to claim 1 writes auxiliary SRAM circuit, which is characterized in that N number of SRAM storage
Unit is separately connected a corresponding wordline, wherein carrying out when a wordline is selected to the corresponding SRAM memory cell
Write operation.
3. negative voltage bit line according to claim 1 writes auxiliary SRAM circuit, which is characterized in that the electricity of first bit line
When pressure is higher than the voltage of second bit line, the first signal output HIGH voltage, the second signal exports low-voltage；It is described
When the voltage of second bit line is higher than the voltage of first bit line, first signal exports low-voltage, and the second signal is defeated
High voltage out.
4. negative voltage bit line according to claim 1 writes auxiliary SRAM circuit, which is characterized in that the comparing unit uses
Sense amplifier, the sense amplifier have first input end and the second input terminal and the first output end and second output terminal,
The first input end is connect with first bit line, and second input terminal is connect with second bit line, and described first is defeated
Outlet is for exporting first signal, and the second output terminal is for exporting the second signal.
5. negative voltage bit line according to claim 3 writes auxiliary SRAM circuit, which is characterized in that each SRAM storage
Unit includes,
One first switch device controllably connects first bit line to a first node under a corresponding wordline effect；
One second switch device controllably connects second bit line to a second node under the action of Yu Suoshu wordline；
One basic unit of storage, when Yu Suoshu first node is high voltage and the second node is low-voltage, the data of storage
It is 1；Or when the first node is low-voltage and the second node is high voltage, the data of storage are 0.
6. negative voltage bit line according to claim 5 writes auxiliary SRAM circuit, which is characterized in that the basic unit of storage
Including,
First PMOS tube, selectively turn-on power voltage and the first node under the voltage effect of a second node；
The supply voltage and second section is selectively connected under the voltage effect of Yu Suoshu first node in second PMOS tube
Point；
The first node and ground voltage is selectively connected under the voltage effect of Yu Suoshu second node in first NMOS tube；
The second node and the ground voltage is selectively connected under the effect of Yu Suoshu first node voltage in second NMOS tube.
7. negative voltage bit line according to claim 1 writes auxiliary SRAM circuit, which is characterized in that first bit line is along N
The orientation of a SRAM memory cell is arranged and is located at same one side of the SRAM memory cell；Second bit line edge
The another side opposite with first bit line setting in the orientation of N number of SRAM memory cell.
8. the method that negative voltage bit line writes auxiliary, which is characterized in that it is applied in SRAM circuit described in claim 1,
Each SRAM memory cell includes,
One first switch device controllably connects first bit line to a first node under a corresponding wordline effect；
One second switch device controllably connects second bit line to a second node under the action of Yu Suoshu wordline；
Further include the steps that data 0 are written:
Step 11, first bit line is pulled down to ground voltage；
Step 12, the voltage difference of first bit line and second bit line and the first signal and the second signal are exported；
Step 13, the connection of first bit line and the ground voltage is disconnected, first signal passes through the first coupling electricity
Hold the coupling on first bit line and obtains a negative voltage；
Step 14, the wordline of a SRAM memory cell is selected, and first bit line is connected to a first node, the first segment
Point is low-voltage and the second node is pulled to high voltage.
9. the method that negative voltage bit line according to claim 8 writes auxiliary, which is characterized in that the step including data 1 are written
It is rapid:
Step 21, second bit line is pulled down to ground voltage；
Step 22, the voltage difference of first bit line and second bit line and the first signal and the second signal are exported；
Step 23, the connection of second bit line and the ground voltage is disconnected, the second signal passes through the second coupling electricity
Hold the coupling on second bit line and obtains a negative voltage；
Step 24, the wordline of a SRAM memory cell is selected, and second bit line is connected to the second node, and described second
Node is low-voltage and the first node is pulled to high voltage.
10. the method that negative voltage bit line according to claim 8 or claim 9 writes auxiliary, which is characterized in that described in step 2
When the voltage of one bit line is higher than the voltage of second bit line, the first signal output HIGH voltage, the second signal output
Low-voltage；When the voltage of second bit line is higher than the voltage of first bit line, first signal exports low-voltage, described
Second signal output HIGH voltage.
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| US10541023B2 (en) * | 2017-09-04 | 2020-01-21 | Mediatek Inc. | Data line control circuit using write-assist data line coupling and associated data line control method |
| CN109584928B (en) * | 2018-11-30 | 2021-07-23 | 中国科学院微电子研究所 | Write assist circuit and write assist method for static random access memory |
| CN112992202B (en) | 2021-03-24 | 2022-08-05 | 长鑫存储技术有限公司 | Sense amplifier, memory and control method |
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