CN107014462B - A kind of interface ASIC of capacitance level transducer - Google Patents
A kind of interface ASIC of capacitance level transducer Download PDFInfo
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- CN107014462B CN107014462B CN201710232243.1A CN201710232243A CN107014462B CN 107014462 B CN107014462 B CN 107014462B CN 201710232243 A CN201710232243 A CN 201710232243A CN 107014462 B CN107014462 B CN 107014462B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01F—MEASURING VOLUME, VOLUME FLOW, MASS FLOW OR LIQUID LEVEL; METERING BY VOLUME
- G01F23/00—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm
- G01F23/22—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water
- G01F23/26—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water by measuring variations of capacity or inductance of capacitors or inductors arising from the presence of liquid or fluent solid material in the electric or electromagnetic fields
- G01F23/263—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water by measuring variations of capacity or inductance of capacitors or inductors arising from the presence of liquid or fluent solid material in the electric or electromagnetic fields by measuring variations in capacitance of capacitors
- G01F23/266—Indicating or measuring liquid level or level of fluent solid material, e.g. indicating in terms of volume or indicating by means of an alarm by measuring physical variables, other than linear dimensions, pressure or weight, dependent on the level to be measured, e.g. by difference of heat transfer of steam or water by measuring variations of capacity or inductance of capacitors or inductors arising from the presence of liquid or fluent solid material in the electric or electromagnetic fields by measuring variations in capacitance of capacitors measuring circuits therefor
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Abstract
A kind of capacitance level transducer interface ASIC, belongs to sensor field.End is grounded switch one by one, switch 21 terminates reference voltage source, the common node of two other end of switch one and switch connects as driving end with capacitance level transducer one end, the capacitance level transducer other end connects with the one end reference capacitance Cref, the reference capacitance Cref other end connects with the common node of four one end of switch three and switch, three other end of switch ground connection；Public five one end of termination switch and front end sample charge amplifier in of capacitance level transducer and reference capacitance Cref, five other end of switch ground connection；Front end sample charge amplifier out connects voltage amplifier circuit input terminal；Voltage amplifier circuit output termination correlated double sampling circuit input terminal, correlated double sampling circuit output termination PI controller input terminal；PI controller output end connects low-pass filter input terminal, and first low pass filter output connects with four other end of switch, to constitute the closed loop detection of capacitance level transducer output capacitance.
Description
Technical field
The present invention relates to a kind of capacitance level transducer interface ASIC, belong to sensor field.
Background technique
Level measuring technology is widely used, and common measurement method has float method, capacitance method, supercritical ultrasonics technology etc..Wherein, electric
Appearance formula liquid level sensor is often applied to aerospace field due to the advantages that its dynamic response is good, stability is strong, and measurement is former
Reason is to obtain liquid level information by two interelectrode capacitances in detection liquid.To low temperature during space launch vehicle lift-off
There are many means of monitoring and the measurement of liquid propellant, and capacitance type liquid level measuring method is one of most common method.
The weak capacitive detection circuit of capacitance level transducer mostly uses traditional electricity in country's space transporter at present
Capacitance measuring circuits structure, and be the measuring circuit built using the traditional discrete element such as resistance, capacitor, thus measurement accuracy compared with
Low (only 10-14Farad magnitude), faint capacitance signal is easy to be flooded by noise signal, and this severely limits delivery fire
The resolution ratio of arrow level gauging is unable to satisfy the demand of New Launch high-precision liquid level measurement.And use microelectronic technique
The specific integrated circuit (ASIC) of production has the characteristics that small in size, Highgrade integration, high-precision and application are easy, just gradually takes
For discrete component measuring circuit.Therefore, design high-precision, high-resolution weak capacitance detection ASIC are for improving carrying space
The performance of capacitance level transducer plays a crucial role in rocket.
Summary of the invention
Present invention aims at a kind of capacitance level transducer interface ASIC is proposed, in order to solve domestic space flight fortune at present
The problem of carrying traditional weak capacitive detection circuit low measurement accuracy of capacitance level transducer in rocket, proposes a kind of base
In the capacitance level transducer interface specific integrated circuit (ASIC) of novel low imbalance temperature drift three-stage operational amplifier, realize
Single-chip integrated.The ASIC is made of microelectronic technique, solves capacitance level transducer weak capacitive in carrier rocket
The miniaturization of detection circuit, Highgrade integration and the easy problem of application, realize high linearity, high capacitance Measurement Resolution and
High capacitance measures stability, while also meeting the requirement of the environmental adaptability of capacitance level transducer interface ASIC.
Suitable for high-precision, high-resolution capacitance level transducer weak capacitance detection.
Realize above-mentioned purpose, the technical solution adopted by the present invention is as follows:
A kind of interface ASIC of capacitance level transducer, comprising: front end sample charge amplifier, voltage amplifier circuit,
Correlated double sampling circuit, low-pass filter, reference voltage source, switch one, switch two, switch three, switch four, is opened PI controller
Close five and reference capacitance；
One end of the switch one is grounded, a termination reference voltage source of the switch two, the other end of switch one
Connect as driving end with one end of capacitance level transducer with the common node of the other end of switch two, capacitance type liquid level passes
The other end of sensor connects with one end of reference capacitance, one end of the other end of reference capacitance and one end of switch three and switch four
Common node connect, the other end of switch ground connection；The public termination switch five of capacitance level transducer and reference capacitance
The input terminal of one end and front end sample charge amplifier connects, and switch five is reset switch, and the other end of switch five is grounded, front end
The input terminal of the output termination voltage amplifier circuit of sample charge amplifier；The output of the voltage amplifier circuit terminates related
The input terminal of dual-sampling circuit, the input terminal of the output termination PI controller of correlated double sampling circuit；The PI controller
The output end of the input terminal of low-pass filter of output termination, low-pass filter connects with the other end of switch four.
The beneficial effect of the present invention compared with the existing technology is: a kind of capacitance level transducer proposed by the present invention connects
Mouth ASIC, is detected using closed loop configuration, realizes output voltage Vout and the linear pass capacitance level transducer output capacitance C
System, and the very high linearity is realized, capacitance detecting is non-linear to reach 0.01%.Before being eliminated using correlated double sampling circuit
DC offset voltage, the low frequency 1/f of end sample charge amplifier and voltage amplifier circuit two parts bring operational amplifier make an uproar
Error charge caused by sound and the injection of analog switch charge, clock feedthrough, realizes high linearity measurement.In voltage amplifier circuit
One R1 of resistance, two R2 of resistance are arranged outside chip, therefore the adjustable gain of voltage amplifier circuit, by improving voltage amplifier circuit
Voltage gain can inhibit the noise of late-class circuit, to improve the capacitance signal resolution ratio of interface asic chip.PI control
Operational amplifier 105 in device uses the three-stage operational amplifier of low maladjustment voltage temperature coefficient, so that interface ASIC be made to have
Very low zero-bit temperature coefficient.
To sum up, the present invention solves the miniaturization of capacitance level transducer weak capacitive detection circuit in carrier rocket,
The problem of Highgrade integration and application simplicity realizes high linearity, high capacitance Measurement Resolution and high capacitance measurement stability.
Detailed description of the invention
Fig. 1 is the circuit diagram of the interface ASIC of capacitance level transducer of the present invention a kind of；
Fig. 2 is the working timing figure of the interface ASIC of capacitance level transducer of the present invention a kind of；
Fig. 3 is the physical circuit figure of operational amplifier.
In figure: front end sample charge amplifier 101, voltage amplifier circuit 102, correlated double sampling circuit 103, PI controller
104, low-pass filter 106, reference voltage source Vref, reference capacitance Cref, one S1 of switch, two S2 of switch, three S3 of switch, switch
Four S4, five S5 of switch, six S6 of switch, switch July 1st S7-1, seven or two S7-2 of switch, eight S8 of switch, nine S9 of switch, one C1 of capacitor,
Two CF of capacitor, three C2 of capacitor, four C3 of capacitor, five C4 of capacitor, six Cp1 of capacitor, seven Cp2 of capacitor, eight C5 of capacitor, operational amplifier one
A1, two A2 of operational amplifier, three A3 of operational amplifier, four A4 of operational amplifier, five A5 of operational amplifier, operational amplifier six
A6, one R1 of resistance, two R2 of resistance, three R3 of resistance, four R4 of resistance, five R5 of resistance, six R6 of resistance, seven R7 of resistance, eight R8 of resistance, electricity
Hinder nine R9, bias voltage 1, bias voltage 22, bias voltage 33, one Q1 of PMOS tube, two Q2 of PMOS tube, three Q3 of PMOS tube,
Four Q4 of NMOS tube, five Q5 of NMOS tube, six Q6 of PMOS tube, seven Q7 of PMOS tube, eight Q8 of PMOS tube, nine Q9 of PMOS tube, PMOS tube ten
Q10,11 Q11 of NMOS tube, 12 Q12 of NMOS tube, 13 Q13 of NMOS tube, 14 Q14 of NMOS tube, 15 Q15 of PMOS tube,
16 Q16 of NMOS tube.
Further description of the technical solution of the present invention with reference to the accompanying drawing, and however, it is not limited to this, all to this
Inventive technique scheme is modified or replaced equivalently, and without departing from the spirit and scope of the technical solution of the present invention, should all be covered
Within the protection scope of the present invention.
Specific embodiment
Specific embodiment 1: as shown in Figure 1, a kind of interface ASIC of capacitance level transducer, comprising: front end charge
Sampling amplifier 101, voltage amplifier circuit 102, correlated double sampling circuit 103, PI controller 104, low-pass filter 106, ginseng
Examine voltage source Vref, one S1 of switch, two S2 of switch, three S3 of switch, four S4 of switch, switch five S5 and reference capacitance Cref；
One end of one S1 of switch is grounded, a termination reference voltage source Vref of two S2 of switch, switch one
The common node of the other end of two S2 of the other end and switch of S1 connects as driving end with one end of capacitance level transducer,
The other end of capacitance level transducer connects with one end of reference capacitance Cref, the other end and switch three of reference capacitance Cref
The common node of one end of one end and four S4 of switch of S3 connects, the other end ground connection of switch S3；Capacitance level transducer with
One end of public five S5 of termination switch of reference capacitance Cref and the input terminal of front end sample charge amplifier 101 connect, switch
Five S5 are reset switch, and the other end of five S5 of switch is grounded, the output termination voltage amplification electricity of front end sample charge amplifier 101
The input terminal on road 102；The input terminal of the output termination correlated double sampling circuit 103 of the voltage amplifier circuit 102, it is related double
The input terminal of the output termination PI controller 104 of sample circuit 103；The output of the PI controller 104 terminates low-pass filtering
The output end of the input terminal of device 106, low-pass filter 106 connects with the other end of four S4 of switch (to constitute capacitance type liquid level
The closed loop of sensor output capacitance detects, and improves the linearity of capacitance detecting).
Reference voltage source Vref is generated by bandgap voltage reference.The output quantity of capacitance level transducer is capacitor, there is two
A output terminal.
Specific embodiment 2: Fig. 1 and Fig. 3 illustrate that present embodiment, present embodiment make further embodiment one
Illustrate, the front end sample charge amplifier 101 includes six S6 of switch, switch July 1st S7-1, seven or two S7-2 of switch, capacitor one
The non-inverting input terminal of C1, two CF of capacitor and operational amplifier one A1, one A1 of operational amplifier and one end of one C1 of capacitor and switch
The common node of one end of seven or two S7-2 connects, the common node of the other end of the other end and seven or two S7-2 of switch of one C1 of capacitor
Ground connection, input terminal of the one end of six S6 of switch as front end sample charge amplifier 101, the other end and switch seven of six S6 of switch
The common node of one end of two CF of one end and capacitor of one S7-1 connects and is connected to the anti-phase input of one A1 of operational amplifier jointly
End, the other end of switch July 1st S7-1, the common node of the output end of one A1 of the other end and operational amplifier of two CF of capacitor are made
For the output end of front end sample charge amplifier 101.
When entering amplifier error pickup phase P2, one A1 of prime operational amplifier is electric by offset voltage and low-frequency noise
Pressure is applied to inverting input terminal.When entering charge amplifier preparation phase P3, July 1st S7-1 is switched on two CF of capacitor
Cause charge injection and clock feed-through effect.In order to reduce influence of the Charge injection effect to one A1 of operational amplifier, in operation
Seven or two S7-2 of switch and one C1 of capacitor is set at the positive input of one A1 of amplifier.Therefore, seven or two S7-2 of switch and electricity
Hold a C1 and plays the role of single order counteracting to the parasitic capacitance of one A1 of operational amplifier.
Specific embodiment 3: as shown in Figures 1 and 3, present embodiment is described further embodiment one, described
Voltage amplifier circuit 102 include one R1 of resistance, two R2 of resistance, three R3 of resistance, four R4 of resistance, two A2 of operational amplifier and operation
Three A3 of amplifier, input of the non-inverting input terminal of two A2 of operational amplifier as voltage amplifier circuit 102, two A2 of operational amplifier
Inverting input terminal connect with the common node of one end of two R2 of one end of one R1 of resistance and resistance, another termination of one R1 of resistance
The common node on ground, one end of three R3 of the other end and resistance of two R2 of resistance connects with the output end of two A2 of operational amplifier, electricity
The other end for hindering three R3 connects with the common node of one end of four R4 of resistance with the inverting input terminal of three A3 of operational amplifier, resistance
Output end of the common node of the output end of three A3 of the other end and operational amplifier of four R4 as voltage amplifier circuit 102.
It can change voltage by adjusting one R1 of resistance, four R4 of two R2 of resistance, three R3 of resistance and resistance resistance value size and put
The amplification factor of big circuit, to improve liquid level sensor capacitance detecting resolution ratio.
Specific embodiment 4: as shown in Figures 1 and 3, present embodiment is described further embodiment one, described
Correlated double sampling circuit 103 include five R5 of resistance, three C2 of capacitor, four C3 of capacitor, eight S8 of switch, nine S9 of switch and operation amplifier
Four A4 of device, input terminal of the one end of five R5 of resistance as correlated double sampling circuit 103, the other end and three C2 of capacitor of five R5 of resistance
One end connect, the other end of three C2 of capacitor connects with the common node of one end of nine S9 of one end of eight S8 of switch and switch, opens
The common node ground connection of one end of four C3 of the other end and capacitor of nine S9 is closed, four C3's of the other end and capacitor of eight S8 of switch is another
The common node at end is connected to the non-inverting input terminal of four A4 of operational amplifier, the inverting input terminal and operation of four A4 of operational amplifier
The connected output end as correlated double sampling circuit 103 of four A4 output end of amplifier.
Correlated double sampling circuit is electric by the DC maladjustment of the amplifier of front stage circuits, low-frequency noise by double sampled three C2 of capacitor
Pressure and the charge injection of switch July 1st S7-1, clock feedthrough error are stored, then by disconnecting nine S9 of switch in switch nine
It is obtained as caused by the difference of the quantity of electric charge on sensor capacitance C and reference capacitance Cref at the common node of S9 and eight S8 of switch
Sampling and outputting voltage.Then by the way that eight S8 of switch to be closed so that sampling and outputting voltage is maintained on four C3 of capacitor.In order to prevent
Charge leakage on four C3 of capacitor, four C3 of capacitor are followed by the buffer of high input resistance.
Specific embodiment 5: as shown in Figures 1 and 3, present embodiment is described further embodiment one or four,
The PI controller 104 includes six R6 of resistance, seven R7 of resistance, five C4 of capacitor and operational amplifier five A5, and the one of six R6 of resistance
The input terminal as PI controller 104 is held, one end of five C4 of the other end and capacitor of six R6 of resistance is connected to operational amplifier jointly
The inverting input terminal of five A5, the non-inverting input terminal ground connection of five A5 of operational amplifier, the other end of five C4 of capacitor is with seven R7's of resistance
One end connects, and the common node of the output end of five A5 of the other end and operational amplifier of seven R7 of resistance is as PI controller 104
Output end.
PI controller 104 receives the output DC voltage from correlated double sampling circuit 103, and accumulates to output voltage
Partite transport is calculated and reverse phase ratio enlargement, so that the variation of 104 output voltage of PI controller is more significant, it is defeated to accelerate low-pass filter 106
Voltage Vout reaches the speed of stable state out.
Specific embodiment 6: as shown in Figures 1 and 3, present embodiment is described further embodiment one, described
Low-pass filter 106 include eight R8 of resistance, six A6 of nine R9 of resistance, eight C5 of capacitor and operational amplifier, one end of eight R8 of resistance
As the input terminal of low-pass filter 106, the other end of eight R8 of resistance, one end of eight C5 of one end and capacitor of nine R9 of resistance public affairs
Conode connects with the inverting input terminal of six A6 of operational amplifier, the non-inverting input terminal ground connection of six A6 of operational amplifier, resistance nine
Output of the common node as low-pass filter 106 of the other end of R9, six A6 of the other end and operational amplifier of eight C5 of capacitor
End.
The cutoff frequency of low-pass filter 106 is arranged smaller, to filter out the high-frequency noise in output voltage Vout.
Specific embodiment 7: as shown in Figures 1 and 3, present embodiment is described further embodiment five, described
Five A5 of operational amplifier include bias voltage 1, bias voltage 22, bias voltage 33, one Q1 of PMOS tube, PMOS tube two
Q2, three Q3 of PMOS tube, four Q4 of NMOS tube, five Q5 of NMOS tube, six Q6 of PMOS tube, seven Q7 of PMOS tube, eight Q8 of PMOS tube, PMOS tube nine
Q9, ten Q10 of PMOS tube, 11 Q11 of NMOS tube, 12 Q12 of NMOS tube, 13 Q13 of NMOS tube, 14 Q14 of NMOS tube, PMOS tube
15 Q15,16 Q16 of NMOS tube, seven Cp2 of six Cp1 of capacitor and capacitor；
Four Q4 of NMOS tube, five Q5 of NMOS tube, 13 Q13 of NMOS tube, 14 Q14 of NMOS tube and the NMOS tube 16
The common node of the source electrode of Q16 is grounded, one Q1 of PMOS tube, six Q6 of PMOS tube, nine Q9 of PMOS tube, ten Q10 of PMOS tube and PMOS tube
The common node of the source electrode of 15 Q15 meets VCC, and the grid of six Q6 of one Q1 of PMOS tube and PMOS tube connects bias voltage 1 jointly；
The common node of the source electrode of three Q3 of two Q2 of PMOS tube and PMOS tube connects the drain electrode of one Q1 of PMOS tube, two Q2's of PMOS tube
Grid is the inverting input terminal of five A5 of operational amplifier, and the grid of three Q3 of PMOS tube is the homophase input of five A5 of operational amplifier
End, the drain electrode of two Q2 of PMOS tube, the drain electrode of four Q4 of NMOS tube, eight Q8 of PMOS tube grid common node connect NMOS tube Q4 and
The common node of the common node of NMOS tube Q5 grid, the drain electrode of the drain electrode and NMOS tube Q5 of PMOS tube Q3 connects the grid of PMOS tube Q7
The common node of seven one end Cp2 of pole, the grid of NMOS tube Q16 and capacitor；
The drain electrode of six Q6 of common node PMOS tube of the source electrode of seven Q7 of PMOS tube, eight Q8 of PMOS tube, the leakage of seven Q7 of PMOS tube
Pole connects the common node of the drain electrode of 13 Q13 of source electrode and NMOS tube of 11 Q11 of NMOS tube, and the drain electrode of eight Q8 of PMOS tube meets NMOS
The common node of six one end Cp1 of drain electrode and capacitor of the source electrode, 14 Q14 of NMOS tube of 12 Q12 of pipe；
The common node of the grid of 14 Q14 of 13 Q13 of NMOS tube and NMOS tube connects bias voltage 33, NMOS tube 11
The common node of the grid of 12 Q12 of Q11 and NMOS tube connects bias voltage 22, the drain electrode and PMOS tube nine of 11 Q11 of NMOS tube
The common node of the drain electrode of Q9 connects the common node of ten Q10 grid of nine Q9 of PMOS tube and PMOS tube, the drain electrode of ten Q10 of PMOS tube and
The common node of the drain electrode of 12 Q12 of NMOS tube connects the grid of 15 Q15 of PMOS tube；
The drain electrode of 15 Q15 of PMOS tube, the drain electrode of 16 Q16 of NMOS tube, capacitor six Cp1 and seven Cp2 of capacitor the other end
Output end of the common node as operational amplifier A5.
The offset voltage of five A5 of operational amplifier in PI controller 104 will be reflected directly in sensor output voltage
In Vout, offset temperature coefficient also will be as the crucial composition portion in the temperature coefficient of capacitance level transducer interface ASIC
Point.Its open-loop gain will affect the linearity of interface ASIC, therefore five A5 of operational amplifier is using three-stage operational amplifier topology
Structure, second level capacitance compensation, to realize that the low offset temperature coefficient of five A5 of operational amplifier uses second level differential amplification structure.Its
The output of middle first order amplifier is connected by differential mode with the input of second level amplifier, by the amplifier first order and the second level it
Between matching be converted to second level amplifier matching internal, greatly reduce between the operational amplifier first order and the second level
Transistor-matched requirement, to effectively reduce the offset voltage temperature coefficient of operational amplifier.
The working principle of entire interface ASIC is: by by the testing capacitance of capacitance level transducer and reference capacitance pole
On error sample charge to capacitor CF on plate, then by feeding back output voltage to four S4 of switch after the processing of circuit of rear class
One end, the zero error charge on the final testing capacitance and reference capacitance pole plate for realizing capacitance level transducer meets:
When circuit works, entire duty cycle T includes 5 time phases, and charge resets phase P1, amplifier error picks up
Phase P2, charge amplifier prepare phase P3, sample charge phase P4, integral feedback phase P5.Capacitive detection circuit uses
Cmos switch capacitance detecting mode, effectively improves charge detection ability, utilizes the circuits such as large area input P pipe, correlated-double-sampling
The low frequency 1/f noise of structure reduction charge amplifier.
Illustrate circuit in the working condition of each phase below with reference to Fig. 2.
In P1 phase, five S5 of switch closure, so that the common node of sensor capacitance C and reference capacitance Cref are quickly released
Charge, so that the current potential is quickly released to zero potential.In this phase, switch two S2, S4 tetra- are closed, a switch S1 and switch three
S3 is disconnected, so that reference voltage Vref, output voltage Vout loads the top crown in sensor capacitance C, reference capacitance respectively
The bottom crown of Cref.
In P2 phase, five S5 of switch is disconnected, and in the very short time after five S5 of switch disconnection, six S6 of switch closure.
The common end of sensor capacitance C and reference capacitance Cref are connected with the inverting input terminal of one A1 of prime operational amplifier, open at this time
July 1st S7-1 and seven or two S7-2 of switch closure is closed, eight S8 of switch is disconnected, and S9 nine is closed, front end sample charge amplifier 101 and electricity
The DC offset voltage of operational amplifier in amplifying circuit, low-frequency noise voltage and the charge injection for switching July 1st S7-1 are pressed, when
Error charge caused by clock feedthrough is stored on double sampled capacitor (capacitor three) C2.
In P3 phase, switchs July 1st S7-1 and seven or two S7-2 of switch and disconnect, on one A1 feedback network of operational amplifier only
Capacitor CF(capacitor two), which prepares for electric charge transfer.
In P4 phase, two S2 of switch and four S4 of switch are disconnected, one S1 of switch and three S3 of switch closure in the very short time,
Therefore, there is the pulse voltage that an amplitude is-Vref in the top crown of sensor capacitance C, meanwhile, the bottom crown of capacitor Cref
There is the pulse voltage that an amplitude is Vout.Occur electric charge transfer at this time, sensor capacitance C and reference capacitance Cref's is public
The electric charge transfer of end part is to feedback capacity CF(capacitor two) on.Nine S9 of switch is disconnected at this time, by switching after the of short duration time
Eight S8 closure, by the straight of the operational amplifier in front end sample charge amplifier and voltage amplifier circuit of being eliminated on four C3 of capacitor
Flow offset voltage, low-frequency noise voltage and the charge injection for switching July 1st S7-1, adopting after error charge caused by clock feedthrough
Sample output voltage.Eight S8 of switch is backed off after closure a period of time, before eight S8 of switch being kept to disconnect on four C3 of capacitor
Sampling and outputting voltage obtained.
In P5 phase, two S2 of switch, four S4 of switch, nine S9 of switch, switch July 1st S7-1, seven or two S7-2 of switch closure are opened
It closes a S1, three S3 of switch, five S5 of switch and six S6 of switch to disconnect, feed circuit is mutually separated with capacitive detection circuit at this time.PI control
Device 104 processed integrates the sample charge output voltage kept on four C3 of capacitor, and the voltage after integral is passed through low pass filtered
Obtain the output voltage of integrated circuit after wave device 106, the low-pass cut-off frequencies design of low-pass filter 106 it is very low, PI is controlled
The output voltage of device 104 processed carries out reverse phase, and eliminates radio-frequency component therein.Low-pass filter 106 is by the defeated of integrated circuit
Voltage Feedback is to one end of four S4 of switch out, to realize the closed loop detection of capacitance level transducer output capacitance.
After P5 phase, circuit reenters P1 phase, the execution working sequence of each switch in cycles, final defeated
Voltage makes the quantity of electric charge on sensor capacitance C and reference capacitance on Cref equal out, reaches stable state, and output voltage is kept not
Become.
Claims (7)
1. a kind of interface ASIC of capacitance level transducer, comprising: front end sample charge amplifier (101), voltage amplification electricity
Road (102), PI controller (104), low-pass filter (106), reference voltage source (Vref), is opened correlated double sampling circuit (103)
Close one (S1), switch two (S2), switch three (S3), switch four (S4), switch five (S5) and reference capacitance (Cref)；Its feature exists
In:
One end of the switch one (S1) is grounded, termination reference voltage source (Vref) of the switch two (S2), switch
The common node of the other end of the other end and switch two (S2) of one (S1) as driving end and capacitance level transducer one
End connects, and the other end of capacitance level transducer connects with one end of reference capacitance (Cref), reference capacitance (Cref) it is another
One end connects with the common node of one end of switch three (S3) and one end of switch four (S4), the other end ground connection of switch (S3)；
One end of the public termination switch five (S5) of capacitance level transducer and reference capacitance (Cref) and front end sample charge amplify
The input terminal of device (101) connects, and switch five (S5) is reset switch, and the other end of switch five (S5) is grounded, front end sample charge
The input terminal of output termination voltage amplifier circuit (102) of amplifier (101)；The output of the voltage amplifier circuit (102)
The input terminal of correlated double sampling circuit (103) is terminated, output termination PI controller (104) of correlated double sampling circuit (103)
Input terminal；The input terminal of the low-pass filter of output termination (106) of the PI controller (104), low-pass filter (106)
Output end connects with the other end of switch four (S4)；
The correlated double sampling circuit (103) include resistance five (R5), capacitor three (C2), capacitor four (C3), switch eight (S8),
Switch nine (S9) and operational amplifier four (A4), input terminal of the one end of resistance five (R5) as correlated double sampling circuit (103),
The other end of resistance five (R5) connects with one end of capacitor three (C2), the other end of capacitor three (C2) and the one end of switch eight (S8)
And the common node of one end of switch nine (S9) connects, the public section of one end of the other end and capacitor four (C3) of switch nine (S9)
Point ground connection, the common node of the other end of the other end and capacitor four (C3) of switch eight (S8) are connected to operational amplifier four (A4)
Non-inverting input terminal, the inverting input terminal of operational amplifier four (A4) is connected as related with operational amplifier four (A4) output end
The output end of dual-sampling circuit (103).
2. a kind of interface ASIC of capacitance level transducer according to claim 1, it is characterised in that: the front end
Sample charge amplifier (101) includes switch six (S6), the switch July 1st (S7-1), switch seven or two (S7-2), capacitor one (C1), electricity
Hold two (CF) and operational amplifier one (A1), the non-inverting input terminal of operational amplifier one (A1) and one end of capacitor one (C1) and opens
The common node for closing one end of seven or two (S7-2) connects, the other end of the other end and switch seven or two (S7-2) of capacitor one (C1)
Common node ground connection, input terminal of the one end of switch six (S6) as front end sample charge amplifier (101), switch six (S6)
The other end, which connects with the common node of one end of the switch July 1st (S7-1) and one end of capacitor two (CF) and is connected to operation jointly, to be put
The inverting input terminal of big device one (A1) switchs the other end of the July 1st (S7-1), the other end and operational amplifier of capacitor two (CF)
Output end of the common node of the output end of one (A1) as front end sample charge amplifier (101).
3. a kind of interface ASIC of capacitance level transducer according to claim 1, it is characterised in that: the voltage
Amplifying circuit (102) includes resistance one (R1), resistance two (R2), resistance three (R3), resistance four (R4), operational amplifier two (A2)
With operational amplifier three (A3), input of the non-inverting input terminal of operational amplifier two (A2) as voltage amplifier circuit (102), fortune
The inverting input terminal for calculating amplifier two (A2) connects with the common node of one end of resistance one (R1) and one end of resistance two (R2),
The other end of resistance one (R1) is grounded, and the common node of one end of the other end and resistance three (R3) of resistance two (R2) is put with operation
The output end of big device two (A2) connects, and the other end of resistance three (R3) and the common node of one end of resistance four (R4) are put with operation
The inverting input terminal of big device three (A3) connects, the output end of the other end and operational amplifier three (A3) of resistance four (R4) it is public
Output end of the node as voltage amplifier circuit (102).
4. a kind of interface ASIC of capacitance level transducer according to claim 1, it is characterised in that: the PI control
Device (104) processed includes resistance six (R6), resistance seven (R7), capacitor five (C4) and operational amplifier five (A5), resistance six (R6)
Input terminal of the one end as PI controller (104), the other end of resistance six (R6) and one end of capacitor five (C4) are connected to fortune jointly
Calculate amplifier five (A5) inverting input terminal, operational amplifier five (A5) non-inverting input terminal ground connection, capacitor five (C4) it is another
End connects with one end of resistance seven (R7), the public section of the output end of the other end and operational amplifier five (A5) of resistance seven (R7)
Output end of the point as PI controller (104).
5. a kind of interface ASIC of capacitance level transducer according to claim 4, it is characterised in that: the operation
Amplifier five (A5) includes bias voltage one (1), bias voltage two (2), bias voltage three (3), PMOS tube one (Q1), PMOS tube
Two (Q2), PMOS tube three (Q3), NMOS tube four (Q4), NMOS tube five (Q5), PMOS tube six (Q6), PMOS tube seven (Q7), PMOS
Pipe eight (Q8), PMOS tube nine (Q9), PMOS tube ten (Q10), NMOS tube 11 (Q11), NMOS tube 12 (Q12), NMOS tube ten
Three (Q13), NMOS tube 14 (Q14), PMOS tube 15 (Q15), NMOS tube 16 (Q16), capacitor six (Cp1) and capacitor seven
(Cp2)；
NMOS tube four (Q4), NMOS tube five (Q5), NMOS tube 13 (Q13), NMOS tube 14 (Q14) and the NMOS tube
The common node of the source electrode of 16 (Q16) is grounded, PMOS tube one (Q1), PMOS tube six (Q6), PMOS tube nine (Q9), PMOS tube ten
(Q10) and the common node of the source electrode of PMOS tube 15 (Q15) connects VCC, the grid of PMOS tube one (Q1) and PMOS tube six (Q6)
Bias voltage one (1) is connect jointly；
The common node of the source electrode of PMOS tube two (Q2) and PMOS tube three (Q3) connects the drain electrode of PMOS tube one (Q1), PMOS tube two
(Q2) grid is the inverting input terminal of operational amplifier five (A5), and the grid of PMOS tube three (Q3) is operational amplifier five (A5)
Non-inverting input terminal, the drain electrode of PMOS tube two (Q2), the drain electrode of NMOS tube four (Q4), PMOS tube eight (Q8) grid public section
Point connects the common node of NMOS tube (Q4) and NMOS tube (Q5) grid, the drain electrode of the drain electrode and NMOS tube (Q5) of PMOS tube (Q3)
Common node connects the common node of the grid of PMOS tube (Q7), the grid of NMOS tube (Q16) and the one end capacitor seven (Cp2)；
The drain electrode of the common node PMOS tube six (Q6) of the source electrode of PMOS tube seven (Q7), PMOS tube eight (Q8), PMOS tube seven (Q7)
Drain electrode connect the common node of the source electrode of NMOS tube 11 (Q11) and the drain electrode of NMOS tube 13 (Q13), PMOS tube eight (Q8)
Drain electrode connects the common node of the source electrode of NMOS tube 12 (Q12), the drain electrode of NMOS tube 14 (Q14) and the one end capacitor six (Cp1)；
The common node of the grid of NMOS tube 13 (Q13) and NMOS tube 14 (Q14) connects bias voltage three (3), NMOS tube ten
The common node of one (Q11) and the grid of NMOS tube 12 (Q12) connects bias voltage two (2), the drain electrode of NMOS tube 11 (Q11)
The common node of PMOS tube nine (Q9) and PMOS tube ten (Q10) grid is connect with the common node of the drain electrode of PMOS tube nine (Q9),
The common node of the drain electrode of the drain electrode and NMOS tube 12 (Q12) of PMOS tube ten (Q10) connects the grid of PMOS tube 15 (Q15)；
The drain electrode of PMOS tube 15 (Q15), the drain electrode of NMOS tube 16 (Q16), capacitor six (Cp1) and capacitor seven (Cp2) it is another
Output end of the common node of one end as operational amplifier (A5).
6. a kind of interface ASIC of capacitance level transducer according to claim 1, it is characterised in that: the low pass
Filter (106) includes resistance eight (R8), resistance nine (R9), capacitor eight (C5) and operational amplifier six (A6), resistance eight (R8)
Input terminal of the one end as low-pass filter (106), the other end of resistance eight (R8), one end of resistance nine (R9) and capacitor eight
(C5) common node of one end connects with the inverting input terminal of operational amplifier six (A6), the same phase of operational amplifier six (A6)
Input end grounding, the common node of the other end of resistance nine (R9), the other end of capacitor eight (C5) and operational amplifier six (A6)
Output end as low-pass filter (106).
7. a kind of interface ASIC of capacitance level transducer according to claim 4, it is characterised in that: the operation
Amplifier five (A5) is the three-stage operational amplifier of low maladjustment voltage temperature coefficient.
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| CN201710232243.1A CN107014462B (en) | 2017-04-11 | 2017-04-11 | A kind of interface ASIC of capacitance level transducer |
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| CN108896133B (en) * | 2018-05-11 | 2019-12-17 | 广东美的厨房电器制造有限公司 | Water level measuring device and method for water box and steam stove |
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| CN101692095A (en) * | 2009-09-25 | 2010-04-07 | 哈尔滨工业大学 | Interface circuit with self-checking function for capacitor-type closed-loop accelerometer |
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| CN104349061A (en) * | 2013-08-07 | 2015-02-11 | 佳能株式会社 | Image stabilization apparatus, control method therefor, storage medium storing control program therefor, and image pickup apparatus equipped with image stabilization apparatus |
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| KR102245973B1 (en) * | 2014-02-17 | 2021-04-29 | 삼성전자주식회사 | Correlated double sampling circuit and image sensor including the same |
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| CN101692095A (en) * | 2009-09-25 | 2010-04-07 | 哈尔滨工业大学 | Interface circuit with self-checking function for capacitor-type closed-loop accelerometer |
| CN103178828A (en) * | 2013-03-16 | 2013-06-26 | 哈尔滨工业大学 | High-order sigma-delta closed-loop accelerometer interface circuit capable of self-checking harmonic distortion |
| CN104349061A (en) * | 2013-08-07 | 2015-02-11 | 佳能株式会社 | Image stabilization apparatus, control method therefor, storage medium storing control program therefor, and image pickup apparatus equipped with image stabilization apparatus |
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