CN106997779B - Memory and bit line driving circuit - Google Patents

Memory and bit line driving circuit Download PDF

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Publication number
CN106997779B
CN106997779B CN201610044389.9A CN201610044389A CN106997779B CN 106997779 B CN106997779 B CN 106997779B CN 201610044389 A CN201610044389 A CN 201610044389A CN 106997779 B CN106997779 B CN 106997779B
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bit line
voltage
pmos transistor
nmos transistor
power supply
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CN106997779A (en
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周世聪
陈永耀
倪昊
殷常伟
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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Semiconductor Manufacturing International Shanghai Corp
Semiconductor Manufacturing International Beijing Corp
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    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/24Bit-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/34Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436Arrangements for verifying correct programming or erasure
    • G11C16/3468Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing

Abstract

The invention provides a memory and a bit line driving circuit, wherein the bit line driving circuit comprises: a first NMOS transistor having a gate and a drain connected to a first power supply terminal; the grid electrode of the first PMOS transistor is connected with the first input end, the source electrode of the first PMOS transistor is connected with the source electrode of the first NMOS transistor, and the drain electrode of the first PMOS transistor is connected with a first node; a second NMOS transistor, wherein the grid electrode is connected with the first input end, the source electrode is connected with a second power supply end, and the drain electrode is connected with the first node; and the grid electrode of the second PMOS transistor is connected with a third power supply end, the drain electrode of the second PMOS transistor is connected with the bit line, and the source electrode of the second PMOS transistor is connected with the first node. When the memory is programmed, the highest voltage of the unselected bit line is the sum of the voltage of the third power supply end and the threshold voltage of the second PMOS transistor, the voltage of the unselected bit line is clamped, and the unselected bit line is prevented from forming high potential due to capacitive coupling, so that the memory unit is prevented from being operated mistakenly.

Description

Memory and bit line driving circuit
Technical Field
The present invention relates to the field of memory technologies, and in particular, to a memory and a bit line driving circuit.
Background
In the information age, information storage is one of the most important technical contents in information technology, and memories such as an Electrically Erasable Programmable Read Only Memory (EEPROM), a Flash memory (Flash), and the like are increasingly widely used.
Referring to fig. 1, the memory includes a memory array formed by memory cells 101, a plurality of bit lines BL connected to the memory cells, a plurality of word lines WL, and a plurality of control gate lines CG, and the memory cells 101 are selected and information is accessed through the bit lines BL, the word lines WL, and the control gate lines CG. To achieve information access of the memory cell 101, such as a read operation or a program operation on the memory cell, the memory needs to be switched between different levels to obtain a desired operating voltage. For example, in different operation modes of the memory, the driving circuit of the memory needs to provide different access voltages to the bit line and the word line for the target memory cell 101.
Referring to fig. 2, the driving circuit of the bit line BL IN the prior art includes four transistors, a PMOS transistor P1, an NMOS transistor N1, an NMOS transistor N2 and an NMOS transistor N3, wherein the PMOS transistor P1 and the NMOS transistor N2 are connected to a power supply terminal VPP, gates of the PMOS transistor P1 and the NMOS transistor N1 are connected to an input terminal IN0, a gate of the NMOS transistor N3 is connected to the input terminal IN1, and a drain of the PMOS transistor P3578 is connected to the bit line BL. IN the programming operation of the memory cell 101, the input terminal IN0 is at low level, the input terminal IN1 is at low level, the PMOS transistor P1 and the NMOS transistor N2 are turned on, the NMOS transistor N1 and the NMOS transistor N3 are turned off IN the selected bit line BL, and the voltage on the bit line BL is obtained by subtracting the threshold voltage of the NMOS transistor N2 from the voltage of the power supply terminal VPP. However, IN the unselected bit line BL, the input terminal IN0 is at the voltage of the power supply terminal VPP, the input terminal IN1 is at low level, the PMOS transistor P1, the NMOS transistor N2, and the NMOS transistor N3 are turned off, the NMOS transistor N1 is turned on, and the bit line BL is IN a floating state.
However, as the semiconductor manufacturing process is more advanced, the adjacent bit lines BL are spaced more and more closely, so that the capacitive coupling between the adjacent bit lines BL is also greater and more. In the programming operation, the unselected bit lines BL are in a floating state and are easily capacitively coupled with the adjacent bit lines BL to become a high potential, so that the memory cell is erroneously operated.
Disclosure of Invention
The present invention is directed to a bit line driving circuit, which solves the problem of an erroneous operation of an unselected bit line due to capacitive coupling when a programming operation is performed on a memory cell in the prior art.
To solve the above technical problem, the present invention provides a bit line driving circuit, including:
the grid electrode and the drain electrode of the first NMOS transistor are connected with a first power supply end;
the grid electrode of the first PMOS transistor is connected with a first input end, the source electrode of the first PMOS transistor is connected with the source electrode of the first NMOS transistor, and the drain electrode of the first PMOS transistor is connected with a first node;
a second NMOS transistor, wherein a gate of the second NMOS transistor is connected to the first input terminal, a source of the second NMOS transistor is connected to a second power supply terminal, and a drain of the second NMOS transistor is connected to the first node;
and the grid electrode of the second PMOS transistor is connected with a third power supply end, the drain electrode of the second PMOS transistor is connected with a bit line, and the source electrode of the second PMOS transistor is connected with the first node.
Optionally, the memory further includes a third NMOS transistor, a gate of the third NMOS transistor is connected to the second input terminal, a source of the third NMOS transistor is connected to the second power source terminal, and a drain of the third NMOS transistor is connected to the bit line.
Optionally, the source voltage of the first PMOS transistor is a difference between the voltage of the first power source terminal and the threshold voltage of the first NMOS transistor.
Optionally, when the first node is at a low level, the second PMOS transistor is turned off, and the voltage of the bit line is higher than a sum of the voltage of the third power supply terminal and the threshold voltage of the second PMOS transistor, the second PMOS transistor is turned on.
Correspondingly, the invention also provides a memory, which comprises a memory array, a plurality of bit lines connected with the memory array, a plurality of word lines, a plurality of control gate lines and the bit line driving circuit, wherein the memory cells comprise a plurality of memory cells distributed in an array, the bit lines, the word lines and the control lines are selected to operate the memory cells, and the bit lines are driven by the bit line driving circuit.
Optionally, when the memory cell is programmed, the first power supply terminal is a programming high voltage, and the third power supply terminal is a working voltage.
Optionally, the first input terminal is at a low level to select the bit line, the first NMOS transistor, the first PMOS transistor, and the second PMOS transistor are turned on, the second NMOS transistor is turned off, and a voltage of the bit line is a difference between a voltage of the first power supply terminal and a threshold voltage of the first NMOS transistor.
Optionally, the first input terminal is a programming high voltage, so as to deselect the bit line, the first NMOS transistor and the second NMOS transistor are turned on, the first PMOS transistor is turned off, and when the voltage of the bit line is higher than the sum of the voltage of the third power supply terminal and the threshold voltage of the second PMOS transistor, the second PMOS transistor is turned on.
Optionally, the bit line driving circuit further includes a third NMOS transistor, a gate of the third NMOS transistor is connected to the second input terminal, a source of the third NMOS transistor is connected to the second power source terminal, and a drain of the third NMOS transistor is connected to the bit line.
Optionally, when the memory cell is erased, the first power end is a programming high voltage, the third power end is a working voltage, the first input end is the programming high voltage, the second input end is the working voltage, the first PMOS transistor and the second PMOS transistor are turned off, the third NMOS transistor is turned on, and the bit line is a low level.
Optionally, when the memory cell is read, the first power end is a working voltage, the third power end is a working voltage, the first input end is a working voltage, the second PMOS transistor is turned off, and the voltage of the bit line is determined by other circuits.
Optionally, the second power end is a ground end.
Optionally, the programming high voltage is 15V to 17V, and the working voltage is 1V to 3V.
In the bit line driving circuit, when a memory is programmed, the first input end of an unselected bit line is a programming high voltage, the second input end of the unselected bit line is a low level, the first NMOS transistor and the second NMOS transistor are turned on, the first PMOS transistor is turned off, and when the voltage of the bit line is higher than the voltage of the third power supply end plus the threshold voltage of the second PMOS transistor, the second PMOS transistor is turned on, so that the voltage of the unselected bit line is the highest voltage of the third power supply end plus the threshold voltage of the second PMOS transistor, the voltage of the unselected bit line is clamped, and the misoperation of a memory unit on the unselected bit line is avoided.
Drawings
FIG. 1 is a diagram illustrating a memory structure in the prior art;
FIG. 2 is a circuit diagram of a prior art bit line driver circuit;
FIG. 3 is a circuit diagram of a bit line driving circuit according to an embodiment of the invention.
Detailed Description
The memory and bit line driver circuits of the present invention will now be described in greater detail with reference to the schematic drawings in which preferred embodiments of the invention are shown, it being understood that one skilled in the art could modify the invention herein described while still achieving the advantageous results of the invention. Accordingly, the following description should be construed as broadly as possible to those skilled in the art and not as limiting the invention.
The core idea of the present invention is to provide a memory and a bit line driving circuit thereof, when a programming operation is performed on the memory, in an unselected bit line, the first input terminal is a programming high voltage, the second input terminal is a low level, the first NMOS transistor and the second NMOS transistor are turned on, the first PMOS transistor is turned off, the first node is a low level, and when a voltage of the bit line is higher than a voltage of the third power supply terminal plus a threshold voltage of the second PMOS transistor, the second PMOS transistor is turned on, so that the voltage of the unselected bit line is at most equal to the voltage of the third power supply terminal plus the threshold voltage of the second PMOS transistor, the voltage of the unselected bit line is clamped, and a memory cell on the unselected bit line is prevented from being erroneously operated.
The following describes the bit line driving circuit of the present invention in detail with reference to fig. 3, and the bit line driving circuit of the present invention includes:
a first NMOS transistor Mn1, the gate and drain of the first NMOS transistor Mn1 being connected to a first power supply terminal VPP;
a first PMOS transistor Mp1, the gate of the first PMOS transistor Mp1 being connected to a first input terminal IN0, the source being connected to the source of the first NMOS transistor Mn1, the drain being connected to a first node S1, the source voltage of the first PMOS transistor Mp1 being the difference between the voltage of the first power supply terminal VPP and the threshold voltage of the first NMOS transistor Mn 1;
a second NMOS transistor Mn2, the gate of the second NMOS transistor Mn2 being connected to the first input terminal IN0, the source being connected to a second power supply terminal GND, the drain being connected to the first node S1;
a second PMOS transistor Mp2, wherein the gate of the second PMOS transistor Mp2 is connected to a third power supply terminal VDD, the drain is connected to a bit line BL, the source is connected to the first node S1, and when the first node S1 is at a low level and the second PMOS transistor Mp2 is in a low level, if the voltage of the bit line BL is higher than the sum of the voltage of the third power supply terminal VDD and the threshold voltage of the second PMOS transistor Mp2, the second PMOS transistor Mp2 is turned on to release the voltage on the bit line BL, so that the voltage on the bit line BL is at most the sum of the voltage of the third power supply terminal VDD and the threshold voltage of the second PMOS transistor Mp2, and the voltage on the bit line BL is clamped to avoid the incorrect operation of the memory cell caused by capacitive coupling of the unselected bit line BL;
IN the third NMOS transistor Mn3, a gate of the third NMOS transistor Mn3 is connected to the second input terminal IN1, a source of the third NMOS transistor is connected to the second power terminal GND, and a drain of the third NMOS transistor Mn3 is connected to the bit line BL.
Correspondingly, the present invention further provides a memory, which includes a memory array, a plurality of bit lines BL connected to the memory array, a plurality of word lines WL connected to the memory array, a plurality of control gate lines CG, and the bit line driving circuit, where the memory array includes a plurality of memory cells 101 distributed in an array, and the memory cells 101 include other structures such as a source, a drain, a floating gate, and a control gate, which can be understood by those skilled in the art and are not described herein. The memory of the invention can be EEPROM, Flash and other erasable memories. In this embodiment, bit lines BL, word lines WL, and control gate lines CG are selected by applying different potentials to the bit lines BL, the word lines WL, and the control gate lines CG, so as to perform corresponding operations on the memory cell 101. Each bit line BL is correspondingly connected with the bit line driving circuit, and the bit lines are selected or unselected through the bit line driving circuit.
When the memory cell is programmed, the first power end VPP is a programming high voltage, the second power end GND is a ground end, the third power end VDD is a working voltage, the first input end IN0 is at a low level, the second input end IN1 is at a low level IN the selected bit line BL bit line driving circuit, the first NMOS transistor Mn1, the first PMOS transistor Mp1 and the second PMOS transistor Mp2 are turned on, the second NMOS transistor Mn2 and the third NMOS transistor Mn3 are turned off IN the bit line driving circuit, and the voltage of the selected bit line BL is a difference between the voltage of the first power end VPP and the threshold voltage of the first NMOS transistor Mn 1.
However, IN the bit line driving circuit of the unselected bit line BL during the program operation of the memory cell, the first input terminal IN0 is a program high voltage, the second input terminal IN1 is a low level, the first NMOS transistor Mn1 and the second NMOS transistor Mn2 are turned on, the first PMOS transistor Mp1 is turned off, so that the first node S1 is a low level, if the voltage of the unselected bit line BL is the sum of the voltage of the third power supply terminal VDD (operating voltage) and the threshold voltage of the second PMOS transistor Mp2, the second PMOS transistor Mp2 is turned on, so that the highest voltage of the bit line BL is the sum of the voltage of the third power supply terminal VDD (operating voltage) and the threshold voltage of the second PMOS transistor Mp2, thereby clamping the voltage of the bit line BL and avoiding the coupling of the unselected bit line BL to a higher voltage due to the coupling between adjacent bit lines BL, a malfunction of the memory cell on the unselected bit line BL is avoided.
In this example. The programming high voltage is 15V-17V, and the working voltage is 1V-3V.
When the memory cells are erased, the first power supply end VPP is a programming high voltage, the second power supply end GND is a ground end, the third power supply end VDD is a working voltage, IN the bit line driving circuit of the selected and unselected bit lines BL, the first input end IN0 is a programming high voltage, the second input end IN1 is a working voltage, the first PMOS transistor Mp1 and the second PMOS transistor Mp2 are turned off, the third NMOS transistor Mn3 is turned on, and the selected and unselected bit lines BL are at a low level, so that all the memory cells are erased.
When the memory cell is read, the first power supply end VPP is a working voltage, the second power supply end GND is a ground end, the third power supply end VDD is a working voltage, IN the bit line driving circuit of the selected and unselected bit lines BL, the first input end IN0 is a working voltage, the second input end IN1 is a low level, the second PMOS transistor Mp2 and the third NMOS transistor Mn3 are turned off, and the voltages of the selected and unselected bit lines BL are determined by other circuits.
In summary, in the bit line driving circuit of the present invention, when a program operation is performed on a memory, in an unselected bit line, the first input terminal is a program high voltage, the second input terminal is a low level, the first NMOS transistor and the second NMOS transistor are turned on, the first PMOS transistor is turned off, and when the voltage of the bit line is higher than the voltage of the third power supply terminal plus the threshold voltage of the second PMOS transistor, the second PMOS transistor is turned on, so that the voltage of the unselected bit line is maximally the voltage of the third power supply terminal plus the threshold voltage of the second PMOS transistor, the voltage of the unselected bit line is clamped, and an erroneous operation of a memory cell on the unselected bit line is avoided.
It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims (12)

1. A bit line driver circuit, comprising:
the grid electrode and the drain electrode of the first NMOS transistor are connected with a first power supply end;
the grid electrode of the first PMOS transistor is connected with a first input end, the source electrode of the first PMOS transistor is connected with the source electrode of the first NMOS transistor, and the drain electrode of the first PMOS transistor is connected with a first node;
a second NMOS transistor, wherein a gate of the second NMOS transistor is connected to the first input terminal, a source of the second NMOS transistor is connected to a second power supply terminal, and a drain of the second NMOS transistor is connected to the first node;
a second PMOS transistor, wherein the grid electrode of the second PMOS transistor is connected with a third power supply end, the drain electrode of the second PMOS transistor is connected with a bit line, and the source electrode of the second PMOS transistor is connected with the first node;
and the grid electrode of the third NMOS transistor is connected with a second input end, the source electrode of the third NMOS transistor is connected with the second power supply end, and the drain electrode of the third NMOS transistor is connected with the bit line.
2. The bit line driver circuit according to claim 1, wherein a source voltage of the first PMOS transistor is a difference between a voltage of the first power supply terminal and a threshold voltage of the first NMOS transistor.
3. The bit line driver circuit according to claim 1, wherein when said first node is low, said second PMOS transistor is turned off, and a voltage of said bit line is higher than a sum of a voltage of said third power supply terminal and a threshold voltage of said second PMOS transistor, said second PMOS transistor is turned on.
4. A memory comprising a memory array, a plurality of bit lines connected to the memory array, a plurality of word lines, a plurality of control gate lines, and the bit line driver circuit as claimed in any one of claims 1-3, wherein the memory array comprises a plurality of memory cells distributed in an array, the bit lines, the word lines, and the control gate lines are selected to operate the memory cells, and the bit lines are driven by the bit line driver circuit.
5. The memory of claim 4, wherein the first power supply terminal is a programming high voltage and the third power supply terminal is an operating voltage when the memory cell is programmed.
6. The memory of claim 5, wherein the first input terminal is low to select the bit line, the first NMOS transistor, the first PMOS transistor, and the second PMOS transistor are turned on, the second NMOS transistor is turned off, and the voltage of the bit line is a difference between the voltage of the first power terminal and a threshold voltage of the first NMOS transistor.
7. The memory of claim 5, wherein the first input terminal is a programming high voltage to deselect the bit line, the first NMOS transistor, the second NMOS transistor are turned on, the first PMOS transistor is turned off, and the second PMOS transistor is turned on when the bit line has a voltage higher than a sum of a voltage of the third power supply terminal and a threshold voltage of the second PMOS transistor.
8. The memory of claim 4, wherein the bit line driver circuit further comprises a third NMOS transistor having a gate connected to the second input terminal, a source connected to the second power supply terminal, and a drain connected to the bit line.
9. The memory of claim 8, wherein the first power supply terminal is a programming high voltage, the third power supply terminal is an operating voltage, the first input terminal is a programming high voltage, the second input terminal is an operating voltage, the first PMOS transistor and the second PMOS transistor are turned off, the third NMOS transistor is turned on, and the bit lines are all low when the memory cell is erased.
10. The memory of claim 4, wherein the first power supply terminal is an operating voltage, the third power supply terminal is an operating voltage, the first input terminal is an operating voltage, the second PMOS transistor is turned off, and the bit line voltage is determined by other circuits during a read operation of the memory cell.
11. The memory according to any one of claims 5 to 10, wherein the second power terminal is a ground terminal.
12. The memory according to any one of claims 5 to 7 and 9, wherein the programming high voltage is a voltage of 15V to 17V, and the operating voltage is a voltage of 1V to 3V.
CN201610044389.9A 2016-01-22 2016-01-22 Memory and bit line driving circuit Active CN106997779B (en)

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Citations (2)

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CN103137204A (en) * 2011-11-23 2013-06-05 上海华虹Nec电子有限公司 Bit line control circuit of flash memory
CN104662611A (en) * 2012-07-31 2015-05-27 斯班逊有限公司 Bitline voltage regulation in non-volatile memory

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DE602004018687D1 (en) * 2004-02-19 2009-02-05 Spansion Llc CURRENT VOLTAGE IMPLEMENTATION CIRCUIT AND CONTROL METHOD THEREFOR
US7596035B2 (en) * 2007-06-29 2009-09-29 Micron Technology, Inc. Memory device bit line sensing system and method that compensates for bit line resistance variations
US8693260B2 (en) * 2011-04-19 2014-04-08 Macronix International Co., Ltd. Memory array with two-phase bit line precharge

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN103137204A (en) * 2011-11-23 2013-06-05 上海华虹Nec电子有限公司 Bit line control circuit of flash memory
CN104662611A (en) * 2012-07-31 2015-05-27 斯班逊有限公司 Bitline voltage regulation in non-volatile memory

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