CN106991206B

CN106991206B - Method and device for generating chip plane layout information

Info

Publication number: CN106991206B
Application number: CN201710021637.2A
Authority: CN
Inventors: 秦海阳; 李岩; 陈广缘
Original assignee: Chipone Technology Beijing Co Ltd
Current assignee: Chipone Technology Beijing Co Ltd
Priority date: 2017-01-12
Filing date: 2017-01-12
Publication date: 2020-09-11
Anticipated expiration: 2037-01-12
Also published as: CN106991206A

Abstract

A method and apparatus for generating chip floor plan information, the method comprising: generating boundary information according to a plurality of preset boundary coordinates and an arrangement sequence of the boundary coordinates in the clockwise direction; and generating power supply network pattern information according to the plurality of boundary coordinates, the arrangement sequence of the boundary coordinates in the clockwise direction and a preset characteristic parameter of the power supply network. In the design process of the chip plane layout, at least for the boundary and the power supply network, the user does not need to design and adjust manually, the design time is reduced, and the design accuracy is improved.

Description

Method and device for generating chip plane layout information

Technical Field

The present disclosure relates to the field of integrated circuit chip design, and in particular, to a method and an apparatus for automatically generating chip layout information.

Background

At present, in the field of integrated circuit chip design, the design of a plane layout (Floorplan) is basically finished manually by an engineer, and even the most basic rectangular plane layout can not leave the familiarity of the engineer.

The planar layout design is an important link in the back-end digital design, directly influences the subsequent layout and wiring results, and is a part consuming time and labor in the digital back-end design. In addition, chip design often requires multiple adjustment iterations before tape-out; chip area and structures are re-adjusted and evaluated to meet real-world design requirements and demands, and there is a constant possibility of redesigning floor plans. Engineers design the layout by experience, which is greatly influenced by human factors.

Disclosure of Invention

In view of the above, the present disclosure provides a method and an apparatus for automatically generating chip plane layout information, in which boundary information and power network pattern information are generated according to a plurality of preset boundary coordinates and preset characteristic parameters of a power network, and a user does not need to manually perform design and adjustment iteration of a plane layout, so that design time is reduced and design accuracy is improved.

According to an aspect of the present disclosure, there is provided a method of generating chip floorplan information, including:

generating boundary information according to a plurality of preset boundary coordinates and an arrangement sequence of the boundary coordinates in the clockwise direction;

and generating power supply network pattern information according to the plurality of boundary coordinates, the arrangement sequence of the boundary coordinates in the clockwise direction and a preset characteristic parameter of the power supply network.

Preferably, the power supply network includes an outer ring power supply ring and an inner ring power supply ring, the preset characteristic parameter of the power supply network includes a distance between a core and a boundary, a distance between the outer ring power supply ring and the inner ring power supply ring, a line width of the outer ring power supply ring, and a line width of the inner ring power supply ring, and the generating of the power supply network pattern information according to the plurality of boundary coordinates, an arrangement order of the boundary coordinates in an hour direction, and the preset characteristic parameter of the power supply network includes:

for three boundary coordinates S continuous in the clockwise direction among the plurality of boundary coordinates_i-1、S_iAnd S_i+1According to the boundary coordinates S_i-1、S_iAnd S_i+1Each with the start point boundary coordinates S₁The distance between the two power supply rings to determine the coordinate R of the outer ring power supply ring_iAnd the coordinates r of the inner power ring_iRelative to the boundary coordinate S_iWherein 1 ≦ i ≦ N, N is an integer greater than 4, represents the total number of boundary coordinates, i represents the sequential number of coordinates in the clockwise direction, and S represents when i ≦ 1_i-1Corresponds to S_NWhen i is N, S_i+1Corresponds to S₁；

According to the characteristic parameters of the power supply network and the coordinate R of the outer ring power supply ring_iAnd the coordinates r of the inner power ring_iRelative to the boundary coordinate S_iTo determine the coordinates R of the outer power ring_iAnd the coordinates r of the inner power ring_i；

Coordinate r of inner ring power supply ring_iConnecting according to the arrangement sequence of the hour hand direction to determine the arrangement position of the inner ring power ring, generating pattern information of the inner ring power ring according to the arrangement position of the inner ring power ring and the line width of the inner ring power ring, and connecting the coordinates R of the outer ring power ring_iAre connected according to the arrangement sequence of the hour hand directions to ensureAnd determining the placing position of the outer ring power supply ring and generating outer ring power supply ring pattern information according to the placing position of the outer ring power supply ring and the line width of the outer ring power supply ring.

Preferably, the hour hand direction includes a clockwise direction, and the boundary coordinate S_i-1、S_iAnd S_i+1Are connected in sequence to form a right angle and two sides of the right angle extend respectively in the transverse direction and the longitudinal direction, according to boundary coordinates S_i-1、S_iAnd S_i+1Each with the start point boundary coordinates S₁The distance between the two power supply rings to determine the coordinate R of the outer ring power supply ring_iAnd the coordinates r of the inner power ring_iRelative to the boundary coordinate S_iThe orientations of (a) include:

if a < b < c, judging the coordinate R of the outer ring power supply ring_iAnd the coordinates r of the inner power ring_iAt the boundary coordinate S_iIn which a represents S_i-1And S₁B represents S_iAnd S₁C represents S_i+1And S₁The distance between them;

if a is more than b and more than c, judging the coordinate R of the outer ring power supply ring_iAnd the coordinates r of the inner power ring_iAt the boundary coordinate S_iUpper left of (1);

if b is>a and b>c, or if b<a and b<c，S_i-1At S_i+1At the upper left of (1), at the boundary coordinate S₁、S_i-1、S_iAnd S_i+1Connected in this order to form a quadrilateral and wherein S_i-1、S_iAnd S_i+1When a clockwise pattern is formed, the coordinate R of the outer ring power ring is judged_iAnd the coordinates r of the inner power ring_iAt the boundary coordinate S_iThe left lower side of (1);

if b is>a and b>c, or if b<a and b<c，S_i-1At S_i+1At the lower right of (1), then at the boundary coordinate S₁、S_i-1、S_iAnd S_i+1Connected in this order to form a quadrilateral and wherein S_i-1、S_iAnd S_i+1When a counterclockwise pattern is formed, the coordinate R of the outer ring power ring is determined_iAnd the coordinates r of the inner power ring_iAt the boundary coordinate S_iThe upper right side of (1).

Preferably, the characteristic parameters of the power supply network further include information on the number of wiring layers, and the method further includes: and based on the wiring layer number information, arranging the transverse extension part of the inner ring power supply ring and the outer ring power supply ring in a first wiring layer, and arranging the longitudinal extension part of the inner ring power supply ring in a second wiring layer, wherein the first wiring layer and the second wiring layer are non-top layers.

Preferably, the inner power ring pattern information is generated before the outer power ring pattern information, and the method further comprises: deleting the longitudinally extending portion of the inner ring power supply ring disposed at the second wiring layer after generating the inner ring power supply ring pattern information.

Preferably, the method further comprises: and generating inner ring power ring pattern information and outer ring power ring pattern information in a top wiring layer according to the generated inner ring power ring pattern information and outer ring power ring pattern information, and deleting parts of the inner ring power ring extending from a starting point and an end point to the outer ring power ring in the top wiring layer.

Preferably, the characteristic parameters of the power supply network further include the number of through holes and the pitch of through holes, and the method further includes: and generating through hole pattern information according to the outer ring power supply ring pattern information, the inner ring power supply ring pattern information, the number of through holes and the through hole pitch.

Preferably, the characteristic parameters of the power supply network further include a pitch and a line width of the longitudinal power supply bar, and the method further includes:

calculating the number of longitudinal power bars according to the maximum transverse width of the boundary, the distance between the core and the boundary, the line widths of the outer ring power ring and the inner ring power ring, the distance between the outer ring power ring and the inner ring power ring, and the distance between the longitudinal power bars, wherein the maximum transverse width of the boundary is determined based on the coordinates of the boundary;

rounding the calculated number of the longitudinal power strips to obtain an optimized value of the number of the longitudinal power strips;

calculating an optimized value of the pitch of the longitudinal power bars according to the optimized value of the number of the longitudinal power bars;

determining the placement position of the longitudinal power strips according to the optimized value of the distance between the longitudinal power strips, the transverse maximum width of the boundary, the distance between the core and the boundary, the line widths of the outer ring power ring and the inner ring power ring and the distance between the outer ring power ring and the inner ring power ring; and

and determining the pattern information of the longitudinal power strips according to the placement positions of the longitudinal power strips and the line widths of the longitudinal power strips.

Preferably, the parameter information of the power supply network further includes a pitch and a line width of a horizontal power supply bar and a line height of each line in the chip plan layout, and the method further includes:

taking the central line of the row closest to the lower edge of the inner boundary of the inner ring power ring as a starting edge;

converting the spacing of the transverse power bars into an even number of rows based on the row height as an optimized value of the spacing of the transverse power bars;

calculating the number of the transverse power bars according to the optimized values of the longitudinal maximum width of the boundary, the distance between the core and the boundary, the line widths of the outer ring power ring and the inner ring power ring, the distance between the outer ring power ring and the inner ring power ring, and the distance between the transverse power bars, wherein the longitudinal maximum width of the boundary is determined based on the coordinates of the boundary;

taking the central line of the row as the placing position of the transverse power strips at an optimized value of the space of the transverse power strips at intervals from the starting edge until the placing positions of the transverse power strips with the number equal to the number of the transverse power strips are determined; and

and generating transverse power bar pattern information according to the placing positions of the transverse power bars and the line widths of the transverse power bars.

Preferably, the method further comprises: after the placement positions of the transverse power strips with the number equal to the number of the transverse power strips are determined, if the distance between the upper edge of the inner boundary of the inner ring power ring and the transverse power strip closest to the upper edge of the inner ring power ring is greater than the distance between two adjacent transverse power strips, adding one transverse power strip between the upper edge of the inner boundary of the inner ring power ring and the transverse power strip closest to the upper edge of the inner ring power ring.

Preferably, the method further comprises: the blocking area information is determined according to the inner power ring pattern information and the boundary information.

Preferably, the determining blocking area information according to the inner ring power ring pattern information and the boundary information includes:

circularly shifting the coordinates of the inner boundary of the inner ring power ring contained in the pattern information of the inner ring power ring by a numerical value in the opposite direction of the clockwise direction according to the serial number of the arrangement sequence of the clockwise direction;

respectively taking the boundary coordinates with the same number and the inner boundary coordinates of the inner ring power ring as a first diagonal coordinate and a second diagonal coordinate of the blocking area;

and generating a lower left corner coordinate and an upper right corner coordinate of the blocking area according to the first diagonal coordinate and the second diagonal coordinate of the blocking area.

Preferably, the generating the lower left corner coordinate and the upper right corner coordinate of the blocking area according to the first diagonal coordinate and the second diagonal coordinate of the blocking area comprises:

if the first diagonal coordinate is located at the lower left corner of the blocking area and the second diagonal coordinate is located at the upper right corner of the placing area, taking the first diagonal coordinate as the lower left corner coordinate of the blocking area and taking the second diagonal coordinate as the upper right corner coordinate of the blocking area;

if the first diagonal coordinate is located at the upper right corner of the blocking area and the second diagonal coordinate is located at the lower left corner of the blocking area, taking the first diagonal coordinate as the lower left corner coordinate of the blocking area and taking the second diagonal coordinate as the upper right corner coordinate of the placing area;

if the first diagonal coordinate is located at the upper left corner of the occlusion region and the second diagonal coordinate is located at the lower right corner of the occlusion region, or if the first diagonal coordinate is located at the lower right corner of the occlusion region and the second diagonal coordinate is located at the upper left corner of the occlusion region, then the lower left corner coordinate and the upper right corner coordinate of the occlusion region are calculated from the first diagonal coordinate and the second diagonal coordinate.

According to another aspect of the present disclosure, there is provided an apparatus for generating chip floorplan information, including:

the boundary generating module is used for generating boundary information according to a plurality of preset boundary coordinates and an arrangement sequence of the boundary coordinates in the clockwise direction;

and the power supply network generation module is used for generating power supply network pattern information according to the plurality of boundary coordinates, the arrangement sequence of the boundary coordinates in the clockwise direction and the preset characteristic parameters of the power supply network.

Preferably, the power supply network includes an outer ring power supply ring and an inner ring power supply ring, the preset characteristic parameter of the power supply network includes a distance between a core and a boundary, a distance between the outer ring power supply ring and the inner ring power supply ring, a line width of the outer ring power supply ring, and a line width of the inner ring power supply ring, and the power supply network generation module includes a power supply ring generation module, and the power supply ring generation module includes:

an orientation calculation unit for calculating three boundary coordinates S continuing in the clockwise direction among the plurality of boundary coordinates_i-1、S_iAnd S_i+1According to the boundary coordinates S_i-1、S_iAnd S_i+1Each with the start point boundary coordinates S₁The distance between the two power supply rings to determine the coordinate R of the outer ring power supply ring_iAnd the coordinates r of the inner power ring_iRelative to the boundary coordinate S_iWherein 1 ≦ i ≦ N, N is an integer greater than 4, represents the total number of boundary coordinates, i represents the sequential number of coordinates in the clockwise direction, and S represents when i ≦ 1_i-1Corresponds to S_NWhen i is N, S_i+1Corresponds to S₁；

A power ring coordinate calculation unit for calculating the coordinate R of the outer ring power ring according to the characteristic parameters of the power network_iAnd the coordinates r of the inner power ring_iRelative to the boundary coordinate S_iTo determine the coordinates R of the outer power ring_iAnd the coordinates r of the inner power ring_i；

A power ring pattern generation unit for generating the coordinates r of the inner ring power ring_iConnecting according to the arrangement sequence of the hour hand direction to determine the arrangement position of the inner ring power ring, generating pattern information of the inner ring power ring according to the arrangement position of the inner ring power ring and the line width of the inner ring power ring, and connecting the coordinates R of the outer ring power ring_iAnd connecting according to the arrangement sequence of the hour hand direction to determine the placing position of the outer ring power supply ring and generate outer ring power supply ring pattern information according to the placing position of the outer ring power supply ring and the line width of the outer ring power supply ring.

Preferably, the hour hand direction includes a clockwise direction, and the boundary coordinate S_i-1、S_iAnd S_i+1Sequentially connected to form a right angle and two sides of the right angle extend in the transverse and longitudinal directions, respectively, and the orientation calculation unit is configured to:

if b is>a and b>c, or if b<a and b<c，S_i-1At S_i+1At the lower right of (1), then at the boundary coordinate S₁、S_i-1、S_iAnd S_i+1Connected in this order to form a quadrilateral and wherein S_i-1、S_iAnd S_i+1When a clockwise pattern is formed, the coordinate R of the outer ring power ring is judged_iAnd the coordinates r of the inner power ring_iAt the boundary coordinate S_iThe left lower side of (1);

if b is>a and b>c, or if b<a and b<c，S_i-1At S_i+1At the upper left of (1), at the boundary coordinate S₁、S_i-1、S_iAnd S_i+1Connected in this order to form a quadrilateral and wherein S_i-1、S_iAnd S_i+1When a counterclockwise pattern is formed, the coordinate R of the outer ring power ring is determined_iAnd the coordinates r of the inner power ring_iAt the boundary coordinate S_iThe upper right side of (1).

Preferably, the characteristic parameters of the power supply network further include information of the number of wiring layers, and the power supply ring generation module further includes: and the layer setting unit is used for setting the transverse extension part of the inner ring power supply ring and the outer ring power supply ring in a first wiring layer and setting the longitudinal extension part of the inner ring power supply ring in a second wiring layer based on the wiring layer number information, wherein the first wiring layer and the second wiring layer are non-top layers.

Preferably, the inner ring power ring pattern information is generated before the outer ring power ring pattern information, and the power ring generation module further includes: a first deleting unit configured to delete the longitudinally extending portion of the inner ring power supply ring disposed at the second wiring layer after the inner ring power supply ring pattern information is generated.

Preferably, the power ring generation module further includes:

the top layer wiring unit is used for generating inner ring power ring pattern information and outer ring power ring pattern information in a top layer wiring layer according to the generated inner ring power ring pattern information and outer ring power ring pattern information; and

and a second deleting unit configured to delete a portion of the inner-turn power supply ring extending from the start point and the end point to the outer-turn power supply ring in the top wiring layer.

Preferably, the characteristic parameters of the power supply network further include the number of through holes and the pitch of through holes, and the apparatus further includes: and the through hole generation module is used for generating through hole pattern information according to the outer ring power supply ring pattern information, the inner ring power supply ring pattern information, the number of the through holes and the through hole interval.

Preferably, the characteristic parameters of the power supply network further include a pitch and a line width of a longitudinal power supply bar, the apparatus further includes a longitudinal power supply bar generating module, and the longitudinal power supply bar generating module includes:

a longitudinal power bar number calculation unit for calculating the number of longitudinal power bars from a transverse maximum width of a boundary, a distance between a core and the boundary, line widths of an outer power ring and an inner power ring, a distance between the outer power ring and the inner power ring, and a distance between the longitudinal power bars, the longitudinal maximum width of the boundary being determined based on coordinates of the boundary;

the longitudinal power strip number optimizing unit is used for rounding the calculated number of the longitudinal power strips to obtain a number optimized value of the longitudinal power strips;

the longitudinal power strip spacing optimization unit is used for calculating the spacing optimization value of the longitudinal power strips according to the number optimization value of the longitudinal power strips;

the longitudinal power strip placement position calculation unit is used for determining the placement positions of the longitudinal power strips according to the optimized value of the distance between the longitudinal power strips, the transverse maximum width of the boundary, the distance between the core and the boundary, the line widths of the outer ring power ring and the inner ring power ring and the distance between the outer ring power ring and the inner ring power ring; and

and the longitudinal power strip pattern generation unit is used for determining longitudinal power strip pattern information according to the arrangement position of the longitudinal power strips and the line width of the longitudinal power strips.

Preferably, the characteristic parameters of the power supply network further include the number and line width of the lateral power supply bars, the apparatus further includes a lateral power supply bar generation module, and the lateral power supply bar generation module includes:

a starting line determining unit for taking a central line of a row closest to a lower edge of an inner boundary of the inner ring power ring as a starting edge;

a transverse power bar pitch optimization unit for converting the pitch of the transverse power bars into an even number of rows based on the row height as an optimized value of the pitch of the transverse power bars

A horizontal power bar number calculation unit for calculating the number of horizontal power bars from optimized values of a vertical maximum width of a boundary, a distance between a core and the boundary, line widths of an outer power ring and an inner power ring, a distance between the outer power ring and the inner power ring, and a pitch of the horizontal power bars, the vertical maximum width of the boundary being determined based on coordinates of the boundary;

a horizontal power bar placement position calculation unit for taking a center line of a row as a placement position of horizontal power bars at an optimized value of a pitch of the horizontal power bars from a start edge until placement positions of horizontal power bars equal in number to the number of the horizontal power bars are determined; and

and the transverse power strip pattern generating unit is used for generating transverse power strip pattern information according to the placing position of the transverse power strips and the line width of the transverse power strips.

Preferably, the transversal power bar generating module further comprises: and the power strip supplementing unit is used for adding one transverse power strip between the upper edge of the inner boundary of the inner ring power ring and the transverse power strip closest to the inner ring power ring if the distance between the upper edge of the inner boundary of the inner ring power ring and the transverse power strip closest to the inner ring power ring is greater than the sum of the distances between two adjacent transverse power strips after the placing positions of the transverse power strips equal to the optimized number are determined.

Preferably, the apparatus further comprises: and the blocking area generating module is used for determining the placing area information according to the pattern information and the boundary information of the inner ring power ring.

Preferably, the blocking region generating module includes:

a number shifting unit for circularly shifting the coordinates of the inner boundary of the inner power ring included in the inner power ring pattern information by one value in the reverse direction of the hour direction according to the numbering of the arrangement sequence of the hour direction;

the diagonal determining unit is used for respectively taking the boundary coordinates with the same number and the inner boundary coordinates of the inner ring power ring as a first diagonal coordinate and a second diagonal coordinate of the blocking area;

and the blocking area coordinate calculation unit is used for generating a lower left corner coordinate and an upper right corner coordinate of the blocking area according to the first diagonal coordinate and the second diagonal coordinate of the blocking area.

Preferably, the blocking area coordinate calculation unit is configured to:

if the first diagonal coordinate is located at the upper right corner of the blocking area and the second diagonal coordinate is located at the lower left corner of the blocking area, taking the second diagonal coordinate as the lower left corner coordinate of the blocking area and taking the first diagonal coordinate as the upper right corner coordinate of the blocking area;

if the first diagonal coordinate is located at the upper left corner of the blocked area and the second diagonal coordinate is located at the lower right corner of the blocked area, or if the first diagonal coordinate is located at the lower right corner of the blocked area and the second diagonal coordinate is located at the upper left corner of the blocked area, the lower left corner coordinate and the upper right corner coordinate of the put area are calculated from the first diagonal coordinate and the second diagonal coordinate.

Drawings

To more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below, and it is apparent that the drawings in the following description only relate to some embodiments of the present disclosure and do not limit the present disclosure.

Fig. 1 illustrates a method of generating chip floorplan information according to an embodiment of the present disclosure.

Fig. 2a illustrates an example of the shape of a boundary and a core according to an embodiment of the present disclosure.

FIG. 2b shows an example of the coordinates and orientation of a boundary in accordance with an embodiment of the present disclosure.

Fig. 2c shows a partial schematic diagram of a power supply network according to an embodiment of the disclosure.

Fig. 3 shows a flowchart of a method of generating power ring pattern information according to an embodiment of the present disclosure.

Fig. 4a shows a schematic diagram of a layout of a power ring according to an embodiment of the present disclosure.

Fig. 4b shows a partial enlargement of fig. 4 a.

Fig. 4c shows a further enlarged detail of fig. 4 a.

Fig. 5 a-5 d illustrate example flow diagrams of a method of determining a bearing of a power ring network according to an embodiment of the present disclosure.

Fig. 6 shows a schematic diagram of a layout of an inner ring power ring pattern in accordance with an embodiment of the disclosure.

Fig. 7 shows a schematic diagram of a layout of an outer ring power ring pattern in accordance with an embodiment of the disclosure.

Fig. 8 shows a schematic diagram of a layout of a top-level power ring according to an embodiment of the present disclosure.

Fig. 9 shows a schematic enlarged view of the redundant portion of the inner-ring top power ring.

Fig. 10 shows a flowchart of a method of generating via pattern information according to an embodiment of the present disclosure.

Fig. 11 shows a schematic diagram of a layout of vias according to an embodiment of the present disclosure.

Fig. 12 shows a flowchart of a method of generating longitudinal power strip pattern information according to an embodiment of the present disclosure.

Fig. 13 shows a schematic diagram of a layout of a vertical power bar according to an embodiment of the present disclosure.

Fig. 14 shows a flowchart of a method of generating lateral power stripe pattern information according to an embodiment of the present disclosure.

Fig. 15 shows a schematic diagram of a layout of lateral power strips according to an embodiment of the present disclosure.

Fig. 16 shows a flow chart of a method 600 of generating barrier region information according to an embodiment of the present disclosure.

Fig. 17a shows a schematic diagram of coordinate point number shift in the occlusion region information generation process according to an embodiment of the present disclosure.

Fig. 17b shows schematic diagrams of layouts before and after coordinate conversion in a blocking area information generation process according to an embodiment of the present disclosure.

Fig. 18 is a schematic diagram illustrating a coordinate conversion method in a blocking area information generation process according to an embodiment of the present disclosure.

Fig. 19 shows a block diagram of an apparatus for generating chip floor plan information according to an embodiment of the present disclosure.

Fig. 20 shows a block diagram of a power network generation module according to an embodiment of the disclosure.

Fig. 21 shows a block diagram of a power supply loop generation module in the power supply network generation module.

Fig. 22 shows a block diagram of a vertical power bar generation module in a power network generation module according to an embodiment of the present disclosure.

Fig. 23 shows a block diagram of a horizontal power bar generation module in a power network generation module according to another embodiment of the present disclosure.

Fig. 24 shows a block diagram of a blocking region generation module according to an embodiment of the present disclosure.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present disclosure more clear, the technical solutions of the embodiments of the present disclosure will be described below in detail and completely with reference to the accompanying drawings of the embodiments of the present disclosure. It is to be understood that the embodiments described are only a few embodiments of the present disclosure, and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the described embodiments of the disclosure without any inventive step, are within the scope of protection of the disclosure.

The chip floor design content mainly comprises the following steps: the area shape of a boundary (boundary), a core (core), the positions of an interface (pad), a port (port) and a macro (macro), the network construction of a power ring (ring) and a power bar (strap), and the area placement of a block area (block). Because uncertain factors exist in the position placement of the pad, the port and the macro, engineers need to reasonably place the position according to experience; but there is some correlation and regularity in the design of the boundaries, power networks and blackout areas. Therefore, it is considered that the automatic design of the floor can be realized in terms of the boundary, the power supply network, the blocking area, and the like.

The invention provides a method and a device for automatically generating chip plane layout information, which are used for generating boundary and core information and power supply network pattern information according to a plurality of preset boundary (boundary) coordinates and an arrangement sequence thereof as well as preset characteristic parameters of a power supply network, so that at least for the boundary and the power supply network, a user does not need to manually design and adjust, the design time is reduced, and the design accuracy is improved.

Fig. 1 illustrates a method 100 of generating chip floorplan information in accordance with an embodiment of the disclosure.

In step S101, boundary information is generated based on a plurality of preset boundary coordinates and an arrangement order of the boundary coordinates in the clockwise direction. Fig. 2a shows an example of the shape of the boundaries of a cruciform pattern, where the outer rings represent the boundaries and the inner rings represent the cores (core). The power network is disposed within the core area. Information about the core, for example, the coordinate points and the arrangement order of the core may be generated together with the boundary information or may be calculated from the boundary information. Fig. 2b shows an example of the boundary coordinates of the cruciform pattern and its order of arrangement in the clockwise direction. As shown in fig. 2b, the same point coordinates (x1, y1) are used as the starting point position and the ending point position of the coordinates of the polygon boundary, and the boundary coordinates are (x1, y1), (x2, y2), …, (x12, y12) in the clockwise direction, and the connection directions are w1, w2, …, and w 12. These coordinates determine the position and shape of the boundary. These coordinates can be created as an array and counted for later use to infer pattern information for the power network and the blackout area.

In step S102, power supply network pattern information is generated based on the plurality of boundary coordinates, the arrangement order of the boundary coordinates in the clockwise direction, and a preset characteristic parameter of the power supply network. Fig. 2c shows a partial schematic diagram of a power supply network according to an embodiment of the disclosure. As shown in fig. 2c, the power network provided inside the border 1 may comprise one or more of the following: power rings (pg ring)2 and 3, power bars (pg strap)4 and 5 bridged on the power rings, and through holes (via)6 arranged on the power rings. The power ring may comprise an outer power ring 2 and an inner power ring 3 and the power bars may comprise longitudinal power bars 4 and transverse power bars 5. The core area of the power supply network is arranged to be divided into a plurality of rows 7, each row 7 having a row height h. The characteristic parameters of the preset power supply network may include, but are not limited to, one or more of the following: wiring layer number information, distance d between core and boundary, bit distance p between outer ring power supply ring and inner ring power supply ring, line width w of outer ring power supply ring and inner ring power supply ring, and bit distance p between longitudinal power supply bars_vLine width w of longitudinal power supply bar_vThe bit distance p between the transverse power bars_hLine width w of the lateral power bars_hAnd the height h. Because each part of the power supply network has certain relevance with the boundary coordinates and the trend thereof, the power supply network pattern information can be calculated based on the characteristic parameters of the power supply network and the boundary coordinates and the trend. When generating the power network pattern information, the power ring pattern information may be generated first, and the via hole pattern information and the power bar pattern information may be generated based thereon. The generation of the via pattern information and the generation of the power bar pattern information may be sequentially performed.

In step S103, barrier region (block) information is generated from the boundary information and the power supply network pattern information. The blocking area is used to prevent standard cells from entering under the power ring. Figures 17 and 18 illustrate the layout of the blocking area with a cross-shaped border as an example, the coordinates of which can be deduced from the border coordinates and the power ring coordinates, as will be described in more detail below.

Fig. 3 shows a flow chart of a method 200 of generating power ring pattern information. The description is made taking the clockwise direction as an example in the present embodiment. The power ring may include an outer ring power ring and an inner ring power ring.

In step S201, based on the wiring layer number information, the laterally extending portion of the inner ring power ring and the outer ring power ring are disposed in the M1 wiring layer, and the longitudinally extending portion of the inner ring power ring is disposed in the M2 wiring layer. In the present embodiment, the wiring layer number information may include the maximum wiring layer number, and preferably may have M5 or M6 as the horizontal highest wiring layer and the vertical highest wiring layer, respectively. The transverse extension and the longitudinal extension of the inner power ring are arranged in different layers, so that the longitudinal extension is deleted for convenience.

At step S202, for three boundary coordinates S continuous in the clockwise direction among the plurality of boundary coordinates_i-1、S_iAnd S_i+1According to the boundary coordinates S_i-1、S_iAnd S_i+1Each with the start point boundary coordinates S₁To determine the power ring coordinate R_iAnd r_iRelative to the boundary coordinate S_iOfBits, where 1 ≦ i ≦ N, N is an integer greater than 3, representing the total number of boundary coordinates, i represents the sequential number of coordinates in the clockwise direction, and S represents when i ≦ 1_i-1Corresponds to S_NWhen i is N, S_i+1Corresponds to S₁。

Fig. 4a shows a schematic diagram of the placement and shape of the outer and inner ring power rings in the case of a cruciform pattern boundary. As can be seen from FIG. 4a, the boundary has a plurality of coordinate points S arranged in a clockwise direction₁,S₂,…,S_NWhere N is an integer greater than 3, in this embodiment N ═ 12. The outer ring power supply ring 2 has the same shape as the boundary 1, and is located in the core region in the boundary 1, and the outer ring of the outer ring power supply ring 2 coincides with the boundary of the core region. The inner ring power supply ring 3 is the same as the outer ring power supply ring 2 in shape, is positioned in the space limited by the outer ring power supply ring 2, and is separated from the outer ring power supply ring 2 by a certain distance. Fig. 4b shows a partial enlargement of fig. 4 a. As shown in fig. 4b, each boundary coordinate point S_iMay have a corresponding outer ring power ring coordinate point R_iAnd a corresponding inner ring power ring coordinate point r_i. If R is_iAnd the connection in the clockwise direction forms the central line of the outer ring power ring, and the central line can be used as the placing position of the outer ring power ring. If r is_iConnecting in the clockwise direction, a center line of the inner power ring is formed, and the center line can be used as the placing position of the inner power ring, as shown by the dotted line in fig. 4 a. Fig. 4c shows a further enlarged detail of fig. 4 a. As shown in fig. 4c, for the starting point S₁Can be substituted by S₁The wiring starting point and the wiring end point of the corresponding inner ring power ring and the outer ring power ring are set at the middle points of the respective starting and ending edges, for example, as shown in fig. 4c, the power ring coordinates are shifted down by w/2 as the starting point, and shifted left by w/2 as the end point, so that the finally obtained pattern is complete, as shown in fig. 4 a.

For example, each boundary coordinate point S is determined_iCorresponding outer ring power supply ring coordinate point R_iAnd inner ring power ring coordinate point r_iIt is determined in which orientation the power ring coordinates are located relative to the boundary coordinate points. Most of the current general useThe boundary takes the shape of a right-angled polygon, i.e. the sides of the boundary extend only in both the transverse and longitudinal directions, which results in any succession of three boundary coordinates S_i-1、S_iAnd S_i+1Are connected in sequence to form a right angle and two sides of the right angle extend in the transverse direction and the longitudinal direction respectively. By analyzing the relationship between the starting point and the boundary coordinates, it is possible to calculate which of the upper left, lower left, upper right, and lower right the position of the power ring coordinates with respect to the boundary coordinates is.

Fig. 5a to 5d show an example flow chart of a method of determining the orientation of a power ring network.

As shown in FIG. 5a, if a < b < c, the power ring coordinate R is determined_iAnd r_iAt the boundary coordinate S_iIn which a represents S_i-1And S₁B represents S_iAnd S₁C represents S_i+1And S₁The distance between them.

As shown in FIG. 5b, if a > b > c, the power ring coordinate R is determined_iAnd r_iAt the boundary coordinate S_iUpper left of (1).

As shown in FIG. 5c, if b>a and b>c, or if b<a and b<c，S_i-1At S_i+1At the lower right of (1), then at the boundary coordinate S₁、S_i-1、S_iAnd S_i+1Connected in this order to form a quadrilateral and wherein S_i-1、S_iAnd S_i+1When a clockwise pattern is formed, the power ring coordinate R is determined_iAnd r_iAt the boundary coordinate S_iThe lower left.

As shown in FIG. 5d, if b>a and b>c, or if b<a and b<c，S_i-1At S_i+1At the upper left of (1), at the boundary coordinate S₁、S_i-1、S_iAnd S_i+1Connected in this order to form a quadrilateral and wherein S_i-1、S_iAnd S_i+1When a counterclockwise pattern is formed, the power ring coordinate R is determined_iAnd r_iAt the boundary coordinate S_iThe upper right side of (1).

In step S203, according toCharacteristic parameters of a power supply network and power supply ring coordinates R_iAnd r_iRelative to the boundary coordinate S_iTo determine the coordinates r of the inner power ring_i. For example for the case shown in the right diagram of fig. 5d, with reference to fig. 4a and 4b, if S_iHas the coordinates of (xi, yi), then r_iThe coordinate of (a) is any one of (xi + d + w + p, yi + d + w + p), (xi + d + w + p, yi-d-w-p), (xi-d-w-p, yi + d + w + p) and (xi-d-w-p, yi-d-w-p). For a starting point S with coordinates (x1, y1)₁Can be substituted by S₁The start coordinate of the corresponding inner power ring is set to (x1+ d + w/2+ p, y1+ d + p) and the end coordinate is set to (x1+ d + p, y1+ d + w/2+ p) in order to complete the power ring pattern.

In step S204, the coordinates ri of the inner ring power rings are connected according to the arrangement sequence in the clockwise direction to determine the placement position of the inner ring power rings, and the pattern information of the inner ring power rings is generated according to the placement position of the inner ring power rings and the line width of the inner ring power rings. The inner power ring pattern information may include outer boundary coordinates, inner boundary coordinates, and centerline coordinates (i.e., coordinate r) of the inner power ring_i). The inner power ring pattern generated by this step is shown in the left part of fig. 6.

In step S205, the portion of the inner power ring disposed at the M2 level is deleted. In some embodiments, because the ground rail (GND rail) of the M1 layer is connected to the outer ground power ring of the M1 layer, the M1 layer does not require a longitudinally extending portion of the inner power ring, which can be disposed in the M2 layer and subsequently deleted. The longitudinally extending portions can be simply deleted by deleting the M2 metal layer at this step without affecting the design of the M1 layer. When the M2 layer is deleted, the through holes on the M2 layer can be deleted together. The pattern of the inner power ring after the removal of the M2 layer is shown in the right hand portion of fig. 6.

In step S206, according to the characteristic parameters of the power network and the power ring coordinate R_iRelative to the boundary coordinate S_iTo determine the coordinates R of the outer power ring_i. For example for the situation shown in FIG. 5c, referring to FIG. 4b, if S is_iHas coordinates of (xi, yi), then R_iMay be (x)i + d + w/2, yi + d + w/2), (xi-d-w/2, yi + d + w/2), (xi + d + w/2, yi-d-w/2), and (xi-d-w/2, yi-d-w/2). For a starting point S with coordinates (x1, y1)₁Can be substituted by S₁The start coordinates of the corresponding outer power ring are set to (x1+ d + w/2, y1+ d) and the end coordinates are set to (x1+ d, y1+ d +2/w) to complete the power ring pattern.

In step S207, the coordinates Ri of the outer ring power rings are connected according to the arrangement sequence in the hour hand direction to determine the placement position of the outer ring power rings, and the outer ring power ring pattern information is generated according to the placement position of the outer ring power rings and the line width of the outer ring power rings. Fig. 7 shows a schematic diagram of a layout of an outer ring power ring according to an embodiment of the disclosure. The outer-ring power ring pattern information is generated from the outer-ring power ring placement position and the outer-ring power ring line width (as shown in the right part of fig. 7) by connecting the respective coordinate points Ri in the order from 1 to 12 from the start point of the outer-ring power ring to determine the outer-ring power ring placement position (shown in the left part of fig. 7). The outer ring power ring pattern information may include an outer coordinate, an inner coordinate, and a centerline coordinate (i.e., coordinate R) of the outer ring power ring_i)。

In step S208, inner ring power ring pattern information and outer ring power ring pattern information are generated in the top wiring layer according to the generated inner ring power ring pattern information and outer ring power ring pattern information. The design of the inner ring power ring and the outer ring power ring of the top layer can be performed in parallel. Specifically, the outer ring power ring can be placed according to the coordinates of the outer ring power ring, and the inner ring power ring can be designed in parallel according to the placement of the outer ring power ring and the distance between the inner ring power ring and the outer ring power ring. However, in the case of such parallel design of the inner ring power supply ring and the outer ring power supply ring, the start point coordinates and the end point coordinates of the script commands are shown in the left part of fig. 8, which causes an excessive wire length to exist in the inner ring power supply ring near the start point and the end point after the design of the inner ring power supply ring and the outer ring power supply ring is completed, as shown in the dotted line part in the right part of fig. 8.

In step S209, the inner ring power ring is extended from the start point and the end point to the outer ring power ring at the top wiring layerThe ring is partially deleted. In some embodiments, FIG. 9 shows a schematic enlarged view of the excess portion of the inner power ring encircled by the dashed line in FIG. 8. In the embodiment shown in fig. 9, it is assumed that the boundary start point S₁The coordinates are (0,0), and then the coordinates of point a are (d + p ), the coordinates of point B are (d + w + p, d), and the coordinates of point C are (d, d + w + p). As shown in fig. 9, the rectangular area portion with coordinates a and B as diagonal lines is an unnecessary portion extending from the start point of the inner ring power ring to the outer ring power ring (as shown by the right-oblique line hatching in fig. 9), and the rectangular area portion with coordinates B and C as diagonal lines is an unnecessary portion extending from the end point of the inner ring power ring to the outer ring power ring (as shown by the left-oblique line hatching in fig. 9), and these two portions are respectively located in different layers, for example, the former is located in the longitudinally highest layer, and the latter is located in the laterally highest layer. At the time of deletion, deletion may be performed in a different layer.

Although the inner-turn power ring pattern information is generated before the outer-turn power ring pattern information in the above-described embodiments, embodiments of the present disclosure are not limited thereto. The outer ring power ring can be generated first and then the inner ring power ring can be generated, and the two power rings can also be generated simultaneously.

In addition to the embodiments of the present disclosure

After the power ring pattern information is generated, via pattern information, power bar pattern information, barrier region information, and the like may be generated therefrom, which is described below with reference to fig. 10 to 19.

Fig. 10 shows a flow chart of a method 300 of generating via pattern information according to an embodiment of the present disclosure. Fig. 11 shows a schematic diagram of a layout of vias according to an embodiment of the present disclosure.

In step S301, the coordinates of the area for arranging the through holes on the power supply ring are calculated from the coordinates of the power supply ring and the width of the power supply ring. For example, as shown in the right side of fig. 11, the coordinates Ri of the outer-ring power supply ring obtained by the above method may be taken as the center coordinates of the region for arranging the through-hole on the outer-ring power supply ring, and the coordinates of the four corners of the through-hole region may be calculated with the width of the outer-ring power supply ring as the lateral and longitudinal lengths of the through-hole region. Similarly, the coordinate r of the inner power ring can be determined_iAs inner ring power ringAnd calculating coordinates of four corners of the via region with a width of the inner coil power supply ring as a lateral and longitudinal length of the via region. One or more vias, preferably an array of vias, may be arranged within each via area.

In step S302, the placement positions of the through holes are calculated according to the preset number of the through holes and the preset distance between the through holes. For example, the number of transverse through holes and the number of longitudinal through holes can be calculated according to the length and the width of the through hole area and the preset transverse and longitudinal through hole intervals, and the arrangement positions of the through holes are set on the through hole area according to the intervals.

In step S303, via pattern information is determined according to the placement positions of the vias. The square patterns can be directly formed on the placing positions, the shapes and the sizes of the through holes can be preset, and through hole pattern information is formed by combining the shapes and the sizes of the through holes.

In step S304, via pattern information is generated in a different wiring layer. As shown in the left part of fig. 11, a via array may be provided in each of the wiring layers from the second-to-bottom layers corresponding to the via region within a preset maximum number of wiring layers.

A generation method of longitudinal power stripe pattern information according to an embodiment of the present disclosure is described below with reference to fig. 12 and 13.

Fig. 12 shows a flow chart of a method 400 of generating longitudinal power bar pattern information according to an embodiment of the present disclosure. Fig. 13 shows a schematic diagram of a layout of a longitudinal power strip according to an embodiment of the present disclosure, with the inner and outer power rings shown in dotted lines for clarity of illustration.

In step S401, the number of longitudinal power bars is calculated according to the maximum width in the lateral direction of the boundary, the distance between the core and the boundary, the line widths of the outer power ring and the inner power ring, the bit distance between the outer power ring and the inner power ring, and the bit distance between the longitudinal power bars. In fig. 13, rectangular boundaries are adopted for convenience of description, and the origin of coordinates (0,0) is taken as the coordinates of the lower left corner of the boundary, and (x,0) is taken as the coordinates of the lower right corner of the boundary, so that the maximum lateral width of the boundary can be determined to be x. In the present embodiment, two longitudinal power bars respectively connected across the outer ring power ring and the inner ring power ring and adjacent to each other are taken as a group, which is n groups in total, the group interval is inc, and the distance between two power bars in each group is inc/2, as shown in fig. 13. The number of groups of vertical power bars may be denoted by n, and the group pitch of the vertical power bars may be denoted by inc. As already described above with reference to fig. 2c, the distance between the boundary and the outer power ring is d, the bit distance between the inner and outer power rings is p, and the power ring width is w. In this case, the placement position of the leftmost vertical power bar as the starting point is (d + w + p + inc/2), the placement position of the rightmost vertical power bar as the end point is x- (d + w + p + inc/2), and the distance therebetween is x- (d + w + p + inc/2) × 2. From this the following equation can be deduced:

n＝[x-(d+w+p+inc/2)*2]/inc+0.5

in step S402, the calculated number of vertical power bars is rounded to obtain an optimized value of the number of vertical power bars. For example, the optimized value n' for the number of vertical power bars may be calculated from n ═ int (n +0.5), where int () represents a rounding. Since the value n calculated in the previous step S401 is not usually an integer, a rounding operation, for example, rounding, is performed in the present step to obtain an integer value n' close to the value of n as a parameter for subsequent calculation.

In step S403, an optimized value of the pitch of the vertical power bars is calculated from the optimized value of the number of the vertical power bars. For example, an optimized value inc ' of the pitch of the longitudinal power bars may be calculated from inc ═ x- (d + w + p + inc/2) × 2]/(n ' -0.5), thereby obtaining a power bar pitch suitable for the number n '.

In step S404, the placement positions of the longitudinal power bars are determined according to the optimized value of the pitch of the longitudinal power bars, the transverse maximum width of the boundary, the distance between the core and the boundary, the line widths of the outer ring power ring and the inner ring power ring, and the distance between the outer ring power ring and the inner ring power ring. For example, a set of longitudinal power bars may be placed every interval inc' starting from the left starting position. Through the steps, the distance between the longitudinal power strip with the leftmost side as the starting point and the left side of the inner boundary of the inner ring power ring is equal to the distance between two adjacent longitudinal power strips, and the distance between the longitudinal power strip with the right side as the end point and the right side of the inner boundary of the inner ring power ring is equal to the distance between the longitudinal power strip with the leftmost side as the starting point and the left side of the inner boundary of the inner ring power ring.

In step S405, longitudinal power bar pattern information is determined according to the placement position of the longitudinal power bars and the line width of the longitudinal power bars. The length of the longitudinal power strips may be determined according to the longitudinal width of the power ring in which the longitudinal power strips are located.

Although the derivation and calculation are performed by taking two power bars as a group, the embodiment of the disclosure is not limited to this, and the derivation and calculation may also be performed by a single power bar, for example, inc/2 may be used as the distance between two adjacent longitudinal power bars to perform the parameter presetting, and then 2n is correspondingly used as the number of power bars to perform the placement by using the interval inc/2 during the placement, which is not described herein again.

A method of generating lateral power stripe pattern information according to an embodiment of the present disclosure is described below with reference to fig. 14 and 15.

Fig. 14 shows a flow chart of a method 500 of generating lateral power bar pattern information according to an embodiment of the present disclosure. Fig. 15 shows a schematic diagram of a layout of a lateral power bar according to an embodiment of the present disclosure, with the inner and outer ring power rings shown in dotted lines for clarity of illustration.

In step S501, the center line of the row closest to the lower edge of the inner boundary of the inner ring power ring is set as the starting edge. Preferably, the height of the lower edge of the inner boundary of the inner power ring can be compared with the height of the upper edge of the row closest thereto. The lower edge of the core is taken as an initial line, and the height of the lower edge of the inner boundary of the inner ring power supply ring is w + p. The w + p is converted to the sum of the rows, resulting in a number of rows int ((w + p)/h +0.5) and a sum of the rows (int ((w + p)/h + 0.5)). times.h. Then, the heights of the two are compared, if the height (w + p) of the lower edge of the inner boundary is greater than the height (namely, the sum of the heights of the rows (int ((w + p)/h + 0.5)). h), the central line of the row above the lower edge of the inner boundary is taken as a calculation edge, the starting position is s ═ (int ((w + p)/h + 0.5)). h +0.5 ═ h, otherwise, the central line of the row below is taken as a calculation edge, and the starting position is s ═ int ((w + p)/h + 0.5)). h-0.5 ×.h. In the embodiment shown in fig. 15, the height of the lower edge of the inner ring inner boundary is less than the height of the upper edge of the row closest thereto, thus taking the center line of the row below the lower edge of the inner boundary as the starting edge. By calculating the placement position of the transverse power strips with the starting edge as a starting point, the distance D between the transverse power strips is equal to the distance D' from the lowest transverse power strip to the starting edge, and is further closest to the distance from the lowest transverse power strip to the upper edge of the power ring below the inner ring. For example, for the lowermost set of lateral power bars, the distance from the VDD power bar to the VSS power bar may be made closest to the distance from the VDD power bar to the upper edge of the lower inner power ring.

In step S502, the pitch of the lateral power bars is converted into a number of rows based on the row height. The number of rows u, also referred to as the group pitch, that are separated between two adjacent groups of lateral power bars can be calculated, for example, from u — int (inc/h), where h denotes the row height. Through this step, can convert predetermined horizontal power strip interval into the line number to follow-up locating position according to the line number interval comes to confirm horizontal power strip.

In step S503, the number of rows is optimized to an even value as an optimized value of the pitch of the lateral power bars. This is because, in the case of a group pitch of u, the pitch between two adjacent power bars in each group is u/2, and if the group pitch is the sum of odd rows, one lateral power bar in a group will not be placed at the centerline position of the row. In view of this, if the value of u calculated from u ═ int (inc/h) is odd, it needs to be converted into an even number, and if the inter-group spacing of a given lateral power bar is smaller than u × h, the converted even number is u-1, and the optimized value inc ═ u-1 × h of the inter-group spacing of the lateral power bars is obtained; if the inter-group spacing of a given lateral power bar is greater than u x h, the even number converted is u +1, resulting in an optimized value of lateral power bar group spacing inc ═ u +1 x h.

In step S504, the number of lateral power bars is calculated from the optimized values of the longitudinal maximum width of the boundary, the distance between the core and the boundary, the line widths of the outer and inner power rings, the distance between the outer and inner power rings, and the pitch of the lateral power bars, the longitudinal maximum width of the boundary being determined based on the coordinates of the boundary. For example, two adjacent lateral power bars connected across different power rings may be grouped in a similar manner to the longitudinal power bars. The optimized value of the group spacing inc'. The total number of lines nt of lines in the whole core is int ((y-2 x d)/h), wherein y represents the maximum width of the boundary in the longitudinal direction, d represents the distance between the core and the boundary, and h represents the line height. The total height of the core is nt h. From this, the number of groups n of transverse power bars, int ((nt × h- (s + inc '/2) × 2)/inc' +0.5), can be derived, where s represents the height of the starting line relative to the lower edge of the kernel. The number of lateral power bars 2n can thus be obtained.

In step S505, the central line of the row is used as the placement position of the lateral power bars at the optimized value of the interval of the lateral power bars from the start edge until the placement positions of 2n lateral power bars are determined. The number of the transverse power bar groups is arranged from the lower side to the upper side, and for example, one transverse power bar may be arranged at a pitch of inc'/2. The central lines of the rows are used as placing positions at certain intervals, so that on one hand, the power strips are evenly placed, and on the other hand, the power strips and a power network can be prevented from being short-circuited or blocking through holes from leading to the power strips from a power rail.

In step S506, it is determined whether the distance between the upper edge of the inner boundary of the inner ring power ring and the nearest transverse power bar is greater than inc'/2, i.e., whether the height difference between the upper edge of the inner boundary and the uppermost transverse power bar is greater than u/2, if so, it means that there is a space in which an individual transverse power bar can be placed, and step S508 is executed, otherwise, step S509 is executed. The height of the last transverse power strip is s + (n-0.5) inc', and the height of the upper edge of the inner boundary is y-w-p-d. The power strips are arranged according to the number of groups, after the last group of power strips are arranged, the height difference between the last power strip and the upper edge of the inner boundary is 0-inc ', the distance between two adjacent power strips is inc '/2, and if the height difference between the last power strip and the upper edge of the inner boundary is more than inc '/2, another power strip can be independently inserted.

In step S507, a lateral power bar is added between the upper edge of the inner boundary of the inner ring power ring and the lateral power bar closest thereto. For example, the center line of the row above the nearest lateral power bar from the upper edge at s + (n-0.5) × inc '+ 0.5 × inc' may be taken as the placement position of the increased lateral power bars. By this step, as many uniform placements of the transverse power bars as possible can be achieved at a distance as close as possible to the preset spacing.

In step S508, horizontal power bar pattern information is generated according to the placement positions of the horizontal power bars and the line widths of the horizontal power bars.

Similar to the placement of the longitudinal power bars, the determination of the placement positions of the transverse power bars is not limited to the above embodiment of grouping, and the calculation may be performed according to the distance and number of the single power bars, which is not described herein again.

Fig. 16 shows a flow chart of a method 600 of generating barrier region information according to an embodiment of the present disclosure. Fig. 17a shows a schematic diagram of coordinate point number shift in the occlusion region information generation process according to an embodiment of the present disclosure, and fig. 17b shows a schematic diagram of a layout after coordinate conversion in the occlusion region information generation process according to an embodiment of the present disclosure, in which the inner ring power supply ring and the outer ring power supply ring are shown in dotted lines for clarity of illustration. Fig. 18 is a schematic diagram illustrating a coordinate conversion method in a blocking area information generation process according to an embodiment of the present disclosure.

In step S601, the inner boundary coordinates of the inner power ring included in the inner power ring pattern information are numbered according to the arrangement order of the hour direction and cyclically shifted by a value in the opposite direction of the hour direction. Fig. 17a shows an example of coordinate shifting in the case of clockwise numbering. As shown by the solid arrows in fig. 17a, in the case of numbering clockwise, the numbers of the respective coordinate points may be shifted in the counterclockwise order, i.e., the number of the coordinate point numbered 1 is changed to 12, the number of the coordinate point numbered 2 is changed to 1, the number of the coordinate point numbered 3 is changed to 2, and so on until the number of the coordinate point numbered 12 is changed to 11. Of course, embodiments of the present disclosure are not limited thereto, and in the case of numbering in the counterclockwise direction, the numbers of the respective coordinate points may be shifted in the clockwise direction, that is, the number of each coordinate point is increased by 1. Through this step, the boundary coordinates with the same number and the inner boundary coordinates of the inner power ring constitute diagonal coordinates of the blocking area, and the diagonal coordinates are connected as indicated by the dotted arrows in fig. 17 a.

In step S602, the boundary coordinates of the same number and the inner boundary coordinates of the inner power ring are respectively used as the first diagonal coordinates and the second diagonal coordinates of the blocking region.

In step S603, the lower left corner coordinate and the upper right corner coordinate of the occlusion region are generated according to the first diagonal coordinate and the second diagonal coordinate of the occlusion region. Although diagonal coordinates of the barrier region are determined after reordering by the numbering of step 701, as shown in the left part of fig. 18, in general, the barrier region information is composed of lower left and upper right coordinates, as shown in the right part of fig. 18, and thus it is necessary to convert the previously calculated diagonal coordinates into lower left and upper right coordinates.

The coordinate conversion method is described below with reference to fig. 18.

As shown in fig. 18a, if the first diagonal coordinate is located at the lower left corner of the occlusion region and the second diagonal coordinate is located at the upper right corner of the occlusion region, the first diagonal coordinate may be directly used as the lower left corner coordinate of the occlusion region and the second diagonal coordinate may be used as the upper right corner coordinate of the occlusion region.

If the first diagonal coordinate is located in the upper right corner of the occlusion region and the second diagonal coordinate is located in the lower left corner of the occlusion region, as shown in figure 18b, the two may be reversed, with the second diagonal coordinate being the lower left corner coordinate of the occlusion region and the first diagonal coordinate being the upper right corner coordinate of the occlusion region.

As shown in fig. 18c, if the first diagonal coordinate is located at the upper left corner of the barrier region and the second diagonal coordinate is located at the lower right corner of the barrier region, then the lower left and upper right corner coordinates may be calculated from the upper left and lower right corner coordinates, e.g., if the upper left corner coordinate is (x1, y2) and the lower right corner coordinate is (x2, y1), then coordinate points (x1, y1) and (x2, y2) may be obtained as the lower left and upper right corner coordinates, respectively.

If the first diagonal coordinate is located in the lower right corner of the occlusion region and the second diagonal coordinate is located in the upper left corner of the occlusion region, as shown in FIG. 18d, the lower left corner coordinate and the upper right corner coordinate may be derived in a manner similar to that described in FIG. 18 c.

The method described in the embodiment of the present disclosure may be implemented in the form of a script, and the flowplan information automatically generated by executing the method may be provided in the form of three files, for example, tdf files, respectively. The first file contains information of boundary, core, row (row) and track (track), and also can contain position information of manually placed Pad, Macro and port (terminal), the second file contains power network information, and the third file contains information of blocking area.

Fig. 19 shows a block diagram of an apparatus 700 for generating chip floor plan information according to an embodiment of the present disclosure.

As shown in fig. 19, the apparatus 700 includes a boundary generating module 701 and a power network generating module 702. Optionally, the apparatus 700 may further comprise a barrier region generation module 703. The boundary generating module 701 is configured to generate boundary information according to a plurality of preset boundary coordinates and an arrangement order of the boundary coordinates in a clockwise direction. The power network generating module 702 is configured to generate power network pattern information according to the boundary coordinates, an arrangement order of the boundary coordinates in the clockwise direction, and a preset characteristic parameter of the power network. The blocking area generating module 703 is configured to determine the placement area information according to the inner ring power ring pattern information and the boundary information.

Fig. 20 shows a block diagram of the power network generation module 702 according to an embodiment of the disclosure.

As shown in fig. 20, the power network generation module 702 includes a power ring generation module 7021, and includes at least one of a via generation module 7022, a vertical power bar generation module 7023, and a horizontal power bar generation module 7024. The power ring generation module 7021 is configured to generate inner ring power ring information and outer ring power ring information according to the boundary information. The through hole generating module 7022 is configured to generate through hole pattern information according to the outer ring power ring pattern information, the inner ring power ring pattern information, and preset through hole characteristic parameters. The longitudinal power strip generation module 7023 is configured to generate longitudinal power strip information according to the boundary information, the inner ring power ring information, the outer ring power ring information, and preset characteristic parameters of the longitudinal power strip. The transverse power bar generating module 7023 is configured to generate transverse power bar information according to the boundary information, the inner ring power ring information, the outer ring power ring information, and preset characteristic parameters of the transverse power bar.

Fig. 21 shows a structural diagram of the power supply loop generation module 7021 in the power supply network generation module 702.

As shown in fig. 21, the power ring generation module 7021 includes a layer setting unit 7021-1, an orientation calculation unit 7021-2, a power ring coordinate calculation unit 7021-3, a power ring pattern generation unit 7021-4, a first deletion unit 7021-5, a top layer wiring unit 7021-6, and a second deletion unit 7021-7.

The layer setting unit 7021-1 is configured to set the laterally extending portion of the inner-ring power ring and the outer-ring power ring in a first wiring layer (e.g., M1 layer) and the longitudinally extending portion of the inner-ring power ring in a second wiring layer (e.g., M2 layer) based on preset wiring layer number information.

The orientation calculating unit 7021-2 is configured to calculate, for three boundary coordinates S that are continuous in the clockwise direction among the plurality of boundary coordinates_i-1、S_iAnd S_i+1According to the boundary coordinates S_i-1、S_iAnd S_i+1Each with the start point boundary coordinates S₁To determine the power ring coordinate R_iAnd r_iOrientation relative to boundary coordinates Si, where 1 ≦ i ≦ N, N is an integer greater than 3, represents the total number of boundary coordinates, i represents the sequential number of coordinates in the clockwise direction, and S represents when i ≦ 1_i-1Corresponds to S_NWhen i is N, S_i+1Corresponds to S₁. The orientation calculation unit 7021-1 may perform the calculation in the manner described with reference to fig. 5a to 5d, for example.

The power ring coordinate calculation unit 7021-3 is used for calculating the power ring according to the characteristic parameters of the power network and the power ringCoordinate R_iAnd r_iRelative to the boundary coordinate S_iTo determine the coordinates R of the outer power ring_iAnd the coordinates r of the inner power ring_i。

The power ring pattern generating unit 7021-4 is configured to use the coordinates R of the outer ring power ring_iConnecting according to the arrangement sequence of the hour hand direction to determine the placement position of the outer ring power ring, generating outer ring power ring pattern information according to the placement position of the outer ring power ring and the line width of the outer ring power ring, and connecting the coordinates r of the inner ring power ring_iAnd connecting according to the arrangement sequence of the hour hand direction to determine the placing position of the inner ring power ring and generate the pattern information of the inner ring power ring according to the placing position of the inner ring power ring and the line width of the inner ring power ring. Specifically, the power ring pattern generating unit 7021-4 may arrange the laterally extending portion of the inner ring power ring and the outer ring power ring in the M1 wiring layer and the longitudinally extending portion of the inner ring power ring in the M2 wiring layer according to the arrangement of the layer setting unit 7021-1.

First deleting unit 7021-5 is configured to delete the longitudinally extending portion of the inner power ring disposed at the second wiring layer (e.g., M2 layer) after generating the inner power ring pattern information.

And the top layer wiring unit 7021-6 is configured to generate inner ring power ring pattern information and outer ring power ring pattern information in a top layer wiring layer according to the generated inner ring power ring pattern information and outer ring power ring pattern information.

A second deleting unit 7021-7 is configured to delete a portion of the inner-turn power supply ring extending from the start point and the end point to the outer-turn power supply ring in the top wiring layer.

In the embodiment of the present disclosure, the layer setting unit 7021-1, the first deletion unit 7021-5, and the second deletion unit 7021-7 may be optional units, and may be correspondingly excluded in the case where it is not necessary to delete the longitudinal portion of the inner-ring power ring and/or the redundant portion of the top-layer inner-ring power ring of M1.

Fig. 22 shows a block diagram of the vertical power bar generation module 7023 in the power network generation module 702 according to an embodiment of the present disclosure.

As shown in fig. 22, the vertical power bar generation module 7023 includes a vertical power bar number calculation unit 7023-1, a vertical power bar number optimization unit 7023-2, a vertical power bar interval optimization unit 7023-3, a vertical power bar arrangement position calculation unit 7023-4, and a vertical power bar pattern generation unit 7023-5.

The longitudinal power bar number calculation unit 7023-1 is configured to calculate the longitudinal power bar number from n ═ x- (d + w + p + inc/2) × 2]/inc +0.5, where n denotes the number of longitudinal power bars, x denotes the lateral maximum width of the boundary, which is determined from the coordinates of the boundary, d denotes the distance between the core and the boundary, w denotes the line width of the outer power ring and the inner power ring, p denotes the bit distance between the outer power ring and the inner power ring, and inc denotes the bit distance between adjacent longitudinal power bars on the outer power ring and the pitch between adjacent longitudinal power bars on the inner power ring.

The vertical power bar number optimizing unit 7023-2 is configured to calculate an optimized value n' of the number of vertical power bars from n ═ int (n +0.5), where int () represents rounding.

The longitudinal power bar pitch optimization unit 7023-3 is configured to calculate an optimized value inc 'of the pitch of the longitudinal power bars from inc ═ x- (d + w + p + inc/2) × 2 ]/(n' -0.5).

The longitudinal power bar placement position calculation unit 7023-4 is configured to determine the placement positions of the longitudinal power bars according to the optimized value inc' of the distance between the longitudinal power bars, the maximum transverse width of the boundary, the distance between the core and the boundary, the line widths of the outer ring power ring and the inner ring power ring, and the distance between the outer ring power ring and the inner ring power ring.

The longitudinal power bar pattern generating unit 7023-5 is configured to determine longitudinal power bar pattern information according to a placement position of the longitudinal power bars and a line width of the longitudinal power bars.

Fig. 23 shows a block diagram of the horizontal power bar generation module 7024 in the power network generation module 702 according to another embodiment of the present disclosure.

As shown in fig. 23, the lateral power bar generation module 7024 includes: a starting calculation line determining unit 7024-1, a transverse power bar interval optimizing unit 7024-2, a transverse power bar number calculating unit 7024-3, a transverse power bar placement position calculating unit 7024-4, a transverse power bar supplementing unit 7024-5 and a transverse power bar pattern generating unit 7024-6.

Starting line determining unit 7024-1 is configured to take the central line of the row closest to the lower edge of the inner boundary of the inner ring power supply ring as a starting edge. If the row height of the nearest row is greater than the height of the lower edge of the inner boundary, the centerline height s of the nearest row is (int ((w + p)/h + 0.5)). h + 0.5. h, and if the row height of the nearest row is less than the height of the lower edge of the inner boundary, the centerline height s of the nearest row is (int ((w + p)/h + 0.5)). h-0.5. h.

The lateral power bar pitch optimizing unit 7024-2 converts the pitch of the lateral power bars into an even number of rows as an optimized value of the pitch of the lateral power bars based on the row height. Specifically, the number of rows u spaced between the lateral power bars may be calculated from u — int (inc/h), where h represents the row height. It is necessary to ensure that the number u of rows is even. If the inter-group spacing of a given transverse power bar is less than u h, the converted even number is u-1, and an optimized value inc ═ (u-1) h of the transverse power bar group spacing is obtained; if the inter-group spacing of a given lateral power bar is greater than u x h, the even number converted is u +1, resulting in an optimized value of lateral power bar group spacing inc ═ u +1 x h.

The number of transverse power bars calculation unit 7024-3 calculates the number of transverse power bars according to the optimized values of the longitudinal maximum width of the boundary, the distance between the core and the boundary, the line widths of the outer power ring and the inner power ring, the distance between the outer power ring and the inner power ring, and the distance between the transverse power bars. Specifically, since the arrangement of the number of the horizontal power bar groups is performed from the lower side to the upper side in sequence, the number of the horizontal power bars can be calculated after s and inc' are determined by the front starting line determining unit 7024-1 and the horizontal power bar interval optimizing unit 7024-2. First, the total row number nt of rows inside the entire core is calculated to be int ((y-2 × d)/h), the total row height of the core is nt × h, and the group number n of lateral power bars is calculated to be int ((nt × h- (s + inc '/2) × 2)/inc' + 0.5). This results in a number of lateral power bars of 2 n.

The transverse power bar arrangement position calculation unit 7024-4 is configured to use the center line of the row as the arrangement position of the transverse power bars at intervals of inc'/2 from the start edge until 2 × n transverse power bars, that is, the arrangement positions of n groups of transverse power bars are determined.

The power bar complementing unit 7024-5 is configured to, after the placement positions of 2 × n transverse power bars are all determined, add one transverse power bar if the distance between the upper edge of the inner boundary of the inner power ring and the closest transverse power bar is greater than inc '/2, and take the center line of the row above the closest transverse power bar at the distance inc'/2 as the placement position of the added transverse power bar.

The transverse power bar pattern generating unit 7024-6 is configured to generate transverse power bar pattern information according to the placement positions of the transverse power bars and the line widths of the transverse power bars.

Fig. 24 shows a block diagram of the blocking region generation module 703 according to an embodiment of the present disclosure.

As shown in fig. 24, the blocking region generation module includes: a number shift unit 7031, a diagonal determination unit 7032, and a blocking area coordinate calculation unit 7033.

The number shifting unit 7031 is configured to cyclically shift the coordinates of the inner boundary of the inner power ring included in the inner power ring pattern information by one value in the order of arrangement in the clockwise direction and in the direction opposite to the clockwise direction. For example, the number shift unit 7031 may perform a reordering of the numbers in the manner described with reference to fig. 17 a.

The diagonal determination unit 7032 is configured to use the boundary coordinates of the same number and the inner boundary coordinates of the inner power ring as a first diagonal coordinate and a second diagonal coordinate of the blocking area, respectively.

The blocking area coordinate calculation unit 7033 is configured to generate a lower left corner coordinate and an upper right corner coordinate of the blocking area according to the first diagonal coordinate and the second diagonal coordinate of the blocking area. For example, the occlusion region coordinate calculation unit 7033 may generate the lower left corner coordinate and the upper right corner coordinate of the occlusion region in the manner described with reference to fig. 17b and fig. 18.

According to the embodiment of the disclosure, boundary information, power network pattern information and blocking area information are generated according to preset boundary coordinates and trends thereof in combination with power network parameters, in some embodiments, even the blocking area information can be correspondingly generated, and the automatic design of the floor is realized. The user does not need to manually draw and place, and only needs to input boundary coordinates, power network parameters and the like, so that the required floor design information can be obtained. When a user needs to modify the design, the modified floor design information can be quickly obtained only by modifying the design parameters. This greatly reduces the design time of the Floorplan while also increasing the rationality and standardization of the Floorplan design. The method is beneficial to releasing back-end designers from the design of the floor plan, and can more quickly match and advance the project progress.

The embodiment of the disclosure adopts an optimization method for calculating the average value of the feedback to calculate the arrangement position of the longitudinal power bars, so that the power network is uniformly and reasonably distributed.

The central line of the row is used as the placing position of the transverse power strip, so that the transverse power strip can not be arranged above rails (rails) on two sides of the row, and the situation that the power supply through holes cannot be opened and are short-circuited due to the fact that the power strip is placed above the rails manually and carelessly is avoided. Therefore, the power strips are orderly and attractive in arrangement and have rationality.

According to the embodiment of the disclosure, the longitudinal extension part and the rest part of the inner ring power ring are arranged in different layers, so that the unnecessary longitudinal extension part can be conveniently deleted subsequently, and a concise and clean design pattern can be obtained. In addition, the embodiment of the disclosure also calculates the coordinates of the redundant part of the inner ring power ring in the top layer wiring and deletes the redundant part, so that the design of the top layer wiring is simple and clean.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.

Claims

1. A method of generating chip floorplan information, comprising:

generating power supply network pattern information according to the plurality of boundary coordinates, the arrangement sequence of the boundary coordinates in the clockwise direction and a preset characteristic parameter of the power supply network,

wherein the power supply network includes an outer ring power supply ring and an inner ring power supply ring, the preset characteristic parameters of the power supply network include a distance between a core and a boundary, a distance between the outer ring power supply ring and the inner ring power supply ring, a line width of the outer ring power supply ring, and a line width of the inner ring power supply ring, and the generating of the power supply network pattern information according to the plurality of boundary coordinates, an arrangement order of the boundary coordinates in an hour direction, and the preset characteristic parameters of the power supply network includes:

for three boundary coordinates S continuous in the clockwise direction among the plurality of boundary coordinates_i-1、S_iAnd S_i+1According to the boundary coordinates S_i-1、S_iAnd S_i+1Each with the start point boundary coordinates S₁The distance between the two power supply rings to determine the coordinate R of the outer ring power supply ring_iAnd the coordinates r of the inner power ring_iRelative to the boundary coordinate S_iWherein 1 ≦ i ≦ N, N is an integer greater than 4, represents the total number of boundary coordinates, i represents the sequential number of coordinates in the clockwise direction, and S when i =1_i-1Corresponds to S_NWhen i = N, S_i+1Corresponds to S₁；

Coordinate r of inner ring power supply ring_iThe inner rings are connected according to the arrangement sequence of the hour hand direction to determine the arrangement position of the inner ring power ring and generate the inner ring according to the arrangement position of the inner ring power ring and the line width of the inner ring power ringPower ring pattern information, and coordinates R of outer ring power ring_iAnd connecting according to the arrangement sequence of the hour hand direction to determine the placing position of the outer ring power supply ring and generate outer ring power supply ring pattern information according to the placing position of the outer ring power supply ring and the line width of the outer ring power supply ring.

2. The method of claim 1, wherein the hour hand direction comprises a clockwise direction, a boundary coordinate S_i-1、S_iAnd S_i+1Are connected in sequence to form a right angle and two sides of the right angle extend respectively in the transverse direction and the longitudinal direction, according to boundary coordinates S_i-1、S_iAnd S_i+1Each with the start point boundary coordinates S₁The distance between the two power supply rings to determine the coordinate R of the outer ring power supply ring_iAnd the coordinates r of the inner power ring_iRelative to the boundary coordinate S_iThe orientations of (a) include:

if a < b < c, judging the coordinate R of the outer ring power supply ring_iAnd the coordinates r of the inner power ring_iAt the boundary coordinate S_iIn which a represents S_i-₁And S₁B represents S_iAnd S₁C represents S_i+1And S₁The distance between them;

3. The method of claim 1, wherein the characteristic parameters of the power supply network further include wiring layer number information, the method further comprising: and based on the wiring layer number information, arranging the transverse extension part of the inner ring power supply ring and the outer ring power supply ring in a first wiring layer, and arranging the longitudinal extension part of the inner ring power supply ring in a second wiring layer, wherein the first wiring layer and the second wiring layer are non-top layers.

4. The method of claim 3, wherein the inner power ring pattern information is generated before the outer power ring pattern information, and further comprising: deleting the longitudinally extending portion of the inner ring power supply ring disposed at the second wiring layer after generating the inner ring power supply ring pattern information.

5. The method of claim 3, further comprising: and generating inner ring power ring pattern information and outer ring power ring pattern information in a top wiring layer according to the generated inner ring power ring pattern information and outer ring power ring pattern information, and deleting parts of the inner ring power ring extending from a starting point and an end point to the outer ring power ring in the top wiring layer.

6. The method of claim 1, wherein the characteristic parameters of the power supply network further include a via number and a via pitch, the method further comprising: and generating through hole pattern information according to the outer ring power supply ring pattern information, the inner ring power supply ring pattern information, the number of through holes and the through hole pitch.

7. The method of claim 1, wherein the characteristic parameters of the power network further include pitch and linewidth of vertical power bars, the method further comprising:

8. The method of claim 1, wherein the characteristic parameters of the power supply network further include a pitch and a line width of the lateral power supply bars and a row height of each row in the chip floor plan, the method further comprising:

9. The method of claim 8, further comprising: after the placement positions of the transverse power strips with the number equal to the number of the transverse power strips are determined, if the distance between the upper edge of the inner boundary of the inner ring power ring and the transverse power strip closest to the upper edge of the inner ring power ring is greater than the distance between two adjacent transverse power strips, adding one transverse power strip between the upper edge of the inner boundary of the inner ring power ring and the transverse power strip closest to the upper edge of the inner ring power ring.

10. The method of claim 1, further comprising: the blocking area information is determined according to the inner power ring pattern information and the boundary information.

11. The method of claim 10, wherein the determining blocking area information from inner power ring pattern information and boundary information comprises:

12. The method of claim 11, wherein the generating lower left and upper right coordinates of a barrier region from the first and second diagonal coordinates of a barrier region comprises:

13. An apparatus for generating chip floorplan information, comprising:

a power network generating module for generating power network pattern information according to the plurality of boundary coordinates, the arrangement sequence of the boundary coordinates in the clockwise direction and the preset characteristic parameters of the power network,

wherein, the power supply network includes outer lane power ring and inner circle power ring, the characteristic parameter of default power supply network includes the distance between core and the boundary, the distance between outer lane power ring and the inner circle power ring, the line width of outer lane power ring and the line width of inner circle power ring, and power supply network generates the module and includes power ring and generates the module, power ring generates the module and includes:

an orientation calculation unit for calculating the orientation of the object,for three boundary coordinates S continuous in the clockwise direction among the plurality of boundary coordinates_i-1、S_iAnd S_i+1According to the boundary coordinates S_i-1、S_iAnd S_i+1Each with the start point boundary coordinates S₁The distance between the two power supply rings to determine the coordinate R of the outer ring power supply ring_iAnd the coordinates r of the inner power ring_iRelative to the boundary coordinate S_iWherein 1 ≦ i ≦ N, N is an integer greater than 4, represents the total number of boundary coordinates, i represents the sequential number of coordinates in the clockwise direction, and S when i =1_i-1Corresponds to S_NWhen i = N, S_i+1Corresponds to S₁；

14. The device of claim 13, wherein the hour hand direction comprises a clockwise direction, a boundary coordinate S_i-1、S_iAnd S_i+1Sequentially connected to form a right angle and two sides of the right angle extend in the transverse and longitudinal directions, respectively, and the orientation calculation unit is configured to:

15. The apparatus of claim 13, wherein the characteristic parameters of the power supply network further include a number of wiring layers information, the power ring generation module further comprising: and the layer setting unit is used for setting the transverse extension part of the inner ring power supply ring and the outer ring power supply ring in a first wiring layer and setting the longitudinal extension part of the inner ring power supply ring in a second wiring layer based on the wiring layer number information, wherein the first wiring layer and the second wiring layer are non-top layers.

16. The apparatus of claim 15, wherein the inner power ring pattern information is generated before the outer power ring pattern information, and the power ring generation module further comprises: a first deleting unit configured to delete the longitudinally extending portion of the inner ring power supply ring disposed at the second wiring layer after the inner ring power supply ring pattern information is generated.

17. The apparatus of claim 15, the power ring generation module further comprising:

18. The apparatus of claim 13, wherein the characteristic parameters of the power supply network further include a via number and a via pitch, the apparatus further comprising: and the through hole generation module is used for generating through hole pattern information according to the outer ring power supply ring pattern information, the inner ring power supply ring pattern information, the number of the through holes and the through hole interval.

19. The apparatus of claim 14, wherein the characteristic parameters of the power network further include a pitch and a linewidth of a vertical power bar, the apparatus further comprising a vertical power bar generation module comprising:

20. The apparatus of claim 13, wherein the characteristic parameters of the power supply network further include a pitch and a line width of a lateral power bar and a row height of each row in the chip floor plan, the apparatus further comprising a lateral power bar generation module, the lateral power bar generation module comprising:

a calculation starting line determining unit for taking a central line of a row closest to a lower edge of an inner boundary of the inner ring power ring as a calculation starting edge;

a horizontal power bar pitch optimization unit for converting the pitch of the horizontal power bars into an even number of rows as an optimized value of the pitch of the horizontal power bars based on the row height;

21. The apparatus of claim 20, wherein the lateral power bar generation module further comprises: and the power strip supplementing unit is used for adding one transverse power strip between the upper edge of the inner boundary of the inner ring power ring and the transverse power strip closest to the inner ring power ring if the distance between the upper edge of the inner boundary of the inner ring power ring and the transverse power strip closest to the inner ring power ring is greater than the sum of the distances between two adjacent transverse power strips after the placing positions of the transverse power strips equal to the optimized number are determined.

22. The apparatus of claim 13, further comprising: and the blocking area generating module is used for determining the placing area information according to the pattern information and the boundary information of the inner ring power ring.

23. The apparatus of claim 22, wherein the blocking region generation module comprises:

24. The apparatus of claim 23, wherein the occlusion region coordinate calculation unit is to: