CN106972022A - A kind of semiconductor devices and preparation method thereof, electronic installation - Google Patents
A kind of semiconductor devices and preparation method thereof, electronic installation Download PDFInfo
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- CN106972022A CN106972022A CN201610014814.XA CN201610014814A CN106972022A CN 106972022 A CN106972022 A CN 106972022A CN 201610014814 A CN201610014814 A CN 201610014814A CN 106972022 A CN106972022 A CN 106972022A
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- capping layer
- layer
- floating boom
- semiconductor devices
- polysilicon capping
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 67
- 238000002360 preparation method Methods 0.000 title claims abstract description 17
- 238000009434 installation Methods 0.000 title claims abstract description 11
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 74
- 229920005591 polysilicon Polymers 0.000 claims abstract description 74
- 238000007667 floating Methods 0.000 claims abstract description 42
- 239000000758 substrate Substances 0.000 claims abstract description 25
- KRHYYFGTRYWZRS-UHFFFAOYSA-M Fluoride anion Chemical compound [F-] KRHYYFGTRYWZRS-UHFFFAOYSA-M 0.000 claims abstract description 19
- 239000007787 solid Substances 0.000 claims description 6
- 239000011469 building brick Substances 0.000 claims description 5
- 239000011435 rock Substances 0.000 claims description 5
- DDFHBQSCUXNBSA-UHFFFAOYSA-N 5-(5-carboxythiophen-2-yl)thiophene-2-carboxylic acid Chemical compound S1C(C(=O)O)=CC=C1C1=CC=C(C(O)=O)S1 DDFHBQSCUXNBSA-UHFFFAOYSA-N 0.000 claims description 4
- 238000004140 cleaning Methods 0.000 claims description 4
- 238000010438 heat treatment Methods 0.000 claims description 3
- 230000009466 transformation Effects 0.000 claims description 3
- 238000003682 fluorination reaction Methods 0.000 claims 1
- 150000002222 fluorine compounds Chemical class 0.000 claims 1
- 238000000034 method Methods 0.000 abstract description 36
- 238000003860 storage Methods 0.000 abstract description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 14
- 239000012212 insulator Substances 0.000 description 10
- 230000003647 oxidation Effects 0.000 description 10
- 238000007254 oxidation reaction Methods 0.000 description 10
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 description 9
- 239000000463 material Substances 0.000 description 8
- 230000008569 process Effects 0.000 description 8
- 229910052710 silicon Inorganic materials 0.000 description 8
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 7
- 238000002955 isolation Methods 0.000 description 7
- 239000010703 silicon Substances 0.000 description 7
- 239000000377 silicon dioxide Substances 0.000 description 7
- 238000005516 engineering process Methods 0.000 description 6
- 238000000137 annealing Methods 0.000 description 5
- 238000005530 etching Methods 0.000 description 5
- 229910052732 germanium Inorganic materials 0.000 description 5
- 230000008859 change Effects 0.000 description 4
- 239000004020 conductor Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 4
- 239000007789 gas Substances 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000006396 nitration reaction Methods 0.000 description 4
- -1 SiGe Inorganic materials 0.000 description 3
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 3
- 238000001312 dry etching Methods 0.000 description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 3
- 230000014759 maintenance of location Effects 0.000 description 3
- 229910000069 nitrogen hydride Inorganic materials 0.000 description 3
- 239000001301 oxygen Substances 0.000 description 3
- 229910052760 oxygen Inorganic materials 0.000 description 3
- 230000005641 tunneling Effects 0.000 description 3
- 229910019975 (NH4)2SiF6 Inorganic materials 0.000 description 2
- XPDWGBQVDMORPB-UHFFFAOYSA-N Fluoroform Chemical compound FC(F)F XPDWGBQVDMORPB-UHFFFAOYSA-N 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 229910000673 Indium arsenide Inorganic materials 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 2
- 229910003811 SiGeC Inorganic materials 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 2
- 150000001875 compounds Chemical class 0.000 description 2
- 239000000470 constituent Substances 0.000 description 2
- 238000010276 construction Methods 0.000 description 2
- 239000003989 dielectric material Substances 0.000 description 2
- 239000007772 electrode material Substances 0.000 description 2
- 238000011065 in-situ storage Methods 0.000 description 2
- RPQDHPTXJYYUPQ-UHFFFAOYSA-N indium arsenide Chemical compound [In]#[As] RPQDHPTXJYYUPQ-UHFFFAOYSA-N 0.000 description 2
- 229910052751 metal Inorganic materials 0.000 description 2
- 239000002184 metal Substances 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910003465 moissanite Inorganic materials 0.000 description 2
- 238000001020 plasma etching Methods 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 2
- 238000003856 thermoforming Methods 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910003978 SiClx Inorganic materials 0.000 description 1
- 229910004014 SiF4 Inorganic materials 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 229910021529 ammonia Inorganic materials 0.000 description 1
- 238000005915 ammonolysis reaction Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229910052681 coesite Inorganic materials 0.000 description 1
- 229910052906 cristobalite Inorganic materials 0.000 description 1
- 238000006392 deoxygenation reaction Methods 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- ZHPNWZCWUUJAJC-UHFFFAOYSA-N fluorosilicon Chemical compound [Si]F ZHPNWZCWUUJAJC-UHFFFAOYSA-N 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 230000004927 fusion Effects 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000013067 intermediate product Substances 0.000 description 1
- 238000010884 ion-beam technique Methods 0.000 description 1
- QSHDDOUJBYECFT-UHFFFAOYSA-N mercury Chemical compound [Hg] QSHDDOUJBYECFT-UHFFFAOYSA-N 0.000 description 1
- 229910052753 mercury Inorganic materials 0.000 description 1
- PQIOSYKVBBWRRI-UHFFFAOYSA-N methylphosphonyl difluoride Chemical group CP(F)(F)=O PQIOSYKVBBWRRI-UHFFFAOYSA-N 0.000 description 1
- 238000003801 milling Methods 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- VIKNJXKGJWUCNN-XGXHKTLJSA-N norethisterone Chemical compound O=C1CC[C@@H]2[C@H]3CC[C@](C)([C@](CC4)(O)C#C)[C@@H]4[C@@H]3CCC2=C1 VIKNJXKGJWUCNN-XGXHKTLJSA-N 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000047 product Substances 0.000 description 1
- 150000004760 silicates Chemical class 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- ABTOQLMXBSRXSM-UHFFFAOYSA-N silicon tetrafluoride Chemical compound F[Si](F)(F)F ABTOQLMXBSRXSM-UHFFFAOYSA-N 0.000 description 1
- 229910052682 stishovite Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052905 tridymite Inorganic materials 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
- H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42336—Gate electrodes for transistors with a floating gate with one gate at least partly formed in a trench
Abstract
The present invention provides a kind of preparation method of semiconductor devices, semiconductor devices and electronic installation, and the preparation method includes：Semiconductor substrate is provided, tunnel dielectric layer, floating boom and gate dielectric are formed with the semiconductor substrate；Polysilicon capping layer is formed on the gate dielectric；Groove is formed in the polysilicon capping layer and the gate dielectric；The surface for the floating boom that surface and the channel bottom to the polysilicon capping layer are exposed is handled, so that the oxide on the surface for the floating boom that the polysilicon capping layer and the channel bottom expose is changed into fluoride；Remove the fluoride on the surface of the floating boom of the polysilicon capping layer and the channel bottom；Form the control gate for covering the polysilicon capping layer and the groove.This method can avoid forming boundary layer between polysilicon capping layer and control, prevent the high-pressure area of fast storage device and cause erase status to fail due to boundary layer.The semiconductor devices and electronic installation have higher stability.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of semiconductor devices and its
Preparation method, electronic installation.
Background technology
With the development of manufacture of semiconductor technology, access speed has been developed in terms of storage device
Faster flash memory (flash memory).Flash memory, which has, can repeatedly enter row information
Deposit, read and the action such as erasing, and the spy that will not also disappear after a loss of power of information of deposit
Property, therefore, flash memory turns into PC and the widely used one kind of electronic equipment
Nonvolatile memory.And NAND (NAND gate) fast storages with big storage due to holding
Amount and relatively high performance, are widely used in the field that read/write requires higher.Recently, NAND
The capacity of flash memory chip has reached 2GB, and size increases sharply.Develop
Go out the solid state hard disc based on NAND quick-flash memory chip, and be used as in pocket computer
Storage device.Therefore, in recent years, NAND fast storages are widely used as in embedded system
Storage device, also serve as the storage device in personal computer system.
In general, NAND quick-flash memory include memory cell areas (cell), high-pressure area,
Area of low pressure, and for high-pressure area, polycrystalline is formed between gate dielectric and control gate
Silicon cap rock, using as during subsequent etching gate dielectric, but is due to polysilicon capping layer and control
Boundary layer is easily formed between grid processed, as shown in Fig. 1 100, such as silica, this is right
Erase status failure is easily caused for the high-pressure area of NAND fast storages.
Therefore, it is necessary to a kind of new preparation method be proposed, to solve the above problems.
The content of the invention
A series of concept of reduced forms is introduced in Summary, this will be specific real
Apply in mode part and be further described.The Summary of the present invention is not meant to
Attempt to limit the key feature and essential features of technical scheme claimed, less
Mean the protection domain for attempting to determine technical scheme claimed.
In view of the shortcomings of the prior art, the present invention proposes a kind of manufacture method of semiconductor devices,
It can avoid forming boundary layer between polysilicon capping layer and control, prevent fast storage device
High-pressure area cause erase status to fail due to boundary layer.
In order to overcome the problem of presently, there are, one aspect of the present invention provides a kind of semiconductor devices
Preparation method, this method comprises the steps：S1：Semiconductor substrate is provided, partly led described
Tunnel dielectric layer, floating boom and gate dielectric are formed with body substrate；S2：It is situated between in the grid
Polysilicon capping layer is formed in electric layer；S3：In the polysilicon capping layer and the gate dielectric
Form groove；S4：The floating boom that surface and the channel bottom to the polysilicon capping layer are exposed
Surface handled so that floating boom that the polysilicon capping layer and the channel bottom expose
The oxide on surface is changed into fluoride；S5：Remove the polysilicon capping layer and the trench bottom
The fluoride on the surface of the floating boom in portion；S6：Formed and cover the polysilicon capping layer and the ditch
The control gate of groove.
Further, in the step S4, using ammonium fluoride to the polysilicon capping layer and
The floating boom surface that the channel bottom exposes is handled, so that the polysilicon capping layer and described
The oxide on the surface of channel bottom floating boom is changed into fluoride.
Further in the step S5, the fluoride is removed by performing heat treatment,
So that the fluoride is gaseous state by Solid State Transformation and is pumped.
Further, the step S4 and S5 is completed by performing SiCoNi cleanings.
Further, prerinse step is also included before the step S4, it is described to remove
The residue on the surface for the floating boom that the surface of polysilicon capping layer and the channel bottom expose.
The manufacture method of the semiconductor devices of the present invention can be avoided in polysilicon capping layer and control
Between form boundary layer, prevent the high-pressure area of fast storage device is caused due to boundary layer
Erase status fails.
Another aspect of the present invention provides the semiconductor devices that a kind of use above method makes, should be partly
Conductor device includes：Semiconductor substrate, is sequentially formed with tunnelling Jie on the semiconductor substrate
Electric layer, floating boom, gate dielectric, polysilicon capping layer and control gate, and positioned at the grid
Groove in dielectric layer, the control gate covers the polysilicon capping layer and the groove.
Interface is not present in semiconductor devices proposed by the present invention between polysilicon capping layer and control
Layer, thus prevent the high-pressure area of fast storage device from causing erase status due to boundary layer
The problem of failure.
Further aspect of the present invention provides a kind of electronic installation, it include a kind of semiconductor devices and
The electronic building brick being connected with the semiconductor devices.
Electronic installation proposed by the present invention, due to above-mentioned semiconductor device, thus with class
As advantage.
Brief description of the drawings
The drawings below of the present invention is used to understand the present invention in this as the part of the present invention.It is attached
Embodiments of the invention and its description are shown in figure, for explaining the principle of the present invention.
In accompanying drawing：
Fig. 1 shows the existing device of the Presence of an interface layer between polysilicon capping layer and control gate
's；
Fig. 2A~Fig. 2 G show the making of semiconductor devices according to an embodiment of the present invention
Method implements the diagrammatic cross-section that each step obtains semiconductor devices successively；
Fig. 3 shows the preparation method of semiconductor devices according to an embodiment of the present invention
Flow chart of steps；
Fig. 4 shows the structural representation of semiconductor devices according to an embodiment of the present invention.
Embodiment
In the following description, a large amount of concrete details are given to provide to the present invention more
Thoroughly understand.It is, however, obvious to a person skilled in the art that of the invention
It can be carried out without one or more of these details.In other examples, in order to keep away
Exempt to obscure with the present invention, be not described for some technical characteristics well known in the art.
It should be appreciated that the present invention can be implemented in different forms, and it is not construed as office
It is limited to embodiments presented herein.On the contrary, providing these embodiments disclosure will be made thoroughly and complete
Entirely, and it will fully convey the scope of the invention to those skilled in the art.In the accompanying drawings,
For clarity, the size and relative size in Ceng He areas may be exaggerated identical accompanying drawing from beginning to end
Mark represents identical element.
It should be understood that be referred to as when element or layer " ... on ", " with ... it is adjacent ", " being connected to "
Or when " being coupled to " other elements or layer, its can directly on other elements or layer, with
It is adjacent, be connected or coupled to other elements or layer, or there may be element or layer between two parties.
On the contrary, when element is referred to as " on directly existing ... ", " with ... direct neighbor ", " being directly connected to "
Or when " being directly coupled to " other elements or layer, then in the absence of element or layer between two parties.Should
Understand, although can be used term first, second, third, etc. describe various elements, part,
Area, floor and/or part, these elements, part, area, floor and/or part should not be by these
Term is limited.These terms be used merely to distinguish element, part, area, floor or part with
Another element, part, area, floor or part.Therefore, do not depart from present invention teach that under,
First element discussed below, part, area, floor or part be represented by the second element, part,
Area, floor or part.
Spatial relationship term for example " ... under ", " ... below ", " below ", " ... it
Under ", " ... on ", " above " etc., can describe for convenience herein and by using from
And an element shown in figure or feature and other elements or the relation of feature are described.Should be bright
In vain, in addition to the orientation shown in figure, spatial relationship term be intended to also including the use of and operation
In device different orientation.If for example, the device upset in accompanying drawing, then, is described as
" below other elements " or " under it " or " under it " element or feature will be orientated
For other elements or feature " on ".Therefore, exemplary term " ... below " and " ...
Under " it may include upper and lower two orientations.Device, which can be additionally orientated, (to be rotated by 90 ° or other
Orientation) and spatial description language as used herein correspondingly explained.
The purpose of term as used herein is only that description specific embodiment and not as this hair
Bright limitation.Herein in use, " one " of singulative, " one " and " described/should "
It is also intended to include plural form, unless context is expressly noted that other mode.It is also to be understood that art
Language " composition " and/or " comprising ", when in this specification in use, determine the feature,
Integer, step, operation, the presence of element and/or part, but be not excluded for it is one or more its
Its feature, integer, step, operation, element, the presence or addition of part and/or group.
Herein in use, term "and/or" includes any and all combination of related Listed Items.
In order to solve foregoing problems, i.e. prevent in the high-pressure area of NAND device,
Boundary layer is formed between polysilicon capping layer and control gate, and causes erase status to fail, the present invention
A kind of preparation method of semiconductor devices is provided, this method comprises the steps：S1：There is provided half
Conductor substrate, is formed with tunnel dielectric layer, floating boom and gate dielectric on the semiconductor substrate
Layer；S2：Polysilicon capping layer is formed on the gate dielectric；S3：In the polysilicon lid
Groove is formed in layer and the gate dielectric；S4：Surface and institute to the polysilicon capping layer
The surface for stating the floating boom that channel bottom exposes is handled, so that the polysilicon capping layer and described
The oxide on the surface for the floating boom that channel bottom exposes is changed into fluoride；S5：Remove described many
The fluoride on the surface of the floating boom of crystal silicon cap rock and the channel bottom；S6：Form covering described
The preparation method of the semiconductor devices of the control gate present invention of polysilicon capping layer and the groove,
After polysilicon capping layer is formed, surface and the channel bottom to the polysilicon capping layer are floated
The surface of grid is handled, and makes the surface of the floating boom of the polysilicon capping layer and the channel bottom
Oxide be changed into fluoride, and the fluoride is then removed, so due to polysilicon capping layer
Surface and the oxide on surface of the channel bottom floating boom be removed, thus be subsequently formed
After the control gate of the polysilicon capping layer and the groove, polysilicon capping layer and control gate it
Between be not in the boundary layer of such as oxide layer so that avoid due to boundary layer exist it is caused all
The problem of failing such as erase status.
In order to thoroughly understand the present invention, detailed structure and step will be proposed in following description
Suddenly, to explain technical scheme proposed by the present invention.Presently preferred embodiments of the present invention is described in detail
It is as follows, but in addition to these detailed descriptions, the present invention can also have other embodiment.
Embodiment one
Below with reference to semiconductors of Fig. 2A~Fig. 2 G and Fig. 3 to an embodiment of the present invention
The preparation method of device is described in detail.
First, step 301 is performed：Semiconductor substrate 201 is provided, in the Semiconductor substrate
Upper 201 are formed with tunnel dielectric layer 202, floating boom 203 and gate dielectric 204, are formed
Structure as shown in Figure 2 A.
Wherein, Semiconductor substrate 201 can be at least one of following material being previously mentioned：
Si, Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V chemical combination
Thing semiconductor, in addition to the sandwich construction etc. that constitutes of these semiconductors or be silicon-on-insulator
(SOI), be laminated on insulator silicon (SSOI), stacking SiGe (S-SiGeOI) on insulator,
Germanium on insulator SiClx (SiGeOI) and germanium on insulator (GeOI) etc..Semiconductor is served as a contrast
Device is could be formed with bottom, such as NMOS and/or PMOS.Equally, semiconductor is served as a contrast
Can also be formed with conductive member in bottom, conductive member can be the grid of transistor, source electrode or
Drain electrode or the metal interconnection structure that is electrically connected with transistor, etc..In addition, half
Isolation structure can also be formed with conductor substrate, the isolation structure is isolated for shallow trench
(STI) structure or selective oxidation silicon (LOCOS) isolation structure are as an example, in this reality
Apply in example, the constituent material of Semiconductor substrate 201 selects monocrystalline, its thickness is
1000~2000nm.
Tunnel dielectric layer 202 is used as insulating barrier, such as grid oxic horizon, tunnel dielectric layer
202 can use various suitable materials, exemplarily, in the present embodiment, tunneling dielectric
Layer 202 uses silica, and its thickness isTunnel dielectric layer 202 can be by this
The technique such as field conventional PVD, CVD, ALD and thermoforming process is formed, exemplary,
In the present embodiment, the tunnel dielectric layer 202 is used as by thermal oxidation method formation silica.
The material of floating boom 203 uses such as polysilicon, its by PVD commonly used in the art,
CVD, ALD are formed.Exemplarily, floating boom is formed by CVD method in the present embodiment
203, its thickness is
Gate dielectric 204 can select various suitable dielectric materials, exemplary in this implementation
In example, in order to improve the interface performance between each layer, and with high dielectric constant, grid is situated between
Electric layer 204 uses ONO structure, i.e. oxide layer/nitration case/oxidation Rotating fields, wherein first
Layer oxide layer is to be located at the oxide layer on floating boom 203, can be formed by thermal oxidation method, oxygen
Nitration case on first layer oxide layer, such as silicon nitride, can by such as PVD, CVD,
The techniques such as ALD are formed, and second of oxide layer can pass through such as PVD, CVD, ALD
And thermal oxidation technology is formed, these techniques are technique commonly used in the art, will not be had herein to it
Gymnastics is described in detail.
Then, step 302 is performed, polysilicon capping layer is formed on the gate dielectric 204
205, the structure formed is as shown in Figure 2 B.
As shown in Figure 2 B, on gate dielectric 204, i.e., formed on ONO layer 204
Polysilicon capping layer 205, the stop that the polysilicon capping layer 205 can be etched as follow-up ONO
Layer.Exemplarily.In the present embodiment, the polysilicon capping layer is formed by CVD techniques
205, its thickness is
Then, step 303 is performed, in the polysilicon capping layer 205 and the gate dielectric
Groove 206 is formed in 204, the groove 206 exposes the floating boom 203, the knot formed
Structure is as shown in Figure 2 C.
It is exemplary, in the present embodiment, by suitable photoetching and etching technics described many
Groove 206, the groove 206 are formed in crystal silicon cap rock 205 and the gate dielectric 204
The exposure floating boom 203, so as to which various MOS crystal can be realized in the high-pressure area of device
The function of pipe.The etch process can be wet-etching technology or dry method etch technology, dry method
Etch process includes but is not limited to：Reactive ion etching (RIE), ion beam milling, plasma
Body is etched or is cut by laser.The source gas of the dry etching can include CF4, CHF3
Or other fluorocarbon gas.
It is exemplary, in this embodiment, the polysilicon capping layer is etched using dry etch process
205 and the gate dielectric 204, and as an example, in the present embodiment, the etching
For dry etching, the technological parameter of the dry etching includes：Etching gas comprising CF4,
The gases such as CHF3, its flow is respectively 50sccm~500sccm, 10sccm~100sccm,
Pressure is 2mTorr~50mTorr, wherein, sccm represents cc/min, mTorr generations
Table milli millimetres of mercury.
Further, due to being formed in step 302 after polysilicon capping layer 205, and in step
In rapid 103, because environment has oxygen, and cause polysilicon capping layer, or even the bottom of groove 206
Floating boom surface formed oxide layer 207, such as silica, if so step 103 it
Direct control gate afterwards, then can as shown in Figure 2 D, in polysilicon capping layer 205 and control gate 208
Between there is dielectric layer 207, so the high-pressure area of device can be caused to go wrong, for example, wiped
Except state failure.Therefore, in the present embodiment, in order to avoid there is such case, performing
After complete step 303, not directly formed control gate, but first to oxide layer 207 at
Reason, this will be described below.
It is understood that groove 206 need not be formed in all regions of device, for example for
For NAND device, groove 206 is only formed in the high-pressure area and area of low pressure of device, and
Do not formed in the memory cell region of device.Certainly, in other devices, it is also possible to
Made a change according to specific situation.
Then, step 304, surface and the groove to the polysilicon capping layer 205 are performed
The surface for the floating boom 203 that 206 bottoms are exposed is handled, so that the polysilicon capping layer 205
The oxide on the surface of the floating boom 203 exposed with the channel bottom is changed into fluoride, institute's shape
Into structure as shown in Figure 2 E.
It is exemplary, in the present embodiment, the oxide layer is handled using ammonium fluoride (NH4F)
207, to be that oxide layer 207 is changed into fluoride layer 209.Specifically reflection process is：NH4F
+SiO2→(NH4)2SiF6(solid)+H2O.It is exemplary, in the present embodiment, reflection temperature
Spend for 10 DEG C to 50 DEG C.
Then, step 305 is performed, the polysilicon capping layer 205 and the groove 206 is removed
The fluoride on the surface for the floating boom 203 that bottom is exposed, the structure formed is as shown in Figure 2 F.
Due to fluoride, such as (NH4) 2SiF6 is volatile solids, can be made by heating
It is gaseous state by Solid State Transformation, so that by air extractor abstraction reaction chamber.Exemplarily, exist
In the present embodiment, made a return journey fluorine removal compound layer 209 by annealing process, annealing temperature is 100 DEG C
~300 DEG C, annealing time is 1 minute to 30 minutes.
It is understood that step 304 and step 305 can be completed each respectively, can also
Completed in the same chamber using SiCoNi cleanings.SiCoNi techniques mainly include two
Step：The long-range plasma etch of NF3/NH3 and in-situ annealing, this two step is all in same chamber body
It is interior to complete.In etching process, wafer is placed on the bottom that temperature is strictly controlled at 35 DEG C
On seat, NF3 and NH3 are transformed into ammonium fluoride (NH4F) and difluoro by the plasma-based of low-power
Change ammonia.Fluoride is condensed in crystal column surface, and is preferentially reacted with oxide, forms hexafluoro silicon ammonia
((NH4)2SiF6).This silicate can distil in more than 70 DEG C environment.It is in situ
In annealing process, wafer is moved to the position close to heater block, and the hydrogen of flowing is by warm
Amount is taken on wafer, and wafer is heated to more than 100 DEG C in a short period of time, makes six
Fluorine silicon ammonolysis craft is gaseous SiF4, NH3 and HF, and is pumped away.
It will also be appreciated that also including pre-cleaning processes before step 104, to go deoxygenation
Change layer and the residue on floating boom surface, to be better carried out subsequent technique.
Finally, step 306 is performed, is formed and covers the polysilicon capping layer 205 and the ditch
The control gate 208 of groove 203, the structure formed is as shown in Figure 2 G.
It is exemplary, in this embodiment, formed by techniques such as PVD, CVD, ALD
The polysilicon layer of the polysilicon capping layer 205 and the groove 203, to be used as control gate.
It is understood that in the present embodiment, after the step is completed, polysilicon capping layer
205 can merge with the polysilicon layer that the step is formed, collectively as control gate in follow-up
Each step for showing the present invention is for only for ease of in electrode material layer, accompanying drawing, so polysilicon
The polysilicon formed in cap rock and this step uses different representations.
So far, the processing step that method according to embodiments of the present invention is implemented, Ke Yili are completed
Solution, the present embodiment manufacturing method of semiconductor device not only includes above-mentioned steps, in above-mentioned step
Before rapid, among or may also include other desired step afterwards, it is included in this implementations and made
In the range of making method.
Embodiment two
The present invention also provides a kind of semiconductor devices, as shown in figure 4, semiconductor devices 400 is wrapped
Include：Semiconductor substrate 401, tunneling dielectric is sequentially formed with the Semiconductor substrate 401
Layer 402, floating boom 403, gate dielectric 404, polysilicon capping layer 405 and control gate 407,
And the groove 406 in the gate dielectric 405, the covering of control gate 407 institute
State polysilicon capping layer 405 and the groove 406.
Wherein Semiconductor substrate 401 can be at least one of following material being previously mentioned：Si、
Ge, SiGe, SiC, SiGeC, InAs, GaAs, InP or other III/V compounds half
Conductor, in addition to the sandwich construction etc. that constitutes of these semiconductors or for silicon-on-insulator (SOI),
Silicon (SSOI), stacking SiGe (S-SiGeOI), insulator on insulator are laminated on insulator
Upper SiGe (SiGeOI) and germanium on insulator (GeOI) etc..Can in Semiconductor substrate
To be formed with device, such as NMOS and/or PMOS.Equally, in Semiconductor substrate also
Conductive member is could be formed with, conductive member can be the grid, source electrode or drain electrode of transistor,
It can also be metal interconnection structure for being electrically connected with transistor, etc..In addition, in semiconductor lining
Isolation structure can also be formed with bottom, the isolation structure is shallow trench isolation (STI) knot
Structure or selective oxidation silicon (LOCOS) isolation structure are used as example.In the present embodiment,
The constituent material of Semiconductor substrate 401 selects monocrystalline silicon.
Tunnel dielectric layer 402 is used as insulating barrier, such as grid oxic horizon, tunnel dielectric layer
202 can use various suitable materials, exemplarily, in the present embodiment, tunneling dielectric
Layer 202 uses silica, and its thickness isTunnel dielectric layer 402 can be by this
The technique such as field conventional PVD, CVD, ALD and thermoforming process is formed, exemplary,
In the present embodiment, the tunnel dielectric layer 202 is used as by thermal oxidation method formation silica.
The material of floating boom 403 uses such as polysilicon, its by PVD commonly used in the art,
CVD, ALD are formed.Exemplarily, floating boom is formed by CVD method in the present embodiment
203, its thickness is
Gate dielectric 404 can select various suitable dielectric materials, exemplary in this implementation
In example, in order to improve the interface performance between each layer, and with high dielectric constant, grid is situated between
Electric layer 404 uses ONO structure, i.e. oxide layer/nitration case/oxidation Rotating fields, wherein first
Layer oxide layer is to be located at the oxide layer on floating boom 403, can be formed by thermal oxidation method, oxygen
Nitration case on first layer oxide layer, such as silicon nitride, can by such as PVD, CVD,
The techniques such as ALD are formed, and second of oxide layer can pass through such as PVD, CVD, ALD
And thermal oxidation technology is formed, these techniques are technique commonly used in the art, will not be had herein to it
Gymnastics is described in detail.
Polysilicon capping layer 405, groove 406 and control gate 407 pass through method commonly used in the art
Formed, will not be repeated here.
It is understood that in the present embodiment, polysilicon capping layer 405 and the meeting of control gate 407
Fusion, collectively as the electrode material layer of control gate in follow-up, is for only for ease of in accompanying drawing
Each device layer is shown, so polysilicon capping layer 405 and control gate 407 use different expression sides
Formula.
Embodiment three
Yet another embodiment of the present invention provides a kind of electronic installation, including above-mentioned semiconductor device
And the electronic building brick being connected with the semiconductor devices.Wherein, the semiconductor devices includes：
Semiconductor substrate, is sequentially formed with tunnel dielectric layer, floating boom, grid on the semiconductor substrate
Pole dielectric layer, polysilicon capping layer and control gate, and the groove in the gate dielectric,
The control gate covers the polysilicon capping layer and the groove.
Wherein, the electronic building brick, can be any electronic building bricks such as discrete device, integrated circuit.
The electronic installation of the present embodiment, can be mobile phone, tablet personal computer, notebook computer, on
Net sheet, game machine, television set, VCD, DVD, navigator, camera, video camera,
Any electronic product such as recording pen, MP3, MP4, PSP or equipment, or it is any including
The intermediate products of the semiconductor devices.
The electronic installation of the embodiment of the present invention, the above-mentioned semiconductor devices due to having used, thus
Equally there is above-mentioned advantage.
The present invention is illustrated by above-described embodiment, but it is to be understood that, it is above-mentioned
The purpose that embodiment is only intended to illustrate and illustrated, and be not intended to limit the invention to described
Scope of embodiments in.In addition it will be appreciated by persons skilled in the art that not office of the invention
It is limited to above-described embodiment, more kinds of modification can also be made according to the teachings of the present invention and repaiied
Change, these variants and modifications are all fallen within scope of the present invention.The present invention's
Protection domain is defined by the appended claims and its equivalent scope.
Claims (7)
1. a kind of preparation method of semiconductor devices, it is characterised in that comprise the steps：
S1：There is provided Semiconductor substrate, be formed with the semiconductor substrate tunnel dielectric layer,
Floating boom and gate dielectric；
S2：Polysilicon capping layer is formed on the gate dielectric；
S3：Groove is formed in the polysilicon capping layer and the gate dielectric；
S4：The surface for the floating boom that surface and the channel bottom to the polysilicon capping layer are exposed
Handled, so that the surface for the floating boom that the polysilicon capping layer and the channel bottom expose
Oxide is changed into fluoride；
S5：Remove the fluorination on the surface of the floating boom of the polysilicon capping layer and the channel bottom
Thing；
S6：Form the control gate for covering the polysilicon capping layer and the groove.
2. the preparation method of semiconductor devices according to claim 1, it is characterised in that
In the step S4, the polysilicon capping layer and the channel bottom are revealed using ammonium fluoride
The floating boom surface gone out is handled, so that the polysilicon capping layer and the channel bottom floating boom
The oxide on surface is changed into fluoride.
3. the preparation method of semiconductor devices according to claim 1, it is characterised in that
In the step S5, the fluoride is removed by performing heat treatment, so that the fluorine
Compound is gaseous state by Solid State Transformation and is pumped.
4. the preparation method of semiconductor devices according to claim 1, it is characterised in that
The step S4 and S5 is completed by performing SiCoNi cleanings.
5. the preparation method of semiconductor devices according to claim 1, it is characterised in that
Also include prerinse step before the step S4, to remove the table of the polysilicon capping layer
The residue on the surface for the floating boom that face and the channel bottom expose.
6. a kind of preparation method of semiconductor devices using as described in one of claim 1-5
The semiconductor devices of making, it is characterised in that including：
Semiconductor substrate,
Be sequentially formed with the semiconductor substrate tunnel dielectric layer, floating boom, gate dielectric,
Polysilicon capping layer and control gate,
And the groove in the gate dielectric, the control gate covering polysilicon
Cap rock and the groove.
7. a kind of electronic installation, it is characterised in that including partly leading as claimed in claim 6
Body device and the electronic building brick being connected with the semiconductor devices.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1430283A (en) * | 2001-12-31 | 2003-07-16 | 世界先进积体电路股份有限公司 | High coupling rate rapid flash memory and its manufacturing method |
| US20040080020A1 (en) * | 2000-10-30 | 2004-04-29 | Kabushiki Kaisha Toshiba | Semiconductor device having two-layered charge storage electrode |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20040080020A1 (en) * | 2000-10-30 | 2004-04-29 | Kabushiki Kaisha Toshiba | Semiconductor device having two-layered charge storage electrode |
| CN1430283A (en) * | 2001-12-31 | 2003-07-16 | 世界先进积体电路股份有限公司 | High coupling rate rapid flash memory and its manufacturing method |
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| 臧松干，王鹏飞，林曦，刘昕彦，丁士进，张卫: "一种新型高速嵌入式动态随机存储器", 《微电子学》 * |
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