CN106953636B - R/D converter with excitation source and parallel/serial digital output and implementation method thereof - Google Patents

R/D converter with excitation source and parallel/serial digital output and implementation method thereof Download PDF

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CN106953636B
CN106953636B CN201611270031.4A CN201611270031A CN106953636B CN 106953636 B CN106953636 B CN 106953636B CN 201611270031 A CN201611270031 A CN 201611270031A CN 106953636 B CN106953636 B CN 106953636B
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output
gate
amplifier
output end
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CN106953636A (en
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余桂周
高群
姚海霆
周晶
吴小晔
刘嘉杰
王子元
任远杰
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CETC 43 Research Institute
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M9/00—Parallel/series conversion or vice versa

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  • Theoretical Computer Science (AREA)
  • Transmission And Conversion Of Sensor Element Output (AREA)
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Abstract

The invention relates to an R/D converter with an excitation source and parallel/serial digital output and a realization method thereof, comprising an excitation generating circuit and a solid-state control transformer circuit which are connected with a rotary transformer, wherein the output end of the solid-state control transformer circuit is connected with a phase-sensitive demodulation circuit through an alternating-current error amplifying circuit, the excitation generating circuit is connected with the phase-sensitive demodulation circuit through a synthetic reference circuit, the output end of the phase-sensitive demodulation circuit is connected with a sixteen-bit reversible counting circuit through a first integrating circuit and a voltage-controlled oscillation circuit in sequence, the solid-state control transformer circuit outputs parallel digital through a data latch, the data latch outputs serial digital through the parallel/serial conversion circuit, and the output end of the sixteen-bit reversible counting circuit is connected with the output end of the solid-state control transformer circuit. The invention realizes the conversion from the angle analog signal output by the rotary transformer to the binary digital signal, and the converted binary digital signal can be output to the post-stage processing circuit in parallel or serial.

Description

R/D converter with excitation source and parallel/serial digital output and implementation method thereof
Technical Field
The invention belongs to the technical field of integrated circuits, and particularly relates to an R/D converter with an excitation source and parallel/serial digital output and an implementation method thereof.
Background
The rotary transformer is also called synchronous decomposer and is a micro motor for control. The indirect measuring device is used for converting mechanical angle into electric signal with a certain function relation with the rotation angle, and is mainly used for triangle operation, coordinate conversion, angle data transmission and the like. In the shaft angular displacement measuring system, the device is a measuring element widely applied due to the characteristics of high conversion precision, good stability, strong environmental adaptability and the like.
The signal output of the rotary transformer is two-phase orthogonal analog signals, the amplitude of the analog signals changes with the sine and cosine of the rotation angle, and the frequency and the excitation frequency are consistent. In the field of industrial detection control, it is necessary to convert an analog signal output from a resolver into a digital signal for a microprocessor at the back end to perform data processing. In addition, a rotary transformer, a conversion chip or a conversion circuit built by a split structure in the system is required to provide an excitation signal, and the existing circuit is generated by an external excitation source. The digital signal output by the conversion circuit has two output modes of serial or parallel for the microprocessor at the back end to carry out digital processing, but the current conversion circuit has only one output mode, so that the acquisition mode of the digital signal processed at the back end is limited.
Disclosure of Invention
The invention aims to provide an R/D converter with an excitation source and parallel/serial digital output and a realization method thereof, which realize the conversion from an angle analog signal output by a rotary transformer to a binary digital signal, and the converted binary digital signal can be selectively output to a post-stage processing circuit in parallel or in series.
In order to achieve the above purpose, the present invention adopts the following technical scheme:
an R/D converter with an excitation source and parallel/serial digital output comprises an excitation generating circuit, a solid-state control transformer circuit, an alternating current error amplifying circuit, a phase-sensitive demodulation circuit, a synthetic reference circuit, a first integrating circuit, a voltage-controlled oscillation circuit, a sixteen-bit reversible counting circuit, a data latch and a parallel/serial conversion circuit;
the excitation generation circuit is connected with the rotary transformer and is used for providing external reference signals of the rotary transformer and the conversion circuit; the solid-state control transformer circuit is connected with the rotary transformer and is used for carrying out difference between sine and cosine input signals output by the rotary transformer and digital signals generated by the reversible counter to obtain error signals; the synthesis reference circuit is connected with the excitation generation circuit and is used for eliminating errors between internal signals and reference signals, and the BIT signals generated by the synthesis reference circuit are used for testing and alarming the amplitudes and the phase differences of internal sine and cosine input signals and reference signals and half-wave signals output by the voltage-controlled oscillation circuit;
the output end of the synthesis reference circuit is connected with the input end of the sixteen-bit reversible counting circuit through the phase-sensitive demodulation circuit; the input end of the alternating current error amplifying circuit is connected with the output end of the solid-state control transformer circuit, the output end of the alternating current error amplifying circuit is connected with the input end of the phase-sensitive demodulation circuit, and the alternating current error amplifying circuit is used for amplifying alternating current full-wave signals with gains of 1 and 4, and the amplified alternating current full-wave signals are converted into half-wave signals through the phase-sensitive demodulation circuit;
the output end of the phase-sensitive demodulation circuit is connected with the input end of the voltage-controlled oscillation circuit through the first integrating circuit; the output end of the voltage-controlled oscillation circuit is respectively connected with the phase-sensitive demodulation circuit and the sixteen-bit reversible counting circuit and is used for generating pulse signals with different frequencies according to the magnitude of the input direct-current error voltage; the parallel/serial conversion circuit is connected with the data latch and is used for converting parallel sixteen-bit digital signals output by the data latch into serial output.
The excitation generation circuit comprises a second integration circuit connected with the rotary transformer, the input end of the second integration circuit is connected with the antistatic protection circuit, the output end of the second integration circuit is connected with the input end of the third integration circuit through the inverting circuit, the output end of the antistatic protection circuit is connected with the input end of the third integration circuit, the input end of the third integration circuit is respectively connected with the output ends of the frequency stabilizing circuit and the amplitude stabilizing circuit, and the output ends of the second integration circuit, the power amplifying circuit and the output end of the third integration circuit are the output ends of the excitation generation circuit.
The second integrating circuit and the third integrating circuit respectively regulate signal frequency through external capacitors C1 and C2, and the capacitors C1 and C2 meet the following formulas:
wherein F is OSC Is the output frequency.
The solid-state control transformer circuit comprises a two-stage rough dividing circuit and a fine dividing circuit, wherein the input end of the first-stage rough dividing circuit is connected with the rotary transformer, the output end of the first-stage rough dividing circuit is connected with the input end of the fine dividing circuit through the second-stage rough dividing circuit, and the output end of the fine dividing circuit is the output end of the solid-state control transformer circuit.
The alternating current error amplifying circuit comprises an amplifier Q1 and a gating device N1, wherein a selection A1 end of the gating device N1 is grounded, the A0 end of the gating device N1 is connected with the output end of the amplifier Q1, the control end of the gating device N0 is connected with the sixteen-bit reversible counting circuit, the output end of the gating device is connected with the reverse input end of the amplifier Q1 through a capacitor C1, the non-inverting input end VO of the amplifier Q1 is connected with the solid-state control transformer circuit, the output end of the amplifier Q1 is connected with the phase-sensitive demodulation circuit, and the reverse input end of the amplifier Q1 is connected with the output end of the amplifier Q1 through a capacitor C2.
The phase-sensitive demodulation circuit comprises a gating device N2, N3, N4 and N5 and an amplifier Q2, wherein the selection O end of the gating device N2 is the input end of the phase-sensitive demodulation circuit, the output end of the gating device N2 is connected with the selection 1 end of the gating device N3, the selection 1 end of the gating device N3 is connected with the reverse input end of the amplifier Q2 through a resistor R1, the selection 0 end of the gating device N3 is connected with the output end of the amplifier Q2 through resistors R2 and R3 in sequence, the output end of the gating device N2 is connected with the output end of the amplifier Q2 through a resistor R3, the control end of the gating device N2 is connected with the control end of the gating device N4 through a NOT gate U1, the selection 0 end of the gating device N4 is connected with the selection 1 end of the gating device N4 and grounded, the output end of the gating device N4 is connected with the selection 1 end of the gating device N5 through a resistor R4 and the non-inverting input end of the amplifier Q2, and the selection 1 end of the gating device N5 is connected with the non-inverting input end of the amplifier Q2 through a resistor R6 and the non-inverting input end of the amplifier Q2 is grounded.
The voltage-controlled oscillating circuit comprises an amplifier Q3 and Q4, a capacitor C3 and a switch S1, wherein the inverting input end of the amplifier Q3 is connected with the first integrating circuit through a resistor R7, the output end of the amplifier Q3 is connected with the inverting input end of the amplifier Q4, the inverting input end of the amplifier Q3 is connected with the output end of the amplifier Q3 through the capacitor C3, the switch S1 is connected at two ends of the capacitor C3 in parallel, the non-inverting input end of the amplifier Q4 is a reference voltage end, and the output end of the amplifier Q4 is connected with the control end of the switch S1.
The parallel/serial conversion circuit comprises a plurality of double-control D flip-flops, wherein the input D ends of the double-control D flip-flops are used for receiving sixteen-bit parallel data output by the data latch, and the output ends of the double-control D flip-flops are converted into serial data sequentially output from high order to low order through the digital conversion circuit.
The digital conversion circuit comprises NOT gates U2, U17 and U12, the input CS end of the NOT gate U17 is a chip selection signal end, the input RW end of the NOT gate U12 is a read-write control signal end, the input MODE end of the NOT gate U2 is a MODE selection signal end, the first input CLK end of the NOT gate U7 is a clock signal end, the output end of the NOT gate U2 is connected with the first input end of the NOT gate U4 through the NOT gate U3, the output end of the NOT gate U4 is connected with the input FE end of the double-control D trigger through the NOT gate U5 and U6 in sequence, the output end of the NOT gate U7 is connected with the input CE end of the double-control D trigger through the NOT gate U5 and U9 in sequence, the output end of the NOT gate U17 is connected with the second input end of the NOT gate U4, the output end of the NOT gate U12 is connected with the first input end of the NOT gate U10 through the NOT gate U11, the two output ends of the NOT gate U10 are respectively connected with the two input ends of the NOT gate U4 and the output end of the NOT gate U14 and the double-control D trigger, the NOT gate U14 and the output end of the NOT gate U14 is connected with the two output ends of the NOT gate U14 and the NOT gate U14.
A realization method of an R/D converter with an excitation source and parallel/serial digital output comprises the following steps:
(1) The excitation generation circuit outputs two paths of orthogonal signals to provide excitation signals for the rotary transformer, and the rotary transformer generates two paths of sin and cos signals which change along with the angle;
(2) The solid-state control transformer circuit receives the sin and cos signals and the digital signal generated by the sixteen-bit reversible counting circuit, and performs difference calculation and comparison on the sin and cos signals to obtain an error signal KEsin (theta-phi);
(3) The error signal KEsin (theta-phi) is amplified by an alternating current error amplifying circuit to obtain an error amplifying signal NCI1, and the error amplifying signal NCI1 is input to a later stage, and a half-wave signal TP1 is obtained by a phase-sensitive demodulation module and a voltage-controlled oscillation circuit;
(4) The half-wave signal TP1 is calculated by a first integrating circuit to obtain VEL direct current level, and pulse and counting direction signals generated by a voltage-controlled oscillating circuit enter a sixteen-bit reversible counting circuit to be counted;
(5) A sixteen-bit digital output signal of the sixteen-bit reversible counting circuit enters a data latch, and the sixteen-bit digital signal is latched and outputted in parallel through the data latch to represent a digital angle;
(6) The parallel sixteen-bit digital signals are converted into sixteen-bit serial output digital signals through a parallel/serial conversion circuit.
According to the technical scheme, the R/D converter with the excitation source and the parallel/serial digital output and the implementation method thereof realize the conversion from the angle analog signal output by the rotary transformer to the binary digital signal, and the converted binary digital signal can be selectively output to the post-processing circuit in parallel or in series. The invention has the advantages of adjustable excitation frequency and data output mode, programmable resolution, speed and voltage, high precision, low power consumption, high integration level and the like.
Drawings
FIG. 1 is a circuit block diagram of the present invention;
FIG. 2 is a circuit block diagram of the stimulus generation circuit of the present invention;
FIG. 3 is a circuit block diagram of a solid state control transformer of the present invention;
FIG. 4 is a circuit diagram of a solid state control transformer of the present invention;
FIG. 5 is a circuit diagram of an AC error amplifying circuit of the present invention;
fig. 6 is a circuit diagram of a phase sensitive demodulation circuit of the present invention;
FIG. 7 is a circuit diagram of a voltage controlled oscillator circuit of the present invention;
FIG. 8 is a circuit diagram of a parallel/serial conversion circuit of the present invention;
fig. 9 is a schematic diagram of a coarse-division circuit of the solid-state control transformer circuit of the present invention.
Detailed Description
The invention is further described below with reference to the accompanying drawings:
as shown in fig. 1, the R/D converter with an excitation source and parallel/serial digital output of the present embodiment includes an excitation generating circuit 1, a solid-state control transformer circuit 2, an ac error amplifying circuit 5, a phase-sensitive demodulation circuit 7, a synthesis reference circuit 6, a first integrating circuit 12, a voltage-controlled oscillating circuit 11, a sixteen-bit up-down counting circuit 8, a data latch 3, and a parallel/serial converting circuit 4, and the above circuits are integrated on a single chip using a standard CMOS integrated circuit process.
The excitation generation circuit 1 is connected with the rotary transformer and is used for providing external reference signals of the rotary transformer and the conversion circuit; the solid-state control transformer circuit 2 is connected with the rotary transformer and is used for carrying out difference between sine and cosine input signals output by the rotary transformer and digital signals generated by the reversible counter to obtain error signals; the output end of the synthesis reference circuit 6 is connected with the input end of the sixteen-bit reversible counting circuit 8 through the phase-sensitive demodulation circuit 7; the input end of the alternating current error amplifying circuit 5 is connected with the output end of the solid-state control transformer circuit 2, and the output end of the alternating current error amplifying circuit is connected with the input end of the phase-sensitive demodulation circuit 7, and is used for amplifying alternating current signals with gains of 1 and 4, and the amplified alternating current full-wave signals are converted into half-wave signals through the phase-sensitive demodulation circuit 7; the output end of the phase-sensitive demodulation circuit 7 is connected with the input end of the voltage-controlled oscillation circuit 11 through the first integration circuit 12; the output end of the voltage-controlled oscillation circuit 11 is respectively connected with the phase-sensitive demodulation circuit 7 and the sixteen-bit reversible counting circuit 8, and the voltage-controlled oscillation circuit 11 is used for generating pulse signals with different frequencies according to the magnitude of the input direct-current error voltage; the data latch 3 is interactively connected with the solid-state control transformer circuit 2, and the parallel/serial conversion circuit 4 is used for converting parallel sixteen-bit digital signals output by the data latch 3 into serial signals and outputting the serial signals. The output end of the sixteen-bit reversible counting circuit 8 is externally connected with an internal encoder 10, and the alternating current error amplifying circuit 5 is externally connected with a resolution control circuit 9.
As shown in fig. 2, the excitation generating circuit 1 includes a second integrating circuit 11 connected to the rotary transformer, an input end of the second integrating circuit 11 is connected to the antistatic protection circuit 10, an output end of the second integrating circuit is connected to an input end of the third integrating circuit 14 via the inverting circuit 12, an output end of the antistatic protection circuit 10 is connected to an input end of the third integrating circuit 14, an input end of the third integrating circuit 14 is connected to output ends of the frequency stabilizing circuit 13 and the amplitude stabilizing circuit 15, and an output end of the second integrating circuit 11 and an output end of the third integrating circuit 14 are output ends of the excitation generating circuit 1. The excitation generating circuit 1 outputs two paths of orthogonal signals of 2.5Vrms, the frequency of the signals can be adjusted through the external capacitors C1 and C2, and the output orthogonal signals can generate excitation signals with different amplitudes through external push-pull amplification, so that the excitation requirements of rotary transformers with different types are met. The external capacitor and the working frequency meet the following conditions:
wherein F is OSC Is the output frequency.
In the circuit application, a power operational amplifier circuit comprising an operational amplifier and a push-pull power amplifier can be externally added, and the circuit comprises an input circuit 20, an operational amplifier circuit 19, a power amplifier circuit 16, an anti-transient protection circuit 18 and an over-current protection circuit 17, wherein the output end of the input circuit 20 is connected with the power amplifier circuit 16 through the operational amplifier circuit 19, and the input end of the power amplifier circuit 16 is connected with the anti-transient protection circuit 18 and the over-current protection circuit 17. The output of the reverse phase or the positive phase power amplifier can be obtained by only connecting any one of the two orthogonal signals output by the excitation generating circuit 1 to the power operational amplifier input end. And a resistor Rs is connected in series between the two paths of orthogonal signal output ends and the power operational amplifier input end, so that the voltage output by the power amplifier can be regulated, and the requirements between the required voltage value and the regulated resistance value are met:
wherein Rs is a series resistance, V OUT And outputting voltage for the power operational amplifier.
The synthetic reference circuit 6 eliminates errors generated by phase differences between internal signals and reference signals through a comparator and an analog switch circuit in the synthetic reference circuit, and the generated BIT signal is used for testing and alarming internal sine and cosine input signals, amplitude and phase differences of the reference signals and output signals of the phase demodulator, and alarms when the BIT signal is zero. Because of the inductive nature of the resolver, its output signal leads the input reference signal, and if the uncompensated reference signal is used to demodulate the output of the control transformer, the quadrature voltage is not completely eliminated. As can be seen from the main block diagram, the synchronization of the converters is achieved based on the internal reference signals generated by the sin and cos input signals, so that the phase of the synchronization reference signal is determined by the input signals, which reduces the quadrature error.
As shown in fig. 3 and 4, the solid-state control transformer circuit 2 comprises a two-stage rough dividing circuit and a fine dividing circuit, wherein the input end of the first-stage rough dividing circuit 21 is connected with the rotary transformer, the output end of the first-stage rough dividing circuit 21 is connected with the input end of the fine dividing circuit 23 through the second-stage rough dividing circuit 22, and the output end of the fine dividing circuit 23 is the output end of the solid-state control transformer circuit 2.
The high five-bit digital signal controls the first-stage coarse-dividing circuit 21 to be roughly divided into 11.25 degrees, the middle four-bit digital signal controls the second-stage coarse-dividing circuit to be roughly divided into 0.703 degrees, the low seven-bit digital signal controls the subdivision circuit to be subdivided into 0.0055 degrees, the error of the obtained digital signal and the obtained analog signal is within 0.0055 degrees, and the circuit schematic diagram is shown in fig. 4.
(1) First-stage rough separation circuitThe partial circuit is composed of a switch capacitor and an operational amplifier, and the high five-bit digital signals Q01-Q05 control a switch part in the circuit through a logic module DEC_5B. Input signalAndv1 and V2 are obtained by operational amplifier A1 and A2 respectively, and +.>
V1＝-Kcos(θ-90°)，V2＝-Ksinθ＝Ksin(θ-180°)
cosθ＝sin(θ-270°)
Q01 and Q02 determine which two signals Ksin theta, ksin (theta-90 degrees), ksin (theta-180 degrees) and Ksin (theta-270 degrees) are transmitted to A3 for operation. When θ is at the first quadrant, sin θ and Ksin (θ -90 °) are passed to the subsequent stage, thus
The feedback coefficient of the operational amplifier A3 (which can be obtained by capacitance ratio) exactly counteracts cos by 45 degrees to obtain V4 = sin (theta-45 degrees), V4 is sent to A4, the other signal sent to A4 is determined by Q01-Q03, when 0 is less than or equal to theta less than 45 degrees,
the feedback coefficient of the operational amplifier A4 exactly counteracts cos by 22.5 degrees to obtain V6 = sin (theta-22.5 degrees), V6 is sent to A6, the other signal sent to A6 is determined by Q01-Q04, when 0 is less than or equal to theta less than 22.5 degrees,
when the resolution is 16 bits, the A6 magnification is 4 times, V8=4Kcos11.25 DEG sin (theta-11.25 DEG), and when the resolution is less than 16 bits, the magnification is 1 time, and V8=Kcos11.25 DEG sin (theta-11.25 DEG).
The signal to A5 is determined by Q01 to Q05, when 0.ltoreq.θ < 11.25 degrees,
when the resolution is 16 bits, the amplification factor of A5 is 4 times, v10=4kcos11.25 ° sin θ, and when the resolution is less than 16 bits, the amplification factor is 1 time, v10=kcos11.25 ° sin θ.
The above process roughly divides 360 degrees to 11.25 degrees, the input analog angle theta is finally positioned in the range of 11.25 degrees, and when the angle theta is in other angle ranges, the process also works according to the above process, and V8 and V10 are generated and sent to the secondary rough division circuit. When θ is within any one of the 11.25 ° ranges, the following two voltages are sent to the subsequent stage circuit.
K1sin11.25°sin(θ-n×11.25°)，K1cos11.25°sin[θ-(n+1)×11.25°]
Where K1 is determined by the resolution, n=0, 1, 2, …, 31.
(2) As shown in fig. 9, the second-stage rough dividing circuit 22 is composed of a resistor string composed of 16 resistors, and the voltages V8 and V10 generated in the previous stage are divided by the resistor string, and the digital signals Q06 to Q09 generate a switching control signal via the logic portion dec_4b to select the voltage across the resistor as the output. The sin function can be considered approximately linear over a range of 11.25 °, with 11.25 ° further roughly divided into 0.703 °.
The outputs VO0, VO1 are sent to the subsequent stage for further subdivision, which can be represented by the following formula.
VO0＝K1cos11.25°sin(θ-m×0.703°)
VO1＝K1cos11.25°sin[θ-(m+1)×0.703°]
Where m=0, 1, 2, …, 511.
(3) The subdivision circuit 23 adopts a charge-scaled DA converter, inputs two signals with the difference of 0.703 DEG output by the front stage, the two signals are respectively connected with capacitors with different numbers, the other ends of the capacitors are connected together to be used as output, the number of the capacitors is determined by digital signals Q010-Q016, different output voltages are obtained by combining the different capacitors, and the lowest digital signal (determined by resolution) subdivides 0.703 DEG
0.703°/2n-9，
For example, the 16bit corresponds to a precision of 0.0055 °. The output VO is an error signal of analog angle and digital angle, which can be expressed as:
VO＝K1cos11.25sin(θ-m×0.703°-β×0.703°)
wherein beta is more than or equal to 0 and less than 1.
After loop feedback, the error signal finally approaches 0, and θ=mx0.703° +βx0.703° is obtained, and the corresponding digital signal is the digital angle Φ.
As shown in fig. 5, the error amplifying circuit 5 includes an amplifier Q1 and a gate N1, the select A1 end of the gate N1 is grounded, the A0 end thereof is connected to the output end of the amplifier Q1, the control end thereof is connected to the sixteen-bit up-down counting circuit 8, the output end thereof is connected to the inverting input end of the amplifier Q1 via a capacitor C1, the non-inverting input end VO of the amplifier Q1 is connected to the solid-state control transformer circuit 2, the output end of the amplifier Q1 is connected to the phase-sensitive demodulation circuit 7, and the inverting input end of the amplifier Q1 is connected to the output end thereof via a capacitor C2.
The gain of the error amplifying circuit is determined by the resolution, when the gain of the operational amplifier is 1, when the gain of the operational amplifier is 12-16 bits, the gain of the operational amplifier is 4, and the control signal is gated A0.
As shown in fig. 6, the phase-sensitive demodulation circuit 7 converts the ac full-wave signal amplified by the error signal into a half-wave signal, and then enters the post-stage integrating circuit. The phase-sensitive demodulation circuit 7 comprises a gating device N2, N3, N4, N5 and an amplifier Q2, wherein the selection O end of the gating device N2 is the input end of the phase-sensitive demodulation circuit 7, the output end of the gating device N2 is connected with the selection 1 end of the gating device N3, the selection 1 end of the gating device N3 is connected with the reverse input end of the amplifier Q2 through a resistor R1, the selection 0 end of the gating device N3 is connected with the output end of the amplifier Q2 through resistors R2 and R3, the output end of the gating device N2 is connected with the output end of the amplifier Q2 through resistors R2 and R3 in sequence, the selection 0 end of the gating device N4 is connected with the selection O end of the gating device N2 through a NOT gate U1, the selection 1 end of the gating device N2 is grounded, the output end of the gating device N4 is connected with the selection 1 end of the gating device N5 through a resistor R4, the selection 1 end of the gating device N5 is connected with the non-phase input end of the amplifier Q2 through a resistor R5, and the non-phase input end of the amplifier Q2 is connected with the non-phase input end of the amplifier Q6 through a resistor R6.
As shown in fig. 7, the voltage-controlled oscillating circuit 11 includes amplifiers Q3 and Q4, a capacitor C3 and a switch S1, wherein an inverting input terminal of the amplifier Q3 is connected to the first integrating circuit 12 through a resistor R7, an output terminal of the amplifier Q3 is connected to an inverting input terminal of the amplifier Q4, an inverting input terminal of the amplifier Q3 is connected to an output terminal of the amplifier Q3 through the capacitor C3, the switch S1 is connected in parallel to two ends of the capacitor C3, a non-inverting input terminal of the amplifier Q4 is a reference voltage terminal, and an output terminal of the amplifier Q4 is connected to a control terminal of the switch S1. The voltage-controlled oscillation circuit 11 generates pulse signals with different frequencies according to the magnitude of the input DC error voltage, the pulse signals are sent to the counter for counting, and meanwhile, the VCO also generates signals for controlling the counting direction of the counter, and a ring oscillator is arranged in the VCO and is used for generating an oscillation signal of 2.66 MHz.
As shown in fig. 8, the parallel/serial conversion circuit 4 converts the parallel sixteen-bit digital signals output from the data latch 3 into serial data, and the parallel/serial conversion circuit 4 includes a plurality of double-control D flip-flops 42, and an input D terminal of the plurality of double-control D flip-flops 42 is configured to receive sixteen-bit parallel data output from the data latch 3, and an output terminal thereof is converted into serial data sequentially output from high-order bits to low-order bits via the digital conversion circuit 41.
The digital conversion circuit 41 of this embodiment includes the NOT gates U2, U17, U12, the NOT gates U4, U7, U10, U14 and the NOT gate U15, the input CS end of the NOT gate U17 is the chip select signal end, the input RW end of the NOT gate U12 is the read/write control signal end, the input MODE end of the NOT gate U2 is the MODE select signal end, the first input CLK end of the NOT gate U7 is the clock signal end, the output end of the NOT gate U2 is connected with the first input end of the NOT gate U4 through the NOT gate U3, the output end of the NOT gate U4 is connected with the input FE end of the double-controlled D trigger 42 through the NOT gates U5 and U6 in sequence, the output end of the NOT gate U7 is connected with the input CE end of the double-controlled D trigger 42 through the NOT gate U5 and U9 in sequence, the output end of the NOT gate U17 is connected with the second input end of the NOT gate U4, the output end of the NOT gate U12 is connected with the first input end of the NOT gate U10 through the NOT gate U11, the two output ends of the NOT gate U10 are connected with the first input end of the NOT gate U4, the output end of the NOT gate U14 and the output end of the two-controlled D trigger 42, the output end of the NOT gate U14 is connected with the output end of the NOT gate U4, the output end of the NOT gate 7 is connected with the output end of the NOT gate 3.
Since the resolver-to-digital converter of the present invention requires that the sixteen-bit digital signal be directly outputted in parallel or alternatively outputted in series, the converter defaults to parallel output in the case where the parallel/serial conversion circuit 4 does not operate. Under the normal power supply condition of the parallel-serial/conversion circuit, the CS chip selection signal, the RW read-write control signal, the MODE MODE selection signal, the CLK clock signal and the like are correctly controlled according to the control time sequence, and the converter realizes that sixteen-bit parallel data output by the data latch 3 are converted into serial data output sequentially from high bit to low bit. If the resolution of the converter is less than sixteen bits, the valid bit of the output serial data is the corresponding resolution and the high ends are aligned.
The invention has two power supply modes, and can realize the power supply of a single +5V power supply or a +/-5V power supply. When the chip selects a single +5V power supply to supply power, a built-in-5V inverter can replace a-5V direct current power supply, but the connection of pins of a power supply part of the chip needs to be changed.
The implementation method of the R/D converter with the excitation source and parallel/serial digital output in the embodiment is as follows:
s1: two paths of orthogonal signals with the effective value of 2.5Vrms and the frequency of 47 Hz-10 KHz generated by the excitation generating circuit 1 provide excitation signals for the rotary transformer, and the rotary transformer generates two paths of sin and cos signals which change along with the angle;
s2: the solid-state control transformer circuit 2 receives the sin and cos signals and the digital signals generated by the sixteen-bit reversible counting circuit, and performs difference solving on the sin and cos signals, and generates an error signal KEsin (theta-phi) through calculation and comparison of two-stage coarse division and one-stage fine division; the new digital angle is generated to approach the analog angle, the analog angle theta and the digital angle phi tend to be equal within the required precision range, and finally the digital angle phi of the reversible counter is equal to the input analog angle. Wherein: θ is the analog angle of the resolver output, K is the transformation ratio, and E is the amplitude of the reference voltage.
S3: the signal is amplified by an alternating current error amplifying circuit 5 to generate an error amplified signal NCI1, the error amplified signal NCI1 is input to a later stage, and the NCI1 enters a phase-sensitive demodulation circuit 7 and a TP2 fed back by a voltage-controlled oscillation circuit 11 to calculate to obtain a half-wave signal TP1;
s4: TP1 is calculated by a first integrating circuit 12 to obtain VEL direct current level, and VEL signals enter a sixteen-bit reversible counting circuit 8 for counting through a clock and a counting direction signal generated by a voltage-controlled oscillating circuit 11;
s5: the sixteen-bit digital output signal of the sixteen-bit reversible counting circuit 8 enters the data latch 3, and the sixteen-bit digital signal is latched and outputted in parallel through the data latch 3 to represent a digital angle;
s6: the parallel sixteen-bit digital signals are converted into sixteen-bit serial output digital signals through a parallel/serial conversion circuit.
The inner encoder 10 is an up/down shift counter that removes the ac error signal by adding or subtracting a least significant bit; the synthetic reference circuit 6 is used for eliminating errors between the internal signal and the reference, and the BIT signal generated by the synthetic reference circuit is used for testing and alarming the amplitude and phase difference of the internal sine and cosine input signal and the reference signal and the output signal 'TP 1' of the phase demodulator.
The above examples are only illustrative of the preferred embodiments of the present invention and are not intended to limit the scope of the present invention, and various modifications and improvements made by those skilled in the art to the technical solution of the present invention should fall within the scope of protection defined by the claims of the present invention without departing from the spirit of the present invention.

Claims (8)

1. An R/D converter with an excitation source and parallel/serial digital output, characterized in that: the device comprises an excitation generating circuit, a solid-state control transformer circuit, an alternating current error amplifying circuit, a phase-sensitive demodulation circuit, a synthetic reference circuit, a first integrating circuit, a voltage-controlled oscillating circuit, a sixteen-bit reversible counting circuit, a data latch and a parallel/serial conversion circuit;
the excitation generation circuit is connected with the rotary transformer and is used for providing external reference signals of the rotary transformer and the conversion circuit; the solid-state control transformer circuit is connected with the rotary transformer and is used for carrying out difference between sine and cosine input signals output by the rotary transformer and digital signals generated by the reversible counter to obtain error signals; the synthesis reference circuit is connected with the excitation generation circuit and is used for eliminating errors between internal signals and reference signals, and the BIT signals generated by the synthesis reference circuit are used for testing and alarming the amplitudes and the phase differences of internal sine and cosine input signals and reference signals and half-wave signals output by the voltage-controlled oscillation circuit;
the output end of the synthesis reference circuit is connected with the input end of the sixteen-bit reversible counting circuit through the phase-sensitive demodulation circuit; the input end of the alternating current error amplifying circuit is connected with the output end of the solid-state control transformer circuit, the output end of the alternating current error amplifying circuit is connected with the input end of the phase-sensitive demodulation circuit, and the alternating current error amplifying circuit is used for amplifying alternating current full-wave signals with gains of 1 and 4, and the amplified alternating current full-wave signals are converted into half-wave signals through the phase-sensitive demodulation circuit;
the output end of the phase-sensitive demodulation circuit is connected with the input end of the voltage-controlled oscillation circuit through the first integrating circuit; the output end of the voltage-controlled oscillation circuit is respectively connected with the phase-sensitive demodulation circuit and the sixteen-bit reversible counting circuit and is used for generating pulse signals with different frequencies according to the magnitude of the input direct-current error voltage; the parallel/serial conversion circuit is connected with the data latch and is used for converting parallel sixteen-bit digital signals output by the data latch into serial output;
the excitation generation circuit comprises a second integration circuit connected with the rotary transformer, the input end of the second integration circuit is connected with an anti-static protection circuit, the output end of the second integration circuit is connected with the input end of a third integration circuit through an inverting circuit, the output end of the anti-static protection circuit is connected with the input end of the third integration circuit, the input end of the third integration circuit is respectively connected with the output ends of a frequency stabilizing circuit and a amplitude stabilizing circuit, and the output ends of the second integration circuit, a power amplifying circuit and the output end of the third integration circuit are the output ends of the excitation generation circuit;
the second integrating circuit and the third integrating circuit respectively regulate signal frequency through external capacitors C1 and C2, and the capacitors C1 and C2 meet the following formulas:
wherein F is OSC Is the output frequency.
2. The R/D converter with excitation source and/or serial digital output according to claim 1, wherein: the solid-state control transformer circuit comprises a two-stage rough dividing circuit and a fine dividing circuit, wherein the input end of the first-stage rough dividing circuit is connected with the rotary transformer, the output end of the first-stage rough dividing circuit is connected with the input end of the fine dividing circuit through the second-stage rough dividing circuit, and the output end of the fine dividing circuit is the output end of the solid-state control transformer circuit.
3. The R/D converter with excitation source and/or serial digital output according to claim 1, wherein: the alternating current error amplifying circuit comprises an amplifier Q1 and a gating device N1, wherein a selection A1 end of the gating device N1 is grounded, the A0 end of the gating device N1 is connected with the output end of the amplifier Q1, the control end of the gating device N0 is connected with the sixteen-bit reversible counting circuit, the output end of the gating device is connected with the reverse input end of the amplifier Q1 through a capacitor C1, the non-inverting input end VO of the amplifier Q1 is connected with the solid-state control transformer circuit, the output end of the amplifier Q1 is connected with the phase-sensitive demodulation circuit, and the reverse input end of the amplifier Q1 is connected with the output end of the amplifier Q1 through a capacitor C2.
4. The R/D converter with excitation source and/or serial digital output according to claim 1, wherein: the phase-sensitive demodulation circuit comprises a gating device N2, N3, N4 and N5 and an amplifier Q2, wherein the selection O end of the gating device N2 is the input end of the phase-sensitive demodulation circuit, the output end of the gating device N2 is connected with the selection 1 end of the gating device N3, the selection 1 end of the gating device N3 is connected with the reverse input end of the amplifier Q2 through a resistor R1, the selection 0 end of the gating device N3 is connected with the output end of the amplifier Q2 through resistors R2 and R3 in sequence, the output end of the gating device N2 is connected with the output end of the amplifier Q2 through a resistor R3, the control end of the gating device N2 is connected with the control end of the gating device N4 through a NOT gate U1, the selection 0 end of the gating device N4 is connected with the selection 1 end of the gating device N4 and grounded, the output end of the gating device N4 is connected with the selection 1 end of the gating device N5 through a resistor R4 and the non-inverting input end of the amplifier Q2, and the selection 1 end of the gating device N5 is connected with the non-inverting input end of the amplifier Q2 through a resistor R6 and the non-inverting input end of the amplifier Q2 is grounded.
5. The R/D converter with excitation source and/or serial digital output according to claim 1, wherein: the voltage-controlled oscillating circuit comprises an amplifier Q3 and Q4, a capacitor C3 and a switch S1, wherein the inverting input end of the amplifier Q3 is connected with the first integrating circuit through a resistor R7, the output end of the amplifier Q3 is connected with the inverting input end of the amplifier Q4, the inverting input end of the amplifier Q3 is connected with the output end of the amplifier Q3 through the capacitor C3, the switch S1 is connected at two ends of the capacitor C3 in parallel, the non-inverting input end of the amplifier Q4 is a reference voltage end, and the output end of the amplifier Q4 is connected with the control end of the switch S1.
6. The R/D converter with excitation source and/or serial digital output according to claim 1, wherein: the parallel/serial conversion circuit comprises a plurality of double-control D flip-flops, wherein the input D ends of the double-control D flip-flops are used for receiving sixteen-bit parallel data output by the data latch, and the output ends of the double-control D flip-flops are converted into serial data sequentially output from high order to low order through the digital conversion circuit.
7. The R/D converter with excitation source and/or serial digital output of claim 6, wherein: the digital conversion circuit comprises NOT gates U2, U17 and U12, the input CS end of the NOT gate U17 is a chip selection signal end, the input RW end of the NOT gate U12 is a read-write control signal end, the input MODE end of the NOT gate U2 is a MODE selection signal end, the first input CLK end of the NOT gate U7 is a clock signal end, the output end of the NOT gate U2 is connected with the first input end of the NOT gate U4 through the NOT gate U3, the output end of the NOT gate U4 is connected with the input FE end of the double-control D trigger through the NOT gate U5 and U6 in sequence, the output end of the NOT gate U7 is connected with the input CE end of the double-control D trigger through the NOT gate U5 and U9 in sequence, the output end of the NOT gate U17 is connected with the second input end of the NOT gate U4, the output end of the NOT gate U12 is connected with the first input end of the NOT gate U10 through the NOT gate U11, the two output ends of the NOT gate U10 are respectively connected with the two input ends of the NOT gate U4 and the output end of the NOT gate U14 and the double-control D trigger, the NOT gate U14 and the output end of the NOT gate U14 is connected with the two output ends of the NOT gate U14 and the NOT gate U14.
8. The method for implementing an R/D converter with an excitation source and/or serial digital output according to claim 1, comprising the steps of:
(1) The excitation generation circuit outputs two paths of orthogonal signals to provide excitation signals for the rotary transformer, and the rotary transformer generates two paths of sin and cos signals which change along with the angle;
(2) The solid-state control transformer circuit receives the sin and cos signals and the digital signal generated by the sixteen-bit reversible counting circuit, and performs difference calculation and comparison on the sin and cos signals to obtain an error signal KEsin (theta-phi);
(3) The error signal KEsin (theta-phi) is amplified by an alternating current error amplifying circuit to obtain an error amplifying signal NCI1, and the error amplifying signal NCI1 is input to a later stage, and a half-wave signal TP1 is obtained by a phase-sensitive demodulation module and a voltage-controlled oscillation circuit;
(4) The half-wave signal TP1 is calculated by a first integrating circuit to obtain VEL direct current level, and pulse and counting direction signals generated by a voltage-controlled oscillating circuit enter a sixteen-bit reversible counting circuit to be counted;
(5) A sixteen-bit digital output signal of the sixteen-bit reversible counting circuit enters a data latch, and the sixteen-bit digital signal is latched and outputted in parallel through the data latch to represent a digital angle;
(6) The parallel sixteen-bit digital signals are converted into sixteen-bit serial output digital signals through a parallel/serial conversion circuit.
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