CN101281042A - High precision CMOS integrated circuit autosyn / rotary transformer - digital conversion technique - Google Patents

Abstract

The invention is a digital converting technology for high precise CMOS integrated circuit differential synchro/rotating transformer, characterized in that the technology processes the digital treatment for the differential synchro/rotating transformer signal, achieving the converting from the differential synchro/rotating transformer to the binary digital signal, which is composed of a solid control transformer circuit, a alternative current error amplifier circuit, a phase-sensitive demodulating circuit, an integral circuit, an synthesis reference circuit, a voltage control shaking circuit and a digital control circuit; the technology uses the standard CMOS integrated circuit technique of the single power source for integrating the circuit on the single chip. The technology of the invention has high precision and low energy consumption.

Description

High precision CMOS integrated circuit autosyn/rotary transformer-digital conversion technique

Technical field

The invention belongs to technical field of integrated circuits, particularly relate to a kind of high precision CMOS integrated circuit autosyn/rotary transformer-digital conversion technique.

Background technology

Selsyn is a kind of induction type electromechanical compo, is used for automatic control, transmits and calculate the answer system synchronously.It can be transformed to the corner of rotating shaft electric signal or electric signal is transformed to the corner of rotating shaft, realizes remote transmission, reception and the conversion of angle-data, reaches the purpose of automatic indication angle, position, distance and instruction.

Rotary transformer is the electromechanical compo that a kind of output voltage changes with angle of rotor.When field copper during with the alternating voltage excitation of certain frequency, the voltage of output winding is tied to form sine with the functional relationships of angle of rotor, cosine function concerns.It is mainly used in coordinate transform, triangulo operation and angle-data transmission.

Autosyn/rotary transformer is as shaft angle displacement measurement element, has measuring accuracy height, simple in structure, reliable, be mainly used in all very high environment of precision prescribed, reliability, compare with other angle measurement method, autosyn/rotary transformer is used for measurement of angle and has remarkable advantages.

1, on performance: because autosyn/rotary transformer inside has only two groups of coils, without any electronic component, so its vibration resistance, temperature tolerance, corrosion resistivity, anti-dust and aspects such as greasy dirt and anti-interference all have good performance, can adapt to the request for utilization of any environment, have high reliability.And photo-electric, raster pattern, magneto-electric angular transducer inner integrated treatment circuit and other electronic devices and components, it is vibrated, the influence of temperature, corrosive gas, dust and greasy dirt is bigger, and photo-electric also is subjected to the life-span influence of light source, and its interference free performance is also not as selsyn and rotary transformer.

2, from using: with the axis angle measurement system that autosyn/rotary transformer is formed, it is wide to have working range, can directly transmit the displacement information of 360 ° of angles of circumference, and need not mechanically contact when long-distance transmissions information.Installation dimension selects the space big, can have from diameter 20mm～200mm, and physical dimension is not subjected to the influence of resolution; Sensor and data processing section only need 5 or 6 lines, the trouble of removing 10～20 lines of other type coding device from.

Autosyn/rotary transformer is as the axis angle measurement element, for automatic control system provides low-cost, high-precision position transducer.In industrial detection control field, selsyn signal/signals of rotating transformer need be converted to digital signal is used for microprocessor or computing machine carries out data processing.At present, realize that the common D/A converter that adopts of autosyn/rotary transformer-digital conversion mode, operational amplifier, resistor network etc. separate the circuit that element is formed, the d. c. voltage signal that this mode realizes, system adopts split-type structural, need to use a large amount of resolution elements inevitably, often have following defective: volume is big, and element distributes and relatively disperses, can not realize the system element high-density installation, volume ratio is bigger.Poor reliability has been used a large amount of resolution elements, and integrated level is low, has reduced the reliability of system.

Summary of the invention

Technical matters to be solved by this invention is at the deficiencies in the prior art, and the CMOS that a kind of volume is little, precision is high, low in energy consumption is provided integrated circuit autosyn/rotary transformer-digital conversion technique.

Technical matters to be solved by this invention is to realize by above technical scheme.The present invention is a kind of high precision CMOS integrated circuit autosyn/rotary transformer-digital conversion technique, be characterized in, it carries out digitized processing to selsyn signal/signals of rotating transformer, realize of the conversion of selsyn signal/signals of rotating transformer to binary digital signal, it is made up of solid-state control transformer circuit, interchange error amplifying circuit, phase demodulation circuit, integrating circuit, synthesized reference circuit, Voltage-Controlled oscillation circuit and digital control circuit, and adopts integrated circuit technique that foregoing circuit is integrated on the single chip.

Technical scheme to be solved by this invention can further realize by following technical scheme.Above-described switch technology is characterized in, input amplifier A ₁, A ₂The signals of rotating transformer of the selsyn signal of three-way input or the input of four lines is converted to the cosine and sine signal V1 and the V2 of low-voltage, the digital angle φ that produces with up-down counter sues for peace in solid-state control transformer circuit, error signal KEsin of output after exchanging error amplifying circuit (θ-φ), the closed loop that this error signal is formed through phase demodulation circuit, integrating circuit, Voltage-Controlled oscillation circuit and digital control circuit is sought the sin (zero point of θ-φ); When this process was finished, the digital angle φ of digital control circuit equaled signal input shaft angle θ.Wherein: θ is the shaft angle of selsyn; K is a no-load voltage ratio; E is the amplitude of reference voltage; ω is a carrier frequency, i.e. the angular frequency of excitation voltage.

Technical scheme to be solved by this invention can further realize by following technical scheme.Above-described switch technology is characterized in, adopts switched capacitor technique in the solid-state control transformer circuit.

Technical scheme to be solved by this invention can further realize by following technical scheme.Above-described switch technology is characterized in, described solid-state control transformer circuit adopts two-stage rough segmentation and one-level sub-circuit, and first order rough segmentation circuit decomposes 0 °-11.25 ° with 0 °-360 ° of angle variable quantities; Rough segmentation circuit in the second level adopts the principle of linear segmented electric resistance partial pressure to decompose 0 °-0.703 °; Sub-circuit adopts the D/A converter of electric charge calibration, constitutes an analog multiplier.

Technical scheme to be solved by this invention can further realize by following technical scheme.Above-described switch technology is characterized in, exchanges error amplifying circuit and realizes that by amplifier and resistor network gain is 1 and 4 AC signal amplification; To exchange the all-wave conversion of signals through the phase demodulation circuit again and become half-wave voltage signal; Integrating circuit converts half-wave voltage signal to d. c. voltage signal by amplifier and resistance-capacitance network; Voltage-Controlled oscillation circuit adopts the charge balance equation voltage controlled oscillator, according to the size generation time clock of the direct-flow error voltage of importing; Digital control circuit is made up of up-down counter, data latching and logic control circuit, and it produces digital angle signal φ under the control of clock pulse signal.

Technical scheme to be solved by this invention can further realize by following technical scheme.Above-described switch technology is characterized in, the synthesized reference circuit by analog switching circuit and comparer will come from input amplifier just, cosine signal V ₁, V ₂Convert internal reference signal to, realize selecting automatically external reference and internal reference by the BIT signal; Described BIT signal is produced by the BIT signal deteching circuit, the system's measuring ability that realize that input signal is low excessively, low excessively, the inside and outside fixed phase difference of reference signal surpasses 45 ° and θ-φ＞100LSB.

The technology of the present invention adopts 3 μ m CMOS technologies, and chip size can be 5 * 6mm ², adopting switched capacitor network to substitute the conventional, electric-resistance technology and on CMOS technology, realize of the conversion of high-precision analog angle signal to digital signal, working temperature is-55 ℃-125 ℃.It has characteristics such as volume is little, precision is high, low in energy consumption.Vacation zero-bit conversion phenomena when adopting the synthesized reference circuit can eliminate angle to differ 180 °.The conversion accuracy of the technology of the present invention can reach 2.3 jiaos of branches; Its parallel data output and incremental code output resolution ratio can be selected; Synthesized reference is arranged, can avoid 180 ° of false zero-bits; Reference and signal phase shift can reach 45 °.Velocity voltage can be regulated by signal resistance, its maximum (top) speed correspondence ± 4V.

Below the technology of the present invention is carried out concrete analysis explanation.

1, solid-state control transformer circuit---the error analysis of closed loop.

Realize that aanalogvoltage form θ angle of representing (electrical angle) and the Φ angle (digital angle) that the binary digit form is represented subtract each other, and (error detector of θ-Φ) is also referred to as " solid-state control transformer " to exchange its difference of error voltage amplitude size expression.Solid-state control transformer is used for the error-detecting of tracking converter.With input quantity θ angle KESin θ Sin ω t (wherein 0 °≤θ＜360 °) and Φ angle, ask difference to obtain error signal KESin (θ-Φ) Sin ω t output.When | θ-Φ | in the time of≤0.0027 °, analog angle θ and digital angle Φ approximately equal in error range, loop is in steady state (SS); When | θ-Φ | in the time of＞0.0027 °, digital angle Φ will change, up to satisfying | and θ-Φ |≤0.0027 °.

Solid-state control transformer circuit adopts two-stage rough segmentation and one-level sub-circuit, and its circuit block diagram as shown in Figure 2.

(1) one-level rough segmentation circuit.Utilize trigonometric function and the difference formula and by operational amplifier to difference after scale factor compensate.One-level rough segmentation circuit rough segmentation to 11.25 °.Input signal is sin θ and cos θ, S+=sin θ then, S-=-sin θ, C+=cos θ, C-=-cos θ.QN1-QN16 is corresponding BIT1-BIT16 respectively, and ZN0-ZN14 is the logic control signal that is produced by QN1-QN5, and Z1-Z17 is the logic control signal that is produced by QN5-QN9, and S1-S13 is the logic control signal that QN1-QN16 produces.

1), as θ during at first quartile

And QN1=0

U1=-sin θ then, U2=cos θ=-sin (θ-90 °)

Then

Through U4=-sin (θ-45 °) after the amplification of operational amplifier.

Switch ZN1 closure when 0 °≤θ＜45 °

U5=-sin θ then

Then

Through U7=-sin (θ-22.5 °) after the amplification of operational amplifier.

ZN6 closure when 0 °≤θ＜22.5 °

U8=-sin θ then

Then

Then follow back U13=-cos11.25 ° of sin (θ-11.25 °) through operational amplifier.

Switch ZN11 closure when 0 °≤θ＜11.25 °

U10＝-sinθ

Through the electric resistance partial pressure heel with

Then

U13 and U14 enter the rough segmentation circuit of back subsequently.

2), when θ is positioned at second quadrant And QN1=0

Then U1=sin θ=-sin (θ-180 °), U2=cos θ=-sin (θ-90 °)

Then

Through U4=-sin (θ-135 °) after the amplification of operational amplifier.

Switch ZN3 closure when 90 °≤θ＜135 °

Then U5=cos θ=-sin (θ-90 °)

Then

Through U7=-sin (θ-112.5 °) after the amplification of operational amplifier.

ZN7 closure when 90 °≤θ＜112.5 °

Then U8=cos θ=-sin (θ-90 °)

Then

Then follow back U13=-cos11.25 ° of sin (θ-101.25 °) through operational amplifier.

Switch ZN10 closure when 90 °≤θ＜101.25 °

Then U10=cos θ=-sin (θ-90 °).

Through the electric resistance partial pressure heel with

Then

U13 and U14 enter the rough segmentation circuit of back subsequently.

3), when θ is positioned at third quadrant

And QN1=1

Then U1=sin θ=-sin (θ-180 °), U2=-cos θ=-sin (θ-270 °)

Then

Through U4=-sin (θ-225 °) after the amplification of operational amplifier.

Switch ZN0 closure when 180 °≤θ＜225 °

Then U5=sin θ=-sin (θ-180 °)

Then

Through U7=-sin (θ-202.5 °) after the amplification of operational amplifier.

ZN5 closure when 180 °≤θ＜202.5 °

Then U8=sin θ=-sin (θ-180 °)

Then

Then follow back U13=-cos11.25 ° of sin (θ-191.25 °) through operational amplifier.

Switch ZN14 closure when 180 °≤θ＜191.25 °

Then U10=sin θ=-sin (θ-180 °).

Through the electric resistance partial pressure heel with

Then

U13 and U14 enter the rough segmentation circuit of back subsequently.

4), when θ is positioned at four-quadrant

And QN1=1

Then U1=-sin θ=-sin (θ-360 °), U2=-cos θ=-sin (θ-270 °)

Then

Through U4=-sin (θ-315 °) after the amplification of operational amplifier.

Switch ZN2 closure when 270 °≤θ＜315 °

Then U5=-cos θ=-sin (θ-270 °)

Then

Through U7=-sin (θ-292.5 °) after the amplification of operational amplifier.

ZN8 closure when 270 °≤θ＜292.5 °

Then U8=-cos θ=-sin (θ-270 °)

Then

Then follow back U13=-cos11.25 ° of sin (θ-281.25 °) through operational amplifier.

Switch ZN9 closure when 270 °≤θ＜281.25 °

Then U10=-cos θ=-sin (θ-270 °).

Through the electric resistance partial pressure heel with

Then

U13 and U14 enter the rough segmentation circuit of back subsequently.

U13＝-cos11.25°sin[θ-(n×11.25°)]

Or U14=-cos11.25 ° of sin{ θ-[(n+1) * 11.25 °] } ... ... ... ... ... 2.

And: U13 * U14≤0

Wherein: U13＜U14 when when the even number of n=0,2,4,6.......30, adopting formula 1., when the odd number of n=1,3,5,7.......29, adopt formula 2. this moment U14＜U13.

That is: one of U13 and U14 are smaller or equal to 0 more than or equal to 0 another one, but can not equal 0 simultaneously.11.25 ° of every increases simultaneously, the sign of U13 and U14 is once exchanged.

(2) secondary rough segmentation circuit.

Adopt the principle of linear segmented electric resistance partial pressure to decompose to 0.703 °.Be similar to and think that the sin function is linear change at 0 °～11.25 °, then can carry out rough segmentation by 4 D/A that are made up of 16 substitutional resistances, least unit is 0.703 °.

The input signal of upper level:

U14＝-cos11.25°sin[θ-(n×11.25°)]

U13＝-cos11.25°sin{θ-[(n+1)×11.25°]}..............................①

U13＝-cos11.25°sin[θ-(n×11.25°)]

Or U14=-cos11.25 ° of sin{ θ-(n+1) * 11.25 °] } ... ... ... ... ... .. is 2.

When input signal is the gauge tap of following formula secondary rough segmentation 1. the time

Angular range: n * 11.25 °≤θ＜(n+1) * 11.25 °.(even number of n=0,2,4,6.......30 at this moment)

When input signal is the gauge tap of following formula secondary rough segmentation 2. the time

Angular range: n * 11.25 °≤θ＜(n+1) * 11.25 °.(this moment n=1,3,5,7.......29,31 odd number).

When input signal is the gauge tap of following formula secondary rough segmentation 1. the time

Angular range: n * 11.25 °≤θ＜(n+1) * 11.25 °.(even number of n=0,2,4,6.......30 at this moment)

Because circuit structure determines Z1 and links to each other with A8 to the Z17 even bit switch odd bits switch that links to each other with A7, and according to the pairing expression formula of first switch of switching sequence less than second pairing expression formula of switch.

The detailed segmentation of this moment and switch close:

Switch Z1 and Z2 closure when n * 11.25 °≤θ＜n * 11.25 °+0.703 °

A8=-cos11.25 ° of sin (θ-n * 11.25) then, A7=-cos11.25 ° of sin[θ-(n * 11.25+0.70 °)].

When n * 11.25 °+0.70 °≤θ＜n * 11.25+1.40 ° switch Z2 and Z3 closure

Then

A7=-cos11.25 ° of sin[θ-(n * 11.25+0.70 °)], A8=-cos11.25 ° of sin[θ-(n * 11.25+1.40 °)] ... ... and the like.

When n * 11.25 °+10.5 °≤θ＜n * 11.25+11.25 ° switch Z16 and Z17 closure

Then

A7＝-cos11.25°sin[θ-(n×11.25+10.5°)]，A8＝-cos11.25°sin[θ-(n×11.25+11.25°)]

When input signal is the gauge tap of following formula secondary rough segmentation 2. the time

Angular range: n * 11.25 °≤θ≤(n+1) * 11.25 °.(this moment n=1,3,5,7.......29,31 odd number).

The detailed segmentation of this moment and switch close:

N * 11.25 °≤θ＜n * 11.25 °+0.703 ° switch Z17 and Z16 closure at that time

A8=-cos11.25 ° of sin (θ-n * 11.25) then, A7=-cos11.25 ° of sin[θ-(n * 11.25+0.70 °)]

Switch Z16 and Z15 closure in the time of n * 11.25 °+0.70 °≤θ＜n * 11.25+1.40 °

A8=-cos11.25 ° of sin[θ-(n * 11.25+1.40 °) then], A7=-cos11.25 ° of sin[θ-(n * 11.25+0.70 °)] ... and the like.

When n * 11.25 °+10.5 °≤θ＜n * 11.25+11.25 ° switch Z2 and Z1 closure

A8=-cos11.25 ° of sin[θ-(n * 11.25+11.25 °) then], A7=-cos11.25 ° of sin[θ-(n * 11.25+10.5 °)]

Say that totally secondary rough segmentation circuit function is the same with the effect of one-level rough segmentation, export one positive one negative two signals and come to handle to late-class circuit.Here also can be with being similar to uniform expression that first order segmentation provides the secondary segmentation like that:

A8＝-cos11.25°sin(θ-m×0.703°)

A7＝-cos11.25°sin[θ-(m+1)0.703°].......................③

A7＝-cos11.25°sin(θ-m×0.703°)

Or A8=-cos11.25 ° of sin[θ-(m+1) 0.703 °] ... ... ... 4.

And: A8 * A7≤0

Wherein: A8＜A7 when when m=0,2,4,6.......508,510 even number, adopting formula 3., when m=1,3,5,7.......509,511 odd number, adopt formula 4. this moment A7＜A8.

That is: one of A8 and A7 are smaller or equal to 0 more than or equal to 0 another one, but can not equal 0 simultaneously.0.703 ° of every increase simultaneously, the sign of A7 and A8 is once exchanged.

Illustrate: the pass of the m here and the n of high-order segmentation is,

M/16=n is that m rounds divided by 16 and obtains n.

(3) sub-circuit.

Sub-circuit adopts the D/A converter of electric charge calibration, constitutes an analog multiplier, at this moment being input as of analog multiplier:

A8＝-cos11.25°sin(θ-m×0.703°)

A7＝-cos11.25°sin[θ-(m+1)×0.703°]........................③

A7＝-cos11.25°sin(θ-m×0.703°)

A8＝-cos11.25°sin[θ-(m+1)0.703°]...........................④

And: A8 * A7≤0

Wherein: A8＜A7 when when m=0,2,4,6.......508,510 even number, adopting formula 3.,

Or when m=1,3,5,7.......509,511 odd number, adopt formula 4. this moment A7＜A8

The effect of analog multiplier is: a series of switches of D/A are just formed wherein 0≤λ＜1 of a proportionality factors lambda and 1-λ

Thereby in ° scope of m * 0.703 °≤θ＜(m+1) * 0.703

Make: θ=λ * 0.703 °+m * 0.703 ° ... ... ... ... 5.

Simultaneously because:

Ue=A8* (1-λ)+A7* λ ... 6. when m=0,2,4,6.......508,510 even number

Ue=A7* (1-λ)+A8* φ ... ... ... 7. when m=1,3,5,7.......509,511 odd number

6. and 7. simultaneously in small angle range, utilize sinx ≈ x to obtain 5. substitution formula:

Ue＝A8*(1-λ)+A7*λ＝-cos11.25°[sin(λ×0.703°)×(1-λ)+sin(λ×0.703°-0.703°)×λ]

≈-cos11.25°[(λ×0.703°)×(1-λ)+(λ×0.703°-0.703°)×λ]＝0

Or

Ue＝A7*(1-λ)+A8*λ＝-cos11.25°[sin(λ×0.703°)×(1-λ)+sin(λ×0.703°-0.703°)×λ]

≈-cos11.25°[(λ×0.703°)×(1-λ)+(λ×0.703°-0.703°)×λ]＝0

So in arbitrarily angled m * 0.703 °≤θ＜(m+1) * 0.703 ° all exist a φ to make θ=λ * 0.703 °+m * 0.703 °, make Ue ≈ 0, the digital angle φ that can think λ, the m of two-stage rough segmentation and one-level sub-circuit and n (m/16=n be m round divided by 16 obtain n) representative in fact like this makes Ue ≈ 0.So the two-stage rough segmentation of solid-state control transformer circuit and one-level segmentation combine and can determine a digital angle φ ≈ θ.

Solid-state generally speaking control transformer circuit is exactly input analog angle θ and produces a signal that can characterize difference size between θ and the φ simultaneously by the computing that switch control is characterized between the digital angle φ: error voltage Ue=KEsin (the sin ω t of θ-φ), simultaneously by error voltage constantly drive subsequent conditioning circuit find make error voltage Ue=KEsin (the digital angle φ of sin ω t ≈ 0 of θ-φ), this moment φ ≈ θ.

2, exchange error amplifying circuit and phase demodulation circuit.

Exchange to amplify and use inverting amplifier to finish, its enlargement factor is controlled, and its circuit amplifies 4 times during K switch 1 ground connection as shown in Figure 3, is following state when not connecing.The phase demodulation circuit as shown in Figure 4, C2 can select enlargement factor 1 or 4 among Fig. 4, DM is the synthesized reference square wave.

3, clock source and BIT signal and synthesized reference circuit.

3.1, the clock source.

The technology of the present invention is owing to use the CMOS technology of digital circuit, thus in its circuit the main Sampling techniques of using with the simulating signal aftertreatment of sampling.There is a reference clock source (frequency of operation is generally 1.333MHz) its inside, and it is carried out 40 frequency divisions.For other parts provide reference clock.

3.2, BIT signal and detection thereof

BIT (build_in test) signal is the detection signal of internal circuit, and it is a digital signal, under normal circumstances is high, and when following 4 kinds of situations occurring, it becomes low:

A), whether the voltage of LOS (loss of signal) detection input signal is lower than 800mV.If 2 input signals (sin and cos) all are lower than 800mV, the BIT signal will step-down.Under normal angled rotation situation, SIN or COS signal always have one greater than this value, have only these 2 signals all to be lower than 800mV, and the BIT signal is just understood step-down.

B), phase error; When 180 ° of false zero-bits or reference and signal phase shift occurring above 45 °.

C), output data step; When output data changes above 100LSB, when promptly significant errors occurring in the error detecting system.

D), LOR (loss of reference) is when the reference-input signal amplitude is lower than 800mV.

As known from the above, BIT is important system's detection signal.

1), the BIT signal clock produces circuit

System provides the reference clock source, need offer the BIT signal deteching circuit according to producing clock with reference to the variation with signal.When detecting the BIT signal, change-over circuit should be in sample states, and the detection signal of this moment should be effective.Can reflect system state this moment during with reference to peak value, so time detection BIT signal gets final product with reference to peak value at each.

2), BIT signal deteching circuit

Circuit diagram is as shown in Figure 5: Fig. 5 is made up of four parts, and when one of them reported an error when this four part, the output of BIT signal became low, and normal condition BIT signal be a height always.

The reference amplitude testing circuit is as shown in Figure 6: K1, K3 are the high level conducting among Fig. 6, and K2, K4 are the low level conducting; Q2 is 40 times of reference clocks for Q2 among Fig. 2; VREF+ is 800mV.The appearance value of C2 is 5 times of C1.K switch 1, K2, K3, K4 make capacitor C 1 always be in charged state, and K switch 5, K6 periodically charge C1 to C2.Entire circuit periodically detects the reference signal energy, and the A point voltage is greater than VREF+ under the normal condition, and the reference amplitude detection signal is exported high level.When the reference signal amplitude was too small, the A point voltage reduces less than 800mV, and was low thereby comparer is output as, and the reference amplitude detection signal is low.

3.3, synthesized reference.

The synthesized reference circuit by analog switching circuit and comparer will come from input amplifier just, cosine signal V1, V2 convert internal reference signal to, realizes selecting automatically external reference and internal reference by the BIT signal; Described BIT signal is produced by the BIT signal deteching circuit, the system's measuring ability that realize that input signal is low excessively, low excessively, the inside and outside fixed phase difference of reference signal surpasses 45 ° and θ-φ＞100LSB.

4, voltage-controlled oscillator circuit.

Voltage controlled oscillator (VCO) is charge balance equation VCO, can produce time clock according to the size of the direct-flow error voltage of importing.Mainly contain to discharge and recharge partly and form with control section.

1), discharges and recharges part

Discharging and recharging mainly the electric capacity that is worth into the multiple relation by two appearances forms.Physical circuit block diagram such as Fig. 8.Wherein C1 is 50pF, and C2 is 25pF.V ± be ± 1.25V.False zero-bit detection signal has pulse to produce when false zero-bit takes place, and makes the VCO vibration, thereby has avoided false zero-bit phenomenon to take place.DIR is direction signal output, and CB provides clock for counter.

During charged state, the K1 closure, K2 disconnects, and K3 selects relevant with Ue polarity, and Ue selects V+ for timing K3, and K3 selected V-when Ue was negative, made capacitor C 2 precharge.Capacitor C 1 is charged according to velocity voltage Ue size, and the duration of charging is directly proportional with the Ue size.Resistance R v can regulate the duration of charging.

When capacitor C 1 charging voltage reaches preset value, enter discharge condition.Control circuit disconnects K1, the K2 closure, and K3 selects relevant with Ue polarity, and Ue selects V-for timing K3, and K3 selected V+ when Ue was negative, accelerated capacitor C 2 discharge and charging processes.The electric charge of capacitor C 1 can be extracted by capacitor C 2, accelerates discharge process.Voltage is lower than preset value on the capacitor C 1, and circuit enters charged state.Above process is finished entire circuit and is discharged and recharged.

Enter discharge process when Ue charging makes the voltage of C1 reach V-, the closed S2 of S1 this moment links to each other with V-, our hypothesis in the Δ t time above capacitor C 2 reach steady state (SS) (owing to the charging voltage of direct switch-capacitor C2, so the Δ t time is very little).

We can analyze down: in the Δ t time, the voltage on the C2 transforms to V-from V+, produces a great electric current, and what influence this electric current produces to capacitor C 1 simultaneously.

Because $I=\frac{Q}{\mathrm{\Δt}},$ And Q=C * Δ V,

Have for C2: Δ V ₂=(V-)-(V+)=-2V, C2=C,

The electric current that is produced is $I=\frac{{\mathrm{\&Delta;<figure-callout\; id="2"\; label="Q"\; filenames="A20081002344100261.png"\; state="\{\{state\}\}">Q</figure-callout>}}_2}{\mathrm{\&Delta;t}}=\frac{-2\mathrm{VC}}{\mathrm{\&Delta;t}},$

And this electric current must discharge to C1,

The electric charge that bleeds off in the Δ t time is Δ Q ₁=I Δ t=2VC

Because the electric charge on the C1 is: Q ₁=C ₁* V ₁=-2VC

Just in time the electric charge on the C1 is put totally, reached the function of discharge.

When Ue was the negative voltage charging, switch S 1 disconnected S2 and is connected with the V-signal, and this moment, C1 was by speed

Voltage U e charging, C2 is by the precharge of V-signal.

Discharge scenario can be with reference to similarly going up surface analysis.

2), control circuit

Control circuit is divided into two parts, control K1, K2 circuit and control K3 circuit.

Control K1, K2 circuit such as Fig. 9:

Clk is a reference clock among Fig. 9, and VCO_OUT is the output of VCO.V ± be ± 1.25V.False zero-bit detection signal can both change control signal S1, control VCO vibration.When false zero-bit detection signal was invalid, control circuit made during greater than V+ or less than V-width of S1 output be fixed as the pulse in 1 clk cycle at VCO_OUT, made VCO discharge and control discharge time.

The technology of the present invention performance index.

Autosyn/rotary transformer-digital conversion performance index are as shown in the table.

Description of drawings

Fig. 1 is autosyn/rotary transformer-digital conversion theory diagram.

Fig. 2 is solid-state control transformer block diagram.

Fig. 3 exchanges error amplifying circuit figure.

Fig. 4 is phase-sensitive circuit figure.

Fig. 5 is the BIT signal deteching circuit.

Fig. 6 is reference amplitude testing circuit figure.

Fig. 7 is that synthesized reference produces circuit.

Fig. 8 is the VCO circuit block diagram.

Fig. 9 is VCO control circuit figure.

Embodiment

Below further describe concrete technical scheme of the present invention,, and do not constitute restriction its right so that those skilled in the art understands the present invention further.

Embodiment 1.A kind of high precision CMOS integrated circuit autosyn/rotary transformer-digital conversion technique, it carries out digitized processing to selsyn signal/signals of rotating transformer, realize of the conversion of selsyn signal/signals of rotating transformer to binary digital signal, it is made up of solid-state control transformer circuit, interchange error amplifying circuit, phase demodulation circuit, integrating circuit, synthesized reference circuit, Voltage-Controlled oscillation circuit and digital control circuit, and adopts integrated circuit technique that foregoing circuit is integrated on the single chip.

Embodiment 2.In embodiment 1 described switch technology, input amplifier A ₁, A ₂The signals of rotating transformer of the selsyn signal of three-way input or the input of four lines is converted to the cosine and sine signal V1 and the V2 of low-voltage, the digital angle φ that produces with up-down counter sues for peace in solid-state control transformer circuit, error signal kEsin of output after exchanging error amplifying circuit (θ-φ), the closed loop that this error signal is formed through phase demodulation circuit, integrating circuit, Voltage-Controlled oscillation circuit and digital control circuit is sought the sin (zero point of θ-φ); When this process was finished, the digital angle φ of digital control circuit equaled signal input shaft angle θ.

Embodiment 3.In embodiment 1 described switch technology, adopt switched capacitor technique in the solid-state control transformer circuit.

Embodiment 4.In embodiment 1 described switch technology, described solid-state control transformer circuit adopts two-stage rough segmentation and one-level sub-circuit, and first order rough segmentation circuit decomposes 0 °-11.25 ° with 0 °-360 ° of angle variable quantities; Rough segmentation circuit in the second level adopts the principle of linear segmented electric resistance partial pressure to decompose 0 °-0.703 °; Sub-circuit adopts the D/A converter of electric charge calibration, constitutes an analog multiplier.

Embodiment 5.In embodiment 1 described switch technology, exchange error amplifying circuit and realize that by amplifier and resistor network gain is 1 and 4 AC signal amplification; To exchange the all-wave conversion of signals through the phase demodulation circuit again and become half-wave voltage signal; Integrating circuit converts half-wave voltage signal to d. c. voltage signal by amplifier and resistance-capacitance network; Voltage-Controlled oscillation circuit adopts the charge balance equation voltage controlled oscillator, according to the size generation time clock of the direct-flow error voltage of importing; Digital control circuit is made up of up-down counter, data latching and logic control circuit, and it produces digital angle signal φ under the control of clock pulse signal.

Embodiment 6.In embodiment 1 described switch technology, the synthesized reference circuit by analog switching circuit and comparer will come from input amplifier just, cosine signal V ₁, V ₂Convert internal reference signal to, realize selecting automatically external reference and internal reference by the BIT signal; Described BIT signal is produced by the BIT signal deteching circuit, the system's measuring ability that realize that input signal is low excessively, low excessively, the inside and outside fixed phase difference of reference signal surpasses 45 ° and θ-φ＞100LSB.

Claims (6)

1. high precision CMOS integrated circuit autosyn/rotary transformer-digital conversion technique, it is characterized in that, it carries out digitized processing to selsyn signal/signals of rotating transformer, realize of the conversion of selsyn signal/signals of rotating transformer to binary digital signal, it is made up of solid-state control transformer circuit, interchange error amplifying circuit, phase demodulation circuit, integrating circuit, synthesized reference circuit, Voltage-Controlled oscillation circuit and digital control circuit, and adopts integrated circuit technique that foregoing circuit is integrated on the single chip.

2. switch technology according to claim 1 is characterized in that, input amplifier A ₁, A ₂The signals of rotating transformer of the selsyn signal of three-way input or the input of four lines is converted to the cosine and sine signal V1 and the V2 of low-voltage, the digital angle φ that produces with up-down counter sues for peace in solid-state control transformer circuit, error signal kEsin of output after exchanging error amplifying circuit (θ-φ), the closed loop that this error signal is formed through phase demodulation circuit, integrating circuit, Voltage-Controlled oscillation circuit and digital control circuit is sought the sin (zero point of θ-φ); When this process was finished, the digital angle φ of digital control circuit equaled signal input shaft angle θ.

3. switch technology according to claim 1 is characterized in that, adopts switched capacitor technique in the solid-state control transformer circuit.

4. switch technology according to claim 1 is characterized in that, described solid-state control transformer circuit adopts two-stage rough segmentation and one-level sub-circuit, and first order rough segmentation circuit decomposes 0 °-11.25 ° with 0 °-360 ° of angle variable quantities; Rough segmentation circuit in the second level adopts the principle of linear segmented electric resistance partial pressure to decompose 0 °-0.703 °; Sub-circuit adopts the D/A converter of electric charge calibration, constitutes an analog multiplier.

5. switch technology according to claim 1 is characterized in that, exchanges error amplifying circuit and realizes that by amplifier and resistor network gain is 1 and 4 AC signal amplification; To exchange the all-wave conversion of signals through the phase demodulation circuit again and become half-wave voltage signal; Integrating circuit converts half-wave voltage signal to d. c. voltage signal by amplifier and resistance-capacitance network; Voltage-Controlled oscillation circuit adopts the charge balance equation voltage controlled oscillator, according to the size generation time clock of the direct-flow error voltage of importing; Digital control circuit is made up of up-down counter, data latching and logic control circuit, and it produces digital angle signal φ under the control of clock pulse signal.

6. switch technology according to claim 1 is characterized in that, the synthesized reference circuit by analog switching circuit and comparer will come from input amplifier just, cosine signal V ₁, V ₂Convert internal reference signal to, realize selecting automatically external reference and internal reference by the BIT signal; Described BIT signal is produced by the BIT signal deteching circuit, the system's measuring ability that realize that input signal is low excessively, low excessively, the inside and outside fixed phase difference of reference signal surpasses 45 ° and θ-φ＞100LSB.

Images