CN104135284A - Phase discrimination method and device as well as phase locking method and phase-locked loop - Google Patents
Phase discrimination method and device as well as phase locking method and phase-locked loop Download PDFInfo
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Abstract
The invention relates to a phase discrimination method and device as well as a phase locking method and a phase-locked loop. An input signal in the phase discrimination method is an analog signal, and a phase-locked loop output signal is a digital signal; the phase-locked loop output signal comprises a plurality of weights which correspond to angle elements in an angle data set; the weights at least comprise a first weight and a second weight which correspond to the angle elements of 180 degrees and 90 degrees; and the output signal is the sum of the angle elements which correspond to valid weights in the weights. The phase discrimination method comprises the following steps: selecting a first sine signal and a first cosine signal according to the first weight and the second weight; and performing addressing in a storage according to other weights, and outputting a sine signal which corresponds to a phase difference between the input signal and the phase-locked loop output signal. According to the method, the phase-locked loop output signal is converted into sinpsi and cospsi through addressing, and multiplication calculation and differential calculation are implemented through a circuit, so that phase discrimination through software calculation is avoided, and the phase discrimination speed is effectively increased.
Description
Technical field
The invention belongs to Phase Tracking technical field, especially a kind of phase detecting method of detection signal phase difference, device and system.
Background technology
Conventional measuring angle transducer has absolute grating encoder, Hall element and resolver.Absolute grating encoder directly becomes digital signal by rotating shaft angular transition, applies simple and conveniently, but is difficult to extensive use because the factors such as environmental suitability, price cause; Hall element is simple in structure, but is difficult to reach high accuracy angular surveying requirement and is restricted; Resolver because of reliable in structure, real-time is good, environmental suitability is strong etc., and advantage is widely used in high accuracy servo system.Resolver be at present the most accurately, the most reliable axle position simulates transducer, is widely used in the various control system such as Aeronautics and Astronautics, navigation, such as radar directed navigation, coordinate transform, fire control, machine tool control system etc.
Due to resolver output be a kind of ac modulation signal, in industrial control process, often signals of rotating transformer need to be converted to digital angle signal, then offer computer digit system and process.This conversion is the digital conversion circuit based on second order servo principle, and its core of lock ring phase tracking system is phase detector circuit.Traditionally, the signal that simulates of resolver output converts digital signal by sampling hold circuit to through A/D and by single-chip microcomputer (or DSP) circuit, carries out antitrigonometric function calculation process again and determine that the digital angle of shaft angle and output digital angle compare phase demodulation, this phase demodulation processing method, make resolution, the absolute precision of whole system all very low, especially tracking velocity is very low, cannot meet high-speed, high precision application scenario at all.Or resolver feedback signal is directly sent into analog to digital converter, the digital translation that realizes rotor position information by software demodulation algorithm compares phase demodulation with output digital angle, this Method And Principle is simple, but resolver is for guaranteeing the precision under certain measuring speed, its feedback frequency signal requires more than 20kHz, to the switching rate of analog to digital converter and software demodulation rate requirement higher (conventionally need at 1MHz), thereby cause device cost greatly to increase.
Summary of the invention
For the deficiencies in the prior art, the object of the present invention is to provide a kind of phase detecting method, device, and phase-lock technique and phase-locked loop, excessive to solve existing phase detecting method operand, react slower technological deficiency.
For this reason, the technical solution used in the present invention is as follows:
A kind of phase detecting method, input signal is analog signal, pll output signal is digital signal, described pll output signal comprises some power and positions, the described power and position angle element concentrated with an angle-data is corresponding, in described power and position, at least comprise first power and position and second power and position corresponding with the angle element of 180 ° and 90 °, described output signal is angle element sum corresponding to the effective power and position in described power and position;
Described phase detecting method comprises the following steps:
According to input signal, generate the first sinusoidal signal and first cosine signal of corresponding positive negative, according to described the first power and position and the second power and position, select positive or the first sinusoidal signal of negative and the first cosine signal of positive or negative;
According to the angle value of other power and position representatives except described the first power and position and the second power and position in the power and position of described output signal, in memory, carry out addressing, obtain second sinusoidal signal corresponding with described angle value and the second cosine signal;
The product of described the first sinusoidal signal and described the second cosine signal is deducted to the product of described the first cosine signal and described the second sinusoidal signal, export the sinusoidal signal that described input signal is corresponding with the phase difference of described pll output signal.
As a kind of preferred technical scheme, described angle value is 0 °～90 °.
As a kind of preferred technical scheme, described angle-data collection is that the first angle element is 180 °, the ordered series of numbers of half that a rear angle element is its last angle element.
As a kind of preferred technical scheme, the power and position of described output signal is 10～16, and its power and position is according to corresponding with the angle element in described ordered series of numbers respectively from high to low.
A phase-lock technique, input signal is analog signal, output signal is digital signal, comprising:
According to above-mentioned phase detecting method, obtain the sinusoidal signal that input signal is corresponding with the phase difference of output signal, generate the first M signal;
Described the first M signal is carried out to filtering, as control signal, enter voltage controlled oscillator;
The described output signal that described voltage controlled oscillator is identical with described input signal according to described control signal generated frequency.
A kind of phase demodulation apparatus, input signal is analog signal, pll output signal is digital signal, described pll output signal comprises some power and positions, the described power and position angle element concentrated with an angle-data is corresponding, in described power and position, at least comprise first power and position and second power and position corresponding with the angle element of 180 ° and 90 °, described output signal is angle element sum corresponding to the effective power and position in described power and position;
Described phase demodulation apparatus comprises input signal converter, switch selection circuit, the first processing module, the second processing module and difference channel;
Described switch selects the control end of circuit and the first power and position of described pll output signal to be connected with the second power and position
The output of described input signal converter selects the input of circuit to be connected with described switch, the output of described switching selector is connected with the second processing module with described the first processing module respectively, and the output of described the first processing module and the second processing module is connected with the input of described difference channel respectively;
Wherein, described the first processing module comprises the first multiplier, the first digital to analog converter and first memory, and the output of described switching selector is connected with an input of described the first multiplier; The address input end of described first memory is connected with the power and position beyond the second power and position with the first power and position of described pll output signal, and output is connected with the input of described the first digital to analog converter; The output of described the first digital to analog converter is connected with another input of described the first multiplier, and the output of described the first multiplier is connected with an input of described difference channel;
Described the second processing module comprises the second multiplier, the second digital to analog converter and second memory, and the output of described switching selector is connected with an input of described the second multiplier; The address input end of described second memory is connected with the power and position beyond the second power and position with the first power and position of pll output signal, and output is connected with the input of described the second digital to analog converter; The output of described the second digital to analog converter is connected with another input of described the second multiplier, and the output of described the second multiplier is connected with another input of described difference channel.
As a kind of preferred technical scheme,, described input signal converter comprises resolver, the first homophase device and the first inverter, and the second homophase device and the second inverter,
The sinusoidal output of described resolver is connected with the input of the first inverter with described the first homophase device respectively, and the output of described the first homophase device and the first inverter selects the input of circuit to be connected with described switch respectively;
The cosine output of described resolver is connected with the input of the second inverter with described the second homophase device respectively, and the output of described the second homophase device and the second inverter selects the input of circuit to be connected with described switch respectively.
As a kind of preferred technical scheme, also comprise output latch circuit, described the first power and position selects circuit to be connected with the second power and position by described output latch circuit and described switch.
As a kind of preferred technical scheme, described angle-data collection is that the first angle element is 180 °, the ordered series of numbers of half that a rear angle element is its last angle element; The power and position of described output signal is 8～16, and its power and position is according to corresponding with the angle element in described ordered series of numbers respectively from high to low.
A phase-locked loop, comprises the phase discriminator, low pass filter and the voltage controlled oscillator that connect successively, and wherein, described phase discriminator is above-mentioned phase demodulation apparatus, the output signal that described pll output signal is described voltage controlled oscillator.
Corresponding sine value and the cosine value of pll output signal that the technical scheme the present invention relates to is carried out addressing acquisition according to the numerical value of pll output signal carries out, after multiplication, exporting the phase difference of described input signal and pll output signal by difference channel.Because the value of the calculating pll output signal of amount of calculation maximum realizes by addressing, and multiplication calculates and Difference Calculation also realizes by circuit, has avoided the mode of calculating by software to carry out phase demodulation, has effectively improved phase demodulation speed.
Accompanying drawing explanation
Fig. 1 is the schematic diagram of pll output signal in a kind of phase detecting method one execution mode of the present invention;
Fig. 2 is the schematic diagram of phase discriminator in a kind of phase detecting method one execution mode of the present invention;
Fig. 3 is the schematic flow sheet of a kind of phase detecting method one execution mode of the present invention;
Fig. 4 is the schematic flow sheet of a kind of phase-lock technique one execution mode of the present invention;
Fig. 5 is the structural representation of a kind of phase demodulation apparatus one execution mode of the present invention;
Fig. 6 is the structural representation of a kind of phase-locked loop one execution mode of the present invention;
In figure:
10: input signal converter; 11: resolver; 12: the first homophase devices; 13: the first inverters; 14: the second homophase devices; 15: the second inverters; 20: switch is selected circuit; 30: the first processing modules; 31: the first digital to analog converters; 32: the first multipliers; 33: first memory; 40: the second processing modules; 41: the second digital to analog converters; 42: the second multipliers; 43: second memory; 50: difference channel.
Embodiment
Below in conjunction with accompanying drawing, the present invention will be further described.In order to overcome long defect of existing panoramic limit input simulation angle and the phase detecting method response time at the digital angle of output, the present invention adopts pll output signal from memory, to carry out addressing and realizes phase demodulation, this phase detecting method is not only simple, reliable, and noon greatly improves and reaches ms level at once.
Referring to Fig. 1, Fig. 1 is the schematic diagram of pll output signal in a kind of phase detecting method one execution mode of the present invention.In this phase detecting method, input signal is analog signal, and output signal is digital signal.As shown in Figure 1, described pll output signal comprises some power and positions, the described power and position angle element concentrated with an angle-data is corresponding, in described power and position, at least comprise first power and position and second power and position corresponding with the angle element of 180 ° and 90 °, described output signal is angle element sum corresponding to the effective power and position in described power and position.In some preferred implementations, described angle-data collection is that the first angle element is 180 °, the ordered series of numbers of half that a rear angle element is its last angle element, the power and position of described pll output signal is according to corresponding with the angle element in described ordered series of numbers respectively from high to low.Therefore, for thering is the pll output signal of n power and position, angle element a corresponding to i power and position from high to low
ifor:
If n power and position is high level (being expressed as 1) in this pll output signal, the numerical value S of this pll output signal is calculated as:
Visible, (be similar to infinite power and position) having under abundant power and position state, the pll output signal of this method for expressing is 360 °, the maximum of the numerical value of pll output signal is 360 °.
For example, one preferred embodiment in, this output signal represents by 16 power and positions, described angle-data collection is that the first angle element is 180 °, the ordered series of numbers of half that a rear angle element is its last angle element.The corresponding relation of each power and position and angle-data collection is as follows:
Therefore, for pll output signal value, be 1,001 1,010 1,101 0101 pll output signal, the numerical value of its expression is:
1*180°+0*90°+0*45°+1*22.5°+1*1.25°+0*5.625+1*2.8125°+0*1.40625°+1*0.703125°+1*0.3515625°+0*0.17578125°+1*0.087890625+0*0.0439453125°+1*0.02197265625°+0*0.02197265625°+1*0.010986328125°＝207.738°。
Obviously, power and position is more, and the precision of the pll output signal of expression is higher.Then, precision is higher, to also more in requisition for the data of processing, is preferably 8～16, such as 10,12,14,16 etc.In addition, according to the first power and position corresponding to 180 ° with corresponding to second power and position of 90 °, just can judge sine that this angle value is corresponding or the positive negative value of cosine signal, can be over 90 ° from height to the 3rd the low angle value to last bit representation thereby use.Concrete condition is as shown in the table:
| The first power and position and the second power and position value | Angular range | Place quadrant |
| 00 | 0～90° | First quartile |
| 01 | 90°～180° | The second quadrant |
| 10 | 180°～270° | Third quadrant |
| 11 | 270°～360° | Fourth quadrant |
Like this, can be according to the quadrant space at the place, phase angle of the value judgement pll output signal of the first power and position and the second power and position, utilize the value of other power and positions to calculate concrete phase value, thereby realize, the data processing of panoramic limit is transformed to the data processing in first quartile.
Referring to Fig. 2, Fig. 2 is the schematic diagram of phase discriminator in a kind of phase detecting method one execution mode of the present invention.In embodiments of the present invention, phase discriminator is to instigate the phase difference between output and two input signals to have definite relation, represents that the function of relation is called phase characteristic therebetween.The phase detecting method that utilizes the phase discriminator shown in Fig. 2 to carry out is to instigate phase difference between output and input signal and pll output signal to have the method for definite relation.In a preferred embodiment, definite relation of phase difference can represent by sine value corresponding to phase difference.
Referring to Fig. 3, Fig. 3 is the schematic flow sheet of a kind of phase detecting method one execution mode of the present invention.In the execution mode shown in Fig. 3, this phase detecting method comprises:
Step S301: generate the first sinusoidal signal and first cosine signal of corresponding positive negative according to input signal, select the first sinusoidal signal and the first cosine signal according to described the first power and position and the second power and position;
Step S302: carry out addressing according to the angle value of other power and position representatives except described the first power and position and the second power and position in the power and position of described output signal in memory, obtain second sinusoidal signal corresponding with described angle value and the second cosine signal;
Step S303: the product of described the first sinusoidal signal and described the second cosine signal is deducted to the product of described the first cosine signal and described the second sinusoidal signal, export the sinusoidal signal that described input signal is corresponding with the phase difference of described pll output signal.
For example, in some embodiments, input signal is the angle signal of simulation, and input simulation angle θ can be transformed into the first sinusoidal signal (sin θ) and the first cosine signal (cos θ) through sensor rotation transformer and utilize homophase device and inverter to generate the first positive and negative sinusoidal signal (sin θ or-sin θ) and the first cosine signal (cos θ or-cos θ).Wherein, the first sinusoidal signal and the first cosine signal are analog signal.Then, according to the quadrant at the first power and position of pll output signal and the second power and position judgement input simulation angle.If in first quartile, select the first positive sinusoidal signal and the first positive cosine signal; If in the second quadrant, select the first negative sinusoidal signal and the first positive cosine signal; If in third quadrant, select the first negative sinusoidal signal and the first negative cosine signal; If in fourth quadrant, select the first positive sinusoidal signal and the first negative cosine signal.
After this, according to other power and positions of pll output signal, in memory, carry out addressing, the angle value that other power and positions of pll output signal of for example take calculate carries out addressing at memory to sine value corresponding to this angle value and cosine value as address, obtains corresponding the second cosine signal (cos ψ) and the second sinusoidal signal (sin ψ) of pll output signal.Visible, owing to having carried out quadrant judgement by the first power and position value and the second power and position value,, the angle value in only needing 0～90 ° in this addressing process carries out addressing, addressing range is effectively reduced, and the requirement of corresponding memory space also can greatly reduce.
Finally, the first sinusoidal signal (sin θ or-sin θ) the second cosine signal (cos ψ) is delivered to the input of a multiplier, generate the product (sin θ * cos ψ or-sin θ * cos ψ) of described the first sinusoidal signal and described the second cosine signal, and first cosine signal (cos θ or-cos θ) the second sinusoidal signal (sin ψ) delivers to the input of a multiplier, generate the product (cos θ * sin ψ or-cos θ * sin ψ) of described the first cosine signal (cos θ) the second sinusoidal signal (sin ψ).After two products are subtracted each other, export described input signal and described pll output signal phase difference sin (θ-ψ) or-sin (θ-ψ):
sin(θ－ψ)＝sinθ*cosψ-cosθ*sinψ
Referring to Fig. 4, Fig. 4 is the schematic flow sheet of a kind of phase-lock technique one execution mode of the present invention.In the execution mode shown in Fig. 4, this phase-lock technique comprises the following steps:
Step S401: obtain the phase difference of input signal and output signal according to the phase detecting method described in above-mentioned arbitrary execution mode, generate the first M signal;
Step S402: described the first M signal is carried out to filtering, enter voltage controlled oscillator as control signal;
Step S403: the described output signal that described voltage controlled oscillator is identical with described input signal according to described control signal generated frequency.
In the phase-lock technique shown in Fig. 4, because needs feed back phase discriminator by output signal, therefore, the pll output signal that above-mentioned execution mode relates to is the output signal in present embodiment.
Referring to Fig. 5, Fig. 5 is the structural representation of a kind of phase demodulation apparatus one execution mode of the present invention.In the execution mode shown in Fig. 5, the phase detecting method that this phase demodulation apparatus adopts is corresponding with the execution mode shown in Fig. 3, and its input signal is analog signal, and pll output signal is digital signal.
This phase demodulation apparatus comprises input signal converter 10, switch selection circuit 20, the first processing module 30, the second processing module 40 and difference channel 50.Described switch selects the control end of circuit 20 and the first power and position of described pll output signal to be connected with the second power and position, also comprises output latch circuit, and described the first power and position selects circuit 20 to be connected with the second power and position by described output latch circuit and described switch.
The output of described input signal converter 10 selects the input of circuit 20 to be connected with described switch, the output of described switching selector is connected with the second processing module 40 with described the first processing module 30 respectively, and the output of described the first processing module 30 and the second processing module 40 is connected with the input of described difference channel 50 respectively.
Wherein, described the first processing module 30 comprises the first multiplier 32, the first digital to analog converter 31 and first memory 33, and the output of described switching selector is connected with an input of described the first multiplier 32; The address input end of described first memory 33 is connected with the power and position beyond the second power and position with the first power and position of described pll output signal, and output is connected with the input of described the first digital to analog converter 31; The output of described the first digital to analog converter 31 is connected with another input of described the first multiplier 32, and the output of described the first multiplier 32 is connected with an input of described difference channel 50.
Described the second processing module 40 comprises the second multiplier 42, the second digital to analog converter 41 and second memory 43, and the output of described switching selector is connected with an input of described the second multiplier 42; The address input end of described second memory 43 is connected with the power and position beyond the second power and position with the first power and position of pll output signal, and output is connected with the input of described the second digital to analog converter 41; The output of described the second digital to analog converter 41 is connected with another input of described the second multiplier 42, and the output of described the second multiplier 42 is connected with another input of described difference channel 50.
Some preferred embodiment in, described input signal converter 10 comprises resolver 11, the first homophase device 12 and the first inverter 13, and the second homophase device 14 and the second inverter 15,
The sinusoidal output of described resolver 11 is connected with the input of the first inverter 13 with described the first homophase device 12 respectively, and the output of described the first homophase device 12 and the first inverter 13 selects the input of circuit 20 to be connected with described switch respectively; The cosine output of described resolver 11 is connected with the input of the second inverter 15 with described the second homophase device 14 respectively, and the output of described the second homophase device 14 and the second inverter 15 selects the input of circuit 20 to be connected with described switch respectively.
In this embodiment, the simulation angle θ of input is transformed into the first sinusoidal signal (sin θ) and the first cosine signal (cos θ) through resolver 11.The first sinusoidal signal (sin θ) enters the first homophase device 12 and positive and negative the first sinusoidal signal of the first inverter 13 output (+sin θ and-sin θ) through sinusoidal output; The first cosine signal (cos θ) is exported the first positive and negative cosine signal (+cos θ and-cos θ) after cosine output is by the second homophase device 14 and the second inverter 15.The first positive and negative sinusoidal signal (+sin θ and-sin θ) and positive and negative the first cosine signal (+cos θ and-cos θ) enter in switch selection circuit 20 and select.Wherein, switch selects circuit 20 to control by the first power and position and second power and position of pll output signal, and concrete control method have been described in detail in phase detecting method part, repeats no more herein.The first sinusoidal signal after selecting (sin θ or-sin θ) and the first cosine signal (cos θ or-cos θ) are sent to respectively an input of the first multiplier 32 and the second multiplier 42.
In addition on the one hand, other power and positions of pll output signal are connected with the address input end of second memory 43 with first memory 33 respectively, utilize the angle value that other power and positions represent in first memory 33, sine value corresponding to this angle value to be carried out to addressing as address, in second memory 43, cosine value corresponding to this angle value carried out to addressing.The cosine value that in the sine value that in first memory 33, addressing obtains and second memory 43, addressing obtains enters respectively after the first analog to digital converter and the conversion of the second analog to digital converter, obtains second sinusoidal signal (sin ψ) of corresponding simulation and second cosine signal (cos ψ) of simulation.
The second cosine signal that addressing obtains (cos ψ) and the first sinusoidal signal (sin θ or-sin θ) send into together the first multiplier 32 carry out multiplication operations obtain sin θ cos ψ or-sin θ cos ψ; The second sinusoidal signal that addressing obtains (sin ψ) and the first cosine signal (cos θ or-cos θ) send into together the second multiplier 42 carry out multiplication operations obtain sin ψ cos θ or-sin ψ cos θ.The signals that above-mentioned two multiply each other after processing deliver to again difference channel 50 output phase difference signal sin (θ-ψ) or-sin (θ-ψ).Some preferred embodiment in, also comprise signal amplification circuit, the input of described signal amplification circuit is connected with the output of described difference channel 50.
Above-mentioned preferred embodiment in, the first multiplier 32 and the first digital to analog converter 31 can be same chips, the second multiplier 42 and the second digital to analog converter 41 can be also same chips, for example multiplication type digital to analog converter has just comprised multiplier and digital to analog converter, the core of whole circuit, identical in structure.Sinusoidal (cosine) functional value of all angles within the scope of storage 0o～90o in first memory 33 (second memory 43), each angle memory cell carries out addressing by the output of forward-backward counter.Some preferred embodiment in, can adopt 14 figure place weighted-voltage D/A converters and 14 s' multiplier, the response time reaches ms level.10,12,14,16 of this phase discriminator system compatibles input simulation angles and the digital angular phasing comparison of output, this phase detector circuit TTL, with COMS circuit compatibility.
Referring to Fig. 6, Fig. 6 is the structural representation of a kind of phase-locked loop one execution mode of the present invention.In the execution mode shown in Fig. 6, the phase-locked loop of this structure comprises phase discriminator, low pass filter and the voltage controlled oscillator connecting successively, wherein, described phase discriminator is the phase demodulation apparatus that above-mentioned execution mode relates to, the output signal that described pll output signal is described voltage controlled oscillator.Wherein, the phase discriminator in phase-locked loop is called again phase comparator, and its effect is the phase difference detecting between input signal, and converts detected phase signal to voltage signal output, and phase discriminator is one of basic element of character of phase-locked loop.
From above-mentioned some execution modes, can find out, the present invention carries out addressing according to the numerical value of output signal and obtains corresponding sine value and cosine value.Because the value of the calculating pll output signal of amount of calculation maximum realizes by addressing, and multiplication calculates and Difference Calculation also realizes by circuit, has avoided the mode of calculating by software to carry out phase demodulation, has effectively improved phase demodulation speed.
And, the present invention is by corresponding by the power and position of the pll output signal angle element concentrated with angle-data, utilize the quadrant of the first power and position and the second power and position judgement pll output signal, make the addressing range of panoramic limit only change into and need in first quartile, carry out addressing, effectively reduce addressing range, improved addressing efficiency.
Should be appreciated that, the present invention is not limited to above-mentioned execution mode, every various changes of the present invention or modification are not departed to the spirit and scope of the present invention, if these are changed and within modification belongs to claim of the present invention and equivalent technologies scope, the present invention also means and comprises these changes and modification.
Claims (10)
1. a phase detecting method, input signal is analog signal, pll output signal is digital signal, it is characterized in that, described pll output signal is represented by some power and positions, described power and position is corresponding with the angle element of an angle-data collection, at least comprises first power and position and second power and position corresponding with the angle element of 180 ° and 90 ° in described power and position, and the numerical value of described output signal is angle element sum corresponding to the effective power and position in described power and position;
Described phase detecting method comprises the following steps:
According to input signal, generate the first sinusoidal signal and first cosine signal of corresponding positive negative, according to described the first power and position and the second power and position, select positive or the first sinusoidal signal of negative and the first cosine signal of positive or negative;
According to the angle value of other power and position representatives except described the first power and position and the second power and position in the power and position of described output signal, in memory, carry out addressing, obtain second sinusoidal signal corresponding with described angle value and the second cosine signal;
The product of described the first sinusoidal signal and described the second cosine signal is deducted to the product of described the first cosine signal and described the second sinusoidal signal, export the sinusoidal signal that described input signal is corresponding with the phase difference of described pll output signal.
2. phase detecting method as claimed in claim 1, is characterized in that, described angle value is 0 °～90 °.
3. phase detecting method as claimed in claim 1 or 2, is characterized in that, described angle-data collection is that the first angle element is 180 °, the ordered series of numbers of half that a rear angle element is its last angle element.
4. phase detecting method as claimed in claim 3, is characterized in that, the power and position of described output signal is 10～16, and its power and position is according to corresponding with the angle element in described ordered series of numbers respectively from high to low.
5. a phase-lock technique, input signal is analog signal, output signal is digital signal, it is characterized in that, comprising:
According to the phase detecting method described in claim 1-4 any one, obtain the sinusoidal signal that input signal is corresponding with the phase difference of output signal, generate the first M signal;
Described the first M signal is carried out to filtering, as control signal, enter voltage controlled oscillator;
The described output signal that described voltage controlled oscillator is identical with described input signal according to described control signal generated frequency.
6. a phase demodulation apparatus, input signal is analog signal, pll output signal is digital signal, it is characterized in that, described pll output signal is represented by some power and positions, the described power and position angle element concentrated with an angle-data is corresponding, at least comprises first power and position and second power and position corresponding with the angle element of 180 ° and 90 ° in described power and position, and described output signal is angle element sum corresponding to the effective power and position in described power and position;
Described phase demodulation apparatus comprises input signal converter, switch selection circuit, the first processing module, the second processing module and difference channel;
Described switch selects the control end of circuit and the first power and position of described pll output signal to be connected with the second power and position;
The output of described input signal converter selects the input of circuit to be connected with described switch, the output of described switching selector is connected with the second processing module with described the first processing module respectively, and the output of described the first processing module and the second processing module is connected with the input of described difference channel respectively;
Wherein, described the first processing module comprises the first multiplier, the first digital to analog converter and first memory, and the output of described switching selector is connected with an input of described the first multiplier; The address input end of described first memory is connected with the power and position beyond the second power and position with the first power and position of described pll output signal, and output is connected with the input of described the first digital to analog converter; The output of described the first digital to analog converter is connected with another input of described the first multiplier, and the output of described the first multiplier is connected with an input of described difference channel;
Described the second processing module comprises the second multiplier, the second digital to analog converter and second memory, and the output of described switching selector is connected with an input of described the second multiplier; The address input end of described second memory is connected with the power and position beyond the second power and position with the first power and position of pll output signal, and output is connected with the input of described the second digital to analog converter; The output of described the second digital to analog converter is connected with another input of described the second multiplier, and the output of described the second multiplier is connected with another input of described difference channel.
7. a kind of phase demodulation apparatus as claimed in claim 6, is characterized in that, described input signal converter comprises resolver, the first homophase device and the first inverter, and the second homophase device and the second inverter,
The sinusoidal output of described resolver is connected with the input of the first inverter with described the first homophase device respectively, and the output of described the first homophase device and the first inverter selects the input of circuit to be connected with described switch respectively;
The cosine output of described resolver is connected with the input of the second inverter with described the second homophase device respectively, and the output of described the second homophase device and the second inverter selects the input of circuit to be connected with described switch respectively.
8. a kind of phase demodulation apparatus as claimed in claim 7, is characterized in that, also comprises output latch circuit, and described the first power and position selects circuit to be connected with the second power and position by described output latch circuit and described switch.
9. a kind of phase demodulation apparatus as claimed in claim 8, is characterized in that, described angle-data collection is that the first angle element is 180 °, the ordered series of numbers of half that a rear angle element is its last angle element; The power and position of described output signal is 10～16, and its power and position is according to corresponding with the angle element in described ordered series of numbers respectively from high to low.
10. a phase-locked loop, comprise the phase discriminator, low pass filter and the voltage controlled oscillator that connect successively, it is characterized in that, described phase discriminator is the phase demodulation apparatus described in claim 6-9 any one, the output signal that described pll output signal is described voltage controlled oscillator.
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