CN106952942A - A kind of Schottky diode of p-type polysilicon groove structure and preparation method thereof - Google Patents
A kind of Schottky diode of p-type polysilicon groove structure and preparation method thereof Download PDFInfo
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- CN106952942A CN106952942A CN201710235233.3A CN201710235233A CN106952942A CN 106952942 A CN106952942 A CN 106952942A CN 201710235233 A CN201710235233 A CN 201710235233A CN 106952942 A CN106952942 A CN 106952942A
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 72
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 66
- 238000002360 preparation method Methods 0.000 title claims description 9
- 239000013049 sediment Substances 0.000 claims abstract description 4
- 238000000407 epitaxy Methods 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 16
- 229910052751 metal Inorganic materials 0.000 claims description 16
- 239000012535 impurity Substances 0.000 claims description 13
- 230000004888 barrier function Effects 0.000 claims description 10
- 238000005530 etching Methods 0.000 claims description 9
- 238000000151 deposition Methods 0.000 claims description 8
- 238000002513 implantation Methods 0.000 claims description 7
- 239000000758 substrate Substances 0.000 claims description 5
- 230000001413 cellular effect Effects 0.000 claims description 4
- 238000000605 extraction Methods 0.000 claims description 4
- 238000000034 method Methods 0.000 claims description 4
- 238000002347 injection Methods 0.000 claims description 3
- 239000007924 injection Substances 0.000 claims description 3
- 239000012774 insulation material Substances 0.000 claims description 3
- 230000000717 retained effect Effects 0.000 claims description 3
- 238000009413 insulation Methods 0.000 claims 1
- 230000015556 catabolic process Effects 0.000 abstract description 17
- 230000000694 effects Effects 0.000 abstract description 3
- 238000011049 filling Methods 0.000 abstract description 3
- 230000009467 reduction Effects 0.000 abstract description 3
- 230000000873 masking effect Effects 0.000 description 8
- 239000004065 semiconductor Substances 0.000 description 6
- 230000008021 deposition Effects 0.000 description 4
- 239000002019 doping agent Substances 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 230000005684 electric field Effects 0.000 description 3
- 229910044991 metal oxide Inorganic materials 0.000 description 3
- 150000004706 metal oxides Chemical class 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 230000006872 improvement Effects 0.000 description 2
- 238000001459 lithography Methods 0.000 description 2
- 230000008569 process Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000000686 essence Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/872—Schottky diodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/04—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
- H01L29/0607—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration
- H01L29/0611—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices
- H01L29/0615—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE]
- H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
- H01L29/0623—Buried supplementary region, e.g. buried guard ring
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/167—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System further characterised by the doping material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
- H01L29/66143—Schottky diodes
Abstract
The invention discloses a kind of p-type polysilicon trench schottky diode, the trench interiors are formed sediment by polysilicon sets full, and the polysilicon is p-type DOPOS doped polycrystalline silicon.The present invention substitutes the oxide layer and the filling mode of N-type polycrystalline silicon inside traditional trench schottky structured channel with p-type polysilicon, reaches the purpose of cut-in voltage under reduction high current, by adjusting polysilicon doping concentration, can reach the effect for improving breakdown voltage.
Description
Technical field
The present invention relates to semiconductor applications, more precisely a kind of Schottky diode of p-type polysilicon groove structure.
Background technology
Schottky diode occupies one with its good forward conduction characteristic and high-speed switch speed in power device field
The ground of seat, but be due to use metal-semiconductor contact on itself makes, it is reversely pressure-resistant out of condition.In the prior art,
Electric field has been focused on channel bottom by the Schottky diode of groove type metal oxide semiconductor structure, improves other positions
The voltage dividing ability of depletion region, effectively raises the breakdown reverse voltage of device, and the forward conduction under high-voltage great-current is electric
Pressure is not but very good.On the premise of other specification is not influenceed, improve the forward direction under Schottky diode high-voltage great-current
Conducting voltage has highly important meaning.Cut-in voltage mistake of the existing trench schottky structure devices under high-voltage great-current
Greatly, still there are many improvement spaces.
The content of the invention
It is an object of the invention to provide a kind of Schottky diode of p-type polysilicon groove structure and preparation method thereof, its
It can realize in trench schottky diode, groove type metal oxide semiconductor knot is replaced with the structure of plough groove type PN junction
Structure, and in the case where not changing epitaxial conditions, the mesh of forward conduction voltage of the device under high current and high temperature can be reduced
, while breakdown reverse voltage can also be improved further.
The present invention uses following technical scheme：
A kind of p-type polysilicon trench schottky diode, including some grooves, the trench interiors are formed sediment by polysilicon to be set
It is full, and the polysilicon is p-type DOPOS doped polycrystalline silicon.
The groove is in N-type epitaxy layer.
The N-type epitaxy layer is not provided with the side of groove on N-type substrate.
In the side deposition insulating layer of N-type epitaxy layer, and the insulating barrier be deposited in N-type epitaxy layer and groove top
Portion, forms termination environment.
The deposited metal above the non-deposition insulating layer part of N-type epitaxy layer and insulating barrier, forms anode.
A kind of preparation method for preparing p-type polysilicon trench schottky diode, comprises the following steps：
The depositing polysilicon in groove, first deposit layer polysilicon, implanting p-type impurity, regulation implantation dosage and
Implantation Energy, polysilicon surface is injected into by impurity；
The second polysilicon is deposited, trench fill is expired, and is annealed, impurity concentration inside polysilicon is uniformly distributed.
It is further comprising the steps of：Insulating barrier is deposited, and is removed cellular region surface insulation material, is only retained in termination environment.
Deposited metal, and perform etching, anneal, extraction electrode is formed as the anode of device, and this metal level is by multilayer
Metal level is constituted.
It is an advantage of the invention that：By filling out for the oxide layer inside traditional trench schottky structured channel and N-type polycrystalline silicon
Fill mode to be substituted with p-type polysilicon, reach the purpose of cut-in voltage under reduction high current, by adjusting polysilicon doping concentration,
The effect for improving breakdown voltage can be reached.
Brief description of the drawings
With reference to embodiment and accompanying drawing, the present invention is described in detail, wherein：
Fig. 1 is the structural representation of the present invention.
Fig. 2 to Fig. 8 is the structure chart of the preparation method intermediate structure of the present invention.
Fig. 9 is emulation log curve map of the diode with prior art breakdown reverse voltage of invention.
The diode that Figure 10 is the present invention is compared figure with prior art cut-in voltage.
Embodiment
The embodiment of the present invention is expanded on further below in conjunction with the accompanying drawings：
As shown in figure 1, the invention discloses a kind of Schottky diode of p-type polysilicon groove structure, if including hondo
Groove 23, and the trench interiors of the groove 23 set full by the shallow lake of polysilicon 40, and the polysilicon 40 is p-type DOPOS doped polycrystalline silicon.
The present invention is filled outside polysilicon and N-type doped with p type impurity in the trench based on trench schottky technique
Prolong layer formation PN junction structure.When device forward direction works, when applying less operating voltage, the Xiao Te with compared with low turn-on voltage
Base junction is first turned on, and with alive increase is applied, PN junction also begins to conducting, and starts as a large amount of electronics, reduction are injected in drift region
Conducting resistance in drift region, reduces its forward conduction voltage under high current working condition.
In the trench schottky structure of the present invention, the polysilicon adulterated with p-type substitutes original gate oxide and n-type doping
Polysilicon, reduces the cut-in voltage under device high-voltage great-current, while improving breakdown reverse voltage.
Under with a epitaxial conditions, with the increase of p-type polysilicon doping concentration in groove, breakdown voltage is in first to rise
Downward trend afterwards.Reason is that p-type polysilicon contacts to form a PN junction, during device reverse operation, this PN junction with N-type epitaxy layer
Together with overlapping with the depletion layer of the schottky junction on surface, play a part of sharing surface field.When p-type polysilicon doping concentration
When too high or too low, i.e., p-type polysilicon dopant concentration is mismatched with extension concentration, and PN junction punctures in advance, has dragged down whole device
The breakdown voltage of part.When p-type polysilicon dopant concentration is matched with epitaxial layer concentration, the electricity at the place of surface schottky junction can be reduced
, so that the breakdown voltage of boost device.
Script is filled in by the present invention on the basis of the Schottky diode of groove type metal oxide semiconductor structure
Gate oxide and N-type polycrystalline silicon in groove are substituted with p-type polysilicon, reduce the cut-in voltage under high current, while
The further breakdown reverse voltage for improving device.
Groove 23 is in N-type epitaxy layer 20.The side that the N-type epitaxy layer 20 is not provided with groove is located at N-type substrate 10
On.
In the side deposition insulating layer 50 of N-type epitaxy layer 20, and the insulating barrier is deposited in N-type epitaxy layer 20 and groove
Top, formed termination environment.The deposited metal 60 above the non-deposition insulating layer part of N-type epitaxy layer 20 and insulating barrier, is formed
Anode.
The terminal structure of the present invention extends to be formed using the groove of multiple filling p-type polysilicons to chip edge, terminal ditch
Groove and cellular groove make simultaneously, this structure can effectively reduce the distribution of active area electric field, so that boost device is hit
Wear voltage.Spacing, width can be set according to the pressure-resistant demand of device between groove.
The invention also discloses the preparation method of the Schottky diode of p-type polysilicon groove structure, comprise the following steps：
Grown as shown in Fig. 2 carrying out extension 20 on N-type substrate 10.Selected according to the property requirements of Schottky diode
Suitable extension disk, the disk is made up of the substrate of low-resistivity and the epitaxial layer of specific electric resistance.
As shown in figure 3, deposit masking layer 21 and photoresist 22 carry out trench lithography, masking layer etching.It is raw on epitaxial layer
Long one layer of masking layer, the effect of the masking layer is to provide to shelter for etching groove below, and sheltering the composition of layer material can be
Silica, silicon nitride or both are combined；Trench lithography is carried out, and masking layer is performed etching, etching groove window is etched.
As shown in figure 4, removing photoresist 22, carry out groove 23 and etch.Photoresist is removed, etching groove is carried out, is sheltering
Groove is formed under the masking action of layer.
As shown in figure 5, depositing polysilicon 30, first deposits the polysilicon of layer, implanting p-type impurity adjusts injectant
Amount and Implantation Energy, polysilicon surface is injected into by impurity.Masking layer is removed, sacrifice oxidation is carried out, and remove removing oxide layer；Deposit
Polysilicon, first deposits the polysilicon of layer, implanting p-type impurity, regulation implantation dosage and Implantation Energy, impurity is injected into
Polysilicon surface.Because the non-impurity-doped polysilicon of first step deposit is relatively thin, Implantation Energy is controlled in 5~15kev, and injection is inclined
Rake angle is 7 °, and control is in the range of guaranteeing to be injected into trenched side-wall and bottom polysilicon, and implanted dopant is generally
Boron.Then second step deposits thicker non-impurity-doped polysilicon again, is filled up completely with groove, annealing, the condition of use of the invention
For 950 DEG C 30 minutes, impurity is uniformly spread, obtain final p-type polysilicon.
As shown in fig. 6, depositing polysilicon 40 again, trench fill is expired, and annealed, make impurity inside polysilicon dense
Degree is uniformly distributed.
As shown in fig. 7, removing surface is more than polysilicon, polysilicon surface in groove is set to maintain an equal level with epitaxial layer silicon face, and
Remove masking layer.
As shown in figure 8, insulating barrier 50 is deposited, cellular region surface insulation material is removed, is only retained in termination environment.
Deposited metal 60, and perform etching, anneal, extraction electrode is formed as the anode of device, and this metal level is by more
Layer metal level is constituted, and is common process, is obtained structure as shown in Figure 1.Deposited metal, and photoetching, etching are carried out, and formed
Extraction electrode is as the anode of device, and this metal level is made up of more metal layers, with N-type silicon epitaxy under rapid thermal anneal process
Layer forms Schottky contacts, and annealing temperature is between 600 DEG C~800 DEG C, and the time is less than 2 minutes.
It is thinned at the back side of N-type silicon chip, then deposited metal, such as silver, gold or other Low ESR alloy-layers,
It is used as the negative electrode of device.
As shown in Fig. 9,10, mutually homepitaxy lower groove metal-oxide-semiconductor structure is reverse with structure of the present invention
The emulation log curve maps of breakdown voltage, curve a is the breakdown voltage curve of structure of the present invention, and another is conventional trench Xiao Te
Based structures breakdown voltage curve, conventional trench Schottky junction structure breakdown voltage curve is 46.1V, and structure of the present invention punctures song
Line is 58.4V, it can be seen that the breakdown voltage of structure of the invention is significantly improved.
Cut-in voltage compares, and curve a is structure cut-in voltage curve of the present invention, and another curve is conventional trench Xiao Te
Based structures cut-in voltage curve, it can be seen that in the case of high current, the cut-in voltage of structure of the present invention is substantially reduced.
The present invention has the good breakdown reverse voltage of PN junction diode and the good positive guide of Schottky diode simultaneously
Logical characteristic.During reverse operation, the PN junction and the depletion layer of schottky junction formed at groove is overlapping in device surface, reduces Xiao Te
The electric-field intensity on base junction surface, is allowed to match with extension concentration by adjusting the doping concentration of polysilicon, reaches that raising is reversely hit
Wear the purpose of voltage.During forward direction work, when applying less operating voltage, the schottky junction guide with compared with low turn-on voltage
Logical, with alive increase is applied, PN junction also begins to conducting, and starts, as a large amount of few sons of drift region injection, to reduce drift region
Interior conducting resistance, reduces its forward conduction voltage under high current working condition.
Compared according to simulation result under the same terms, the p-type polysilicon groove structure in the present invention is than traditional groove knot
Structure is compared, and the conducting voltage under high current is significantly reduced, and by adjusting the dopant concentration of polysilicon, breakdown reverse voltage also can
It is improved.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the invention, all essences in the present invention
Any modification, equivalent and improvement made within refreshing and principle etc., should be included within the scope of the present invention.
Claims (8)
1. a kind of p-type polysilicon trench schottky diode, it is characterised in that including some grooves, the trench interiors pass through
Polysilicon, which forms sediment, sets full, and the polysilicon is p-type DOPOS doped polycrystalline silicon.
2. p-type polysilicon trench schottky diode according to claim 1, it is characterised in that the groove is located at N-type
In epitaxial layer.
3. p-type polysilicon trench schottky diode according to claim 2, it is characterised in that the N-type epitaxy layer is not
If fluted side is on N-type substrate.
4. p-type polysilicon trench schottky diode according to claim 3, it is characterised in that the one of N-type epitaxy layer
Outgrowth insulating barrier, and the insulating barrier be deposited in N-type epitaxy layer and groove top, form termination environment.
5. p-type polysilicon trench schottky diode according to claim 4, it is characterised in that do not formed sediment in N-type epitaxy layer
Deposited metal above product insulation layer segment and insulating barrier, forms anode.
6. a kind of preparation side for preparing the p-type polysilicon trench schottky diode in claim 1 to 5 described in any one
Method, it is characterised in that comprise the following steps：
The depositing polysilicon in groove, first deposits the polysilicon of layer, implanting p-type impurity, regulation implantation dosage and injection
Energy, polysilicon surface is injected into by impurity；
The second polysilicon is deposited, trench fill is expired, and is annealed, impurity concentration inside polysilicon is uniformly distributed.
7. the preparation method of p-type polysilicon trench schottky diode according to claim 6, it is characterised in that also wrap
Include following steps：Insulating barrier is deposited, and is removed cellular region surface insulation material, is only retained in termination environment.
8. the preparation method of p-type polysilicon trench schottky diode according to claim 7, it is characterised in that deposit
Metal level, and perform etching, anneal, anode of the extraction electrode as device is formed, this metal level is made up of more metal layers.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201710235233.3A CN106952942A (en) | 2017-04-12 | 2017-04-12 | A kind of Schottky diode of p-type polysilicon groove structure and preparation method thereof |
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| CN201710235233.3A CN106952942A (en) | 2017-04-12 | 2017-04-12 | A kind of Schottky diode of p-type polysilicon groove structure and preparation method thereof |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN108922872A (en) * | 2018-07-09 | 2018-11-30 | 盛世瑶兰（深圳）科技有限公司 | A kind of power device chip and preparation method thereof |
| CN109390232A (en) * | 2017-08-08 | 2019-02-26 | 天津环鑫科技发展有限公司 | Trench schottky termination environment groove etching method and trench schottky preparation method |
| CN113594263A (en) * | 2021-07-15 | 2021-11-02 | 淄博绿能芯创电子科技有限公司 | Silicon carbide diode and method of manufacture |
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| CN206697480U (en) * | 2017-04-12 | 2017-12-01 | 上海格瑞宝电子有限公司 | A kind of Schottky diode of p-type polysilicon groove structure |
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- 2017-04-12 CN CN201710235233.3A patent/CN106952942A/en active Pending
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| US6590240B1 (en) * | 1999-07-28 | 2003-07-08 | Stmicroelectronics S.A. | Method of manufacturing unipolar components |
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| CN109390232A (en) * | 2017-08-08 | 2019-02-26 | 天津环鑫科技发展有限公司 | Trench schottky termination environment groove etching method and trench schottky preparation method |
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