CN106935640A - HEMT and memory chip - Google Patents
HEMT and memory chip Download PDFInfo
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- CN106935640A CN106935640A CN201511029475.4A CN201511029475A CN106935640A CN 106935640 A CN106935640 A CN 106935640A CN 201511029475 A CN201511029475 A CN 201511029475A CN 106935640 A CN106935640 A CN 106935640A
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- 229910002601 GaN Inorganic materials 0.000 claims abstract description 46
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 claims abstract description 25
- 150000001875 compounds Chemical class 0.000 claims abstract description 22
- RNQKDQAVIXDKAG-UHFFFAOYSA-N aluminum gallium Chemical compound [Al].[Ga] RNQKDQAVIXDKAG-UHFFFAOYSA-N 0.000 claims abstract description 21
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 17
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 17
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 238000003780 insertion Methods 0.000 claims abstract description 8
- 230000037431 insertion Effects 0.000 claims abstract description 8
- 229910052809 inorganic oxide Inorganic materials 0.000 claims abstract description 7
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 12
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 12
- 239000002131 composite material Substances 0.000 claims description 8
- 238000000926 separation method Methods 0.000 claims description 8
- 229910052782 aluminium Inorganic materials 0.000 claims description 7
- 239000004411 aluminium Substances 0.000 claims description 7
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 7
- ZCZYDYAIIVVFPH-UHFFFAOYSA-N alumane;titanium Chemical compound [AlH3].[Ti].[Ti].[Ti] ZCZYDYAIIVVFPH-UHFFFAOYSA-N 0.000 claims description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 5
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 5
- 229910000449 hafnium oxide Inorganic materials 0.000 claims description 5
- WKMKTIVRRLOHAJ-UHFFFAOYSA-N oxygen(2-);thallium(1+) Chemical compound [O-2].[Tl+].[Tl+] WKMKTIVRRLOHAJ-UHFFFAOYSA-N 0.000 claims description 5
- 229910052710 silicon Inorganic materials 0.000 claims description 5
- 239000010703 silicon Substances 0.000 claims description 5
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 5
- 229910003438 thallium oxide Inorganic materials 0.000 claims description 5
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 4
- GWEVSGVZZGPLCZ-UHFFFAOYSA-N Titan oxide Chemical compound O=[Ti]=O GWEVSGVZZGPLCZ-UHFFFAOYSA-N 0.000 claims description 4
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 claims description 4
- 229910052733 gallium Inorganic materials 0.000 claims description 4
- 238000003475 lamination Methods 0.000 claims description 4
- OGIDPMRJRNCKJF-UHFFFAOYSA-N titanium oxide Inorganic materials [Ti]=O OGIDPMRJRNCKJF-UHFFFAOYSA-N 0.000 claims description 4
- YOCUPQPZWBBYIX-UHFFFAOYSA-N copper nickel Chemical compound [Ni].[Cu] YOCUPQPZWBBYIX-UHFFFAOYSA-N 0.000 claims description 3
- WIHZLLGSGQNAGK-UHFFFAOYSA-N hafnium(4+);oxygen(2-) Chemical compound [O-2].[O-2].[Hf+4] WIHZLLGSGQNAGK-UHFFFAOYSA-N 0.000 claims description 3
- 238000009413 insulation Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
- 239000000463 material Substances 0.000 description 4
- 230000008859 change Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052735 hafnium Inorganic materials 0.000 description 3
- VBJZVLUMGGDVMO-UHFFFAOYSA-N hafnium atom Chemical group [Hf] VBJZVLUMGGDVMO-UHFFFAOYSA-N 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 230000005533 two-dimensional electron gas Effects 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 238000013461 design Methods 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- RVTZCBVAJQQJTK-UHFFFAOYSA-N oxygen(2-);zirconium(4+) Chemical compound [O-2].[O-2].[Zr+4] RVTZCBVAJQQJTK-UHFFFAOYSA-N 0.000 description 2
- 238000011160 research Methods 0.000 description 2
- 229910001928 zirconium oxide Inorganic materials 0.000 description 2
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- QCWXUUIWCKQGHC-UHFFFAOYSA-N Zirconium Chemical compound [Zr] QCWXUUIWCKQGHC-UHFFFAOYSA-N 0.000 description 1
- 239000002253 acid Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 239000013078 crystal Substances 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 230000005693 optoelectronics Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000010287 polarization Effects 0.000 description 1
- 230000005855 radiation Effects 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
- H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Junction Field-Effect Transistors (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
Abstract
The invention provides a kind of HEMT and memory chip, wherein the HEMT includes：Substrate；Gallium nitride layer and aluminum gallium nitride layer, the side of the gallium nitride layer are compound in the top layer of the substrate, and the opposite side of the gallium nitride layer is compound in the bottom of the aluminum gallium nitride layer；Dielectric layer, is compound in the top layer of the aluminum gallium nitride layer, and the dielectric layer is provided with the contact hole of at least two insertions；Electrode, the electrode includes drain electrode, gate electrode and source electrode, the drain electrode and the source electrode are respectively arranged in the contact hole of corresponding at least two insertion in corresponding contact hole, wherein, the dielectric layer includes metal oxide layer and/or inorganic oxide layer.By technical scheme, the interfacial state of HEMT is improved, significantly reduce the reverse leakage current of transistor, while improving the reliability of transistor.
Description
Technical field
The present invention relates to technical field of semiconductors, in particular to a kind of high electron mobility crystal
Pipe and a kind of memory chip.
Background technology
In the related art, with the development of semiconductor fabrication, with low-power consumption and high speed high pass
The power device of characteristic turns into mainstream research direction.
GaN (gallium nitride) is third generation semiconductor material with wide forbidden band, with big energy gap
(3.4eV), electron saturation velocities high (2e7cm/s), breakdown electric field (1e10-- high
3e10V/cm), thermal conductivity higher, corrosion-resistant and radiation resistance, and high pressure, high frequency,
There is stronger advantage under high temperature, high-power and Flouride-resistani acid phesphatase environmental condition, thus be considered as short research
The optimal material of wavelength optoelectronic and high voltagehigh frequency rate high power device.
Specifically, high concentration, high mobility are formed at AlGaN (aluminum gallium nitride)/GaN hetero-junctions
Two-dimensional electron gas (2DEG, Two-dimensional electron gas), while hetero-junctions pair
2DEG has good adjustment effect, and GaN base AlGaN/GaN high mobility transistors are power
Study hotspot in device.
But, the use of GaN material and undoped intrinsic material, because its interfacial state causes device to be deposited
In serious reverse leakage, this has a strong impact on the reliability of HEMT.
Therefore, how to design a kind of new HEMT turns into current to improve interfacial state
Technical problem urgently to be resolved hurrily.
The content of the invention
The present invention is based on above mentioned problem, it is proposed that a kind of skill of new HEMT
Art scheme, by the boundary in HEMT, improving HEMT
Face state, significantly reduces the reverse leakage current of above-mentioned transistor, while improving above-mentioned transistor
Reliability.
In view of this, the present invention proposes a kind of HEMT, including：Substrate；Nitrogen
Change gallium layer and aluminum gallium nitride layer, the side of the gallium nitride layer is compound in the top layer of the substrate, described
The opposite side of gallium nitride layer is compound in the bottom of the aluminum gallium nitride layer；Dielectric layer, is compound in the nitrogen
Change the top layer of gallium aluminium lamination, the dielectric layer is provided with the contact hole of at least two insertions；Electrode, it is described
Electrode includes drain electrode, gate electrode and source electrode, the drain electrode and the source electrode
It is respectively arranged in the contact hole of corresponding at least two insertion in corresponding contact hole, wherein,
The dielectric layer includes metal oxide layer and/or inorganic oxide layer.
In the technical scheme, by after gallium nitride layer and aluminum gallium nitride layer is formed, being compounded to form
Dielectric layer, dielectric layer is hafnium, namely with appearance electrical characteristics high and insulation characterisitic, is improved
The interfacial state of HEMT, significantly reduces the reverse leakage current of transistor, reduces
The surface stress of device, while improve the reliability of transistor.
In technical scheme, it is preferred that the metal oxide layer includes：Hafnium oxide layer, zirconium oxide
At least one in layer, titanium oxide layer, alumina layer and thallium oxide layer.
In the technical scheme, hafnium oxide layer, zirconia layer, oxygen are included by setting metal oxide layer
Change at least one in titanium layer, alumina layer and thallium oxide layer, there is provided improve various realities of interfacial state
Scheme is applied, metal oxide has appearance electrical characteristics and insulation characterisitic high.
In technical scheme, it is preferred that the inorganic oxide layer also includes：First silicon nitride layer, institute
The first silicon nitride layer is stated to be compound between the metal oxide layer and the aluminum gallium nitride layer.
In the technical scheme, metal oxide layer and gallium nitride are compound in by setting the first silicon nitride layer
Between aluminium lamination, it is ensured that the voltage endurance of HEMT, reverse leakage is reduced.
In technical scheme, it is preferred that the source electrode is compound including the first titanium-aluminium-titanium-titanium nitride
Layer, the drain electrode includes the second titanium-aluminium-titanium-titanium nitride composite bed.
In technical scheme, it is preferred that the gate electrode includes nickel-copper composite bed
In technical scheme, it is preferred that the aluminum gallium nitride layer includes intrinsic gallium nitride constructed of aluminium layer.
In technical scheme, it is preferred that also include：Separation layer, is compound in the dielectric layer and described
The top layer of electrode.
In the technical scheme, separation layer is set by the top layer in insulating barrier and electrode, in lifter
On the premise of part reliability, interference of the spatial electromagnetic signal to HEMT is reduced.
In technical scheme, it is preferred that the separation layer includes silicon oxide layer and/or the second silicon nitride
Layer.
In technical scheme, it is preferred that the substrate includes intrinsic silicon layer.
According to the second aspect of the invention, it is proposed that a kind of memory chip, including：Such as any one skill
HEMT described in art scheme.
By above technical scheme, by after gallium nitride layer and aluminum gallium nitride layer is formed, being compounded to form
There is dielectric layer, dielectric layer is hafnium, namely with appearance electrical characteristics high and insulation characterisitic, improve
The interfacial state of HEMT, significantly reduces the reverse leakage current of transistor, together
When improve the reliability of transistor.
Brief description of the drawings
Fig. 1 to Fig. 3 shows the structure of HEMT according to an embodiment of the invention
Schematic diagram；
Fig. 4 shows the schematic block diagram of memory chip according to an embodiment of the invention.
Specific embodiment
In order to be more clearly understood that objects, features and advantages of the present invention, below in conjunction with the accompanying drawings and
Specific embodiment is further described in detail to the present invention.It should be noted that not conflicting
In the case of, the feature in embodiments herein and embodiment can be mutually combined.
Many details are elaborated in the following description in order to fully understand the present invention, but,
The present invention can also be different from other modes described here to implement using other, therefore, the present invention
Protection domain do not limited by following public specific embodiment.
With reference to Fig. 1 to Fig. 4, to HEMT according to an embodiment of the invention
It is specifically described.
As shown in Figure 1 to Figure 3, HEMT according to an embodiment of the invention
100, including：Substrate 1；Gallium nitride layer 2 and aluminum gallium nitride layer 3, the side of the gallium nitride layer 2
The top layer of the substrate 1 is compound in, the opposite side of the gallium nitride layer 2 is compound in the aluminum gallium nitride
The bottom of layer 3；Dielectric layer, is compound in the top layer of the aluminum gallium nitride layer 3, and the dielectric layer is set
There is the contact hole of at least two insertions；Electrode, the electrode includes 53 electrodes of drain electrode, the electricity of grid 52
Pole and the electrode of source electrode 52, the electrode of the drain electrode 53 and the electrode of the source electrode 52 are respectively arranged at correspondence
At least two insertion contact hole in corresponding contact hole, wherein, the dielectric layer includes
Metal oxide layer 42 and/or inorganic oxide layer.
In the technical scheme, by after gallium nitride layer 2 and aluminum gallium nitride layer 3 is formed, complex
Into there is dielectric layer, dielectric layer is hafnium, namely with appearance electrical characteristics high and insulation characterisitic, is changed
It has been apt to the interfacial state of HEMT 100, has significantly reduced the reverse leakage of transistor
Stream, reduces the surface stress of device, while improving the reliability of transistor.
Wherein, HEMT 100 apply electric load after, gallium nitride layer 2 and nitridation
Polarization induces two-dimensional electron gas 7 between gallium aluminium lamination 3, and it has high concentration and high mobility characteristic,
While improving device reliability, it is ensured that the manufacture craft of HEMT 100 is compatible
In CMOS (Complementary Metal-Oxide-Semiconductor Transistor, compensation payment
Category oxide-semiconductor transistors) technique is to cause cost so as to reduce.
Embodiment one：
As shown in figure 1, dielectric layer includes the first silicon nitride layer 41 and high-K metal successively from top to bottom
Oxide layer 42.
Embodiment two：
As shown in Fig. 2 dielectric layer includes that the first silicon nitride layer 41, first is aoxidized successively from top to bottom
Silicon layer and high-K metal oxide layer 42.
Embodiment three：
As shown in figure 3, dielectric layer only includes the first silicon oxide layer, wherein the first silicon oxide layer falls within
K compounds high, can equally ensure the voltage endurance of HEMT 100, meanwhile,
Reduce manufacture difficulty and membrane stress.
In technical scheme, it is preferred that the metal oxide layer 42 includes：Hafnium oxide layer, oxidation
At least one in zirconium layer, titanium oxide layer, alumina layer and thallium oxide layer.
In the technical scheme, hafnium oxide layer, zirconium oxide are included by setting metal oxide layer 42
At least one in layer, titanium oxide layer, alumina layer and thallium oxide layer, there is provided improve interfacial state
Multiple embodiments, metal oxide has appearance electrical characteristics and insulation characterisitic high.
In technical scheme, it is preferred that the inorganic oxide layer also includes：First silicon nitride layer
41, first silicon nitride layer 41 is compound in the metal oxide layer 42 and the aluminum gallium nitride layer 3
Between.
In the technical scheme, the He of metal oxide layer 42 is compound in by setting the first silicon nitride layer 41
Between aluminum gallium nitride layer 3, it is ensured that the voltage endurance of HEMT 100, reduce
Reverse leakage.
In technical scheme, it is preferred that the source electrode 53 includes the first titanium-aluminium-titanium-titanium nitride
Composite bed, the drain electrode 51 includes the second titanium-aluminium-titanium-titanium nitride composite bed 42
In technical scheme, it is preferred that the gate electrode 52 includes nickel-copper composite bed.
In technical scheme, it is preferred that the aluminum gallium nitride layer 3 includes intrinsic gallium nitride constructed of aluminium
Layer.
In technical scheme, it is preferred that also include：Separation layer 6, is compound in the dielectric layer and institute
State the top layer of electrode.
In the technical scheme, separation layer 6 is set by the top layer in insulating barrier and electrode, in lifting
On the premise of device reliability, spatial electromagnetic signal is reduced to HEMT 100
Interference.
In technical scheme, it is preferred that the separation layer 6 includes silicon oxide layer and/or the second nitridation
Silicon layer.
In technical scheme, it is preferred that the substrate 1 includes intrinsic silicon layer.
Fig. 4 shows the schematic block diagram of memory chip according to an embodiment of the invention.
As shown in figure 4, memory chip 400 according to an embodiment of the invention, including：It is such as any
HEMT 100 described in item technical scheme.
Technical scheme is described in detail above in association with accompanying drawing, it is contemplated that proposed in correlation technique
How to design a kind of technical scheme of new HEMT, the present invention proposes one kind
The technical scheme of new HEMT, by optimised devices structure, reduces device table
The defect concentration in face, is greatly reduced reverse leakage, improves the performance of device.
The preferred embodiments of the present invention are the foregoing is only, is not intended to limit the invention, for
For those skilled in the art, the present invention can have various modifications and variations.It is all in essence of the invention
Within god and principle, any modification, equivalent substitution and improvements made etc. should be included in the present invention
Protection domain within.
Claims (10)
1. a kind of HEMT, it is characterised in that including：
Substrate；
Gallium nitride layer and aluminum gallium nitride layer, the side of the gallium nitride layer are compound in the table of the substrate
Layer, the opposite side of the gallium nitride layer is compound in the bottom of the aluminum gallium nitride layer；
Dielectric layer, is compound in the top layer of the aluminum gallium nitride layer, and the dielectric layer is provided with least two
The contact hole of insertion；
Electrode, the electrode includes drain electrode, gate electrode and source electrode, the drain electrode
Corresponding in the contact hole of corresponding at least two insertion connecing is respectively arranged at the source electrode
In contact hole,
Wherein, the dielectric layer includes metal oxide layer and/or inorganic oxide layer.
2. HEMT according to claim 1, it is characterised in that described
Metal oxide layer includes：
In hafnium oxide layer, zirconia layer, titanium oxide layer, alumina layer and thallium oxide layer at least one
Kind.
3. HEMT according to claim 2, it is characterised in that described
Inorganic oxide layer also includes：
First silicon nitride layer, first silicon nitride layer is compound in the metal oxide layer and the nitridation
Between gallium aluminium lamination.
4. HEMT according to claim 3, it is characterised in that described
Source electrode include the first titanium-aluminium-titanium-titanium nitride composite bed, the drain electrode include the second titanium-aluminium-
Titanium-titanium nitride composite bed.
5. HEMT according to claim 4, it is characterised in that described
Gate electrode includes nickel-copper composite bed.
6. HEMT according to any one of claim 1 to 5, it is special
Levy and be, the aluminum gallium nitride layer includes intrinsic gallium nitride constructed of aluminium layer.
7. HEMT according to any one of claim 1 to 5, it is special
Levy and be, also include：
Separation layer, is compound in the top layer of the dielectric layer and the electrode.
8. HEMT according to any one of claim 1 to 5, it is special
Levy and be, the separation layer includes silicon oxide layer and/or the second silicon nitride layer.
9. HEMT according to any one of claim 1 to 5, it is special
Levy and be, the substrate includes intrinsic silicon layer.
10. a kind of memory chip, it is characterised in that including：
HEMT as claimed in any one of claims 1-9 wherein.
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| CN201511029475.4A CN106935640A (en) | 2015-12-31 | 2015-12-31 | HEMT and memory chip |
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| CN201511029475.4A CN106935640A (en) | 2015-12-31 | 2015-12-31 | HEMT and memory chip |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110890423A (en) * | 2019-11-28 | 2020-03-17 | 西安电子科技大学芜湖研究院 | High-voltage gallium nitride power device structure and preparation method thereof |
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- 2015-12-31 CN CN201511029475.4A patent/CN106935640A/en active Pending
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