CN106935599B - Manufacturing method of display substrate, display substrate and display device - Google Patents
Manufacturing method of display substrate, display substrate and display device Download PDFInfo
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- CN106935599B CN106935599B CN201710333308.1A CN201710333308A CN106935599B CN 106935599 B CN106935599 B CN 106935599B CN 201710333308 A CN201710333308 A CN 201710333308A CN 106935599 B CN106935599 B CN 106935599B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
- H01L27/1244—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits for preventing breakage, peeling or short circuiting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
Abstract
The invention provides a manufacturing method of a display substrate, the display substrate and a display device. The manufacturing method comprises the following steps: the method includes the steps of forming a via hole penetrating through a plurality of film layers and forming a conductive pattern covering the via hole. The step of forming the via hole includes: forming a climbing auxiliary structure at least at the edge of the via hole; the step of forming the conductive pattern includes: and forming a conductive pattern on the climbing auxiliary structure, so that the conductive pattern can continuously and uninterruptedly extend from the inside of the through hole to the outside of the through hole based on the climbing auxiliary structure. According to the scheme, the climbing auxiliary structure is arranged at the edge of the via hole, so that the conductive pattern is deposited on the climbing auxiliary structure, the phenomenon that the signal loading is influenced due to the fact that the conductive pattern is broken nearby the position of the via hole is avoided, and the probability of poor display phenomena such as bright spots and stripes of a display picture can be reduced.
Description
Technical Field
The present invention relates to the field of manufacturing display products, and in particular, to a method for manufacturing a display substrate, and a display device.
Background
The Half-connection hole process is used as a mode for realizing signal switching between an upper electrode and a lower electrode in a pixel, and the number of switching holes arranged in an array substrate is greatly reduced, so that the phenomenon of uneven diffusion of PI (materials of alignment liquid) and LC (liquid crystal) is favorably improved.
However, the current hall-contact hole preparation process still has some problems:
as shown in fig. 1, in the conventional Half-contact hole preparation process, in the process of etching a via hole in an insulating layer GI, an Active layer Active and the insulating layer GI under a source-drain metal pattern SD are generally over-etched (the source-drain metal pattern SD is made of a metal material and is not easily etched), so that after the etching is finished, the size of the source-drain metal pattern SD is larger than the size of the Active layer Active and the insulating layer GI under the source-drain metal pattern SD, so that when a common electrode 2ITO is subsequently deposited, the source-drain metal pattern SD has a certain shielding effect on an elliptic dotted line in fig. 1, and a step difference exists at the position, which easily causes that the material of the common electrode 2ITO cannot be continuously deposited at the elliptic dotted line in fig. 1, so that a break occurs at the position, and only narrow common electrodes on two sides around the break can be used for transmitting signals, thereby greatly reducing the transmission efficiency of the signals, the charging of the pixel is insufficient, Ion (off-state current) is low, and the display screen has bright spots and stripes.
Of course, the above problem does not occur only on the common electrode, but there is a problem that a crack may occur in all the conductive patterns formed at the via holes. .
Disclosure of Invention
The invention aims to solve the problem that the signal transmission is influenced because the subsequent deposited conductive pattern is more broken easily by the conventional Half-contact hole process.
In order to achieve the above object, in one aspect, an embodiment of the present invention provides a method for manufacturing a display substrate, including a step of forming a via hole penetrating through a plurality of film layers and a step of forming a conductive pattern covering the via hole.
The step of forming the via hole includes:
forming a climbing auxiliary structure at least at the edge of the via hole;
the step of forming the conductive pattern includes:
and forming a conductive pattern on the climbing auxiliary structure, so that the conductive pattern can continuously and uninterruptedly extend from the inside of the through hole to the outside of the through hole based on the climbing auxiliary structure.
Wherein the step of forming the via hole comprises the steps of:
forming via holes penetrating through the plurality of film layers;
before the step of forming the conductive pattern, depositing an insulating material at the edge of the via to form a climbing assistance structure.
The step of forming the via hole specifically comprises:
and forming a via hole penetrating through at least one side edge of the multiple film layers to form a stepped structure, wherein in the stepped structure, the lower film layer is in an ascending order towards the upper film layer, and the distance of staggered arrangement is greater than or equal to a preset threshold value.
The conductive pattern is a common electrode, the plurality of film layers are insulating layers, active layers and source-drain metal patterns, and the manufacturing method specifically comprises the following steps:
sequentially forming a pixel electrode, an insulating layer, an active layer and a source drain metal pattern on a substrate; the pixel electrode is provided with a first region used for being connected with a common electrode, the source-drain metal pattern is provided with a second region used for being connected with the common electrode, and the orthographic projection of the first region on the substrate is mutually independent of the orthographic projection of the active layer and the orthographic projection of the source-drain metal pattern on the substrate;
forming a protective layer with a first through hole and a second through hole on a substrate base plate on which the pixel electrode, the insulating layer, the active layer and the source-drain metal pattern are formed, wherein the first through hole corresponds to the first area, and the second through hole corresponds to the second area;
etching the insulating layer by taking the protective layer as a mask plate so as to form a third through hole on the insulating layer at a position corresponding to the first region; the insulating layer and the active layer form the stepped structure at one side adjacent to the third via hole;
and forming a common electrode, wherein the common electrode is connected with the pixel electrode through the third via hole and is connected with the source and drain metal pattern through the second via hole.
Wherein, form the protective pattern layer with first via hole and second via hole on forming the substrate base plate of pixel electrode, insulating layer, active layer and source leakage metal figure, include:
depositing an insulating material on the substrate with the pixel electrode, the insulating layer, the active layer and the source drain metal pattern so as to form a protective pattern layer;
coating photoresist on the protective layer;
exposing the photoresist through a mask plate, and developing to form a photoresist reserved region and a photoresist unreserved region, wherein the photoresist unreserved region corresponds to the first region and the second region, and the photoresist reserved region corresponds to a region outside the first region and the second region;
and etching the protective layer of the photoresist unreserved region to form a first via hole and a second via hole in the protective layer.
And one side of the source-drain metal pattern adjacent to the third via hole forms the stepped structure.
The etching of the part of the insulating layer corresponding to the first area by using the protective layer as a mask comprises the following steps:
after the first via hole and the second via hole are formed, removing the photoresist of the protective layer between the first via hole and the second via hole;
etching the part of the insulating layer corresponding to the first area and the part of the protective layer which is not covered by the photoresist by using an etching solution so as to form the third through hole in the insulating layer and communicate the first through hole and the second through hole in the protective layer to form a fourth through hole;
removing the residual photoresist of the protective layer;
the common electrode is connected with the source-drain metal pattern through the fourth through hole of the protection layer and is connected with the pixel electrode through the fourth through hole of the protection layer and the third through hole of the insulating layer.
The second region is an edge region of the source-drain metal pattern adjacent to the third via hole, so that one side of a protective layer formed on the source-drain metal pattern adjacent to the third via hole forms the stepped structure.
On the other hand, the embodiment of the invention also provides a display substrate, and the display substrate is manufactured by the manufacturing method.
In addition, the invention also provides a display device which comprises the display substrate.
The scheme of the invention has the following beneficial effects:
according to the scheme, the climbing auxiliary structure is arranged at the edge of the via hole, so that the conductive pattern is deposited on the climbing auxiliary structure, the phenomenon that the signal loading is influenced due to the fact that the conductive pattern is broken nearby the position of the via hole is avoided, and the probability of poor display phenomena such as bright spots and stripes of a display picture can be reduced.
Drawings
Fig. 1 is a schematic view illustrating a broken common electrode line of a conventional display substrate;
FIGS. 2A-2C are schematic flow charts of a method for manufacturing a display substrate according to a first implementation manner of the present invention;
FIGS. 3A to 3D are schematic flow charts of a second implementation manner of the method for manufacturing a display substrate according to the present invention;
fig. 4A to fig. 4H are schematic detailed flow charts of a second implementation manner of the method for manufacturing a display substrate according to the present invention.
Detailed Description
In order to make the technical problems, technical solutions and advantages of the present invention more apparent, the following detailed description is given with reference to the accompanying drawings and specific embodiments.
Aiming at the problem that the signal transmission is influenced by the fact that the subsequently deposited conductive pattern is easy to break in the existing Half-contact hole process, the invention provides a solution.
In one aspect, the invention provides a method for manufacturing a display substrate, comprising the steps of forming via holes penetrating through a plurality of film layers and forming a conductive pattern covering the via holes;
wherein, the step of forming the via hole comprises:
forming a climbing auxiliary structure at least at the edge of the via hole;
the step of forming the conductive pattern includes:
and forming a conductive pattern on the climbing auxiliary structure, so that the conductive pattern can continuously extend from the inside of the via hole to the outside of the via hole based on the climbing auxiliary structure.
In the manufacturing method of the embodiment, the climbing auxiliary structure is arranged at the edge of the via hole, so that the conductive pattern is deposited on the climbing auxiliary structure, thereby avoiding the phenomenon that the signal loading is influenced by the fracture near the via hole position, and reducing the probability of poor display phenomena such as bright spots, stripes and the like on a display picture.
By way of exemplary introduction, the present embodiment may be implemented in two ways to form a climbing assistance structure.
One way to implement this is to form the climbing assistance structure at the edge of the via hole through a separate process, that is, the step of forming the via hole in this embodiment includes:
step a1, as shown in fig. 2A, forming via holes (at the oval dotted lines) penetrating through a plurality of film layers (the plurality of film layers may be, but are not limited to, the passivation layer PVX and the insulating layer GI shown in fig. 2A) according to a conventional Half-contact hole process;
step a2, as shown in fig. 2B, before the step of forming the conductive pattern, depositing an insulating material at the edge of the via hole to form a climbing assistance structure Filler; compared with the prior art shown in fig. 1, the hill climbing assistance structure Filler of the present embodiment may be filled with the Active layer Active and the over-etched portion of the insulating layer GI;
in this step, it is preferable that the climbing assistance structure Filler is made of an insulating material with good fluidity, corrosion resistance and high temperature resistance, such as photoresist. After the photoresist deposition is completed, different areas of the photoresist are exposed with different intensities to form a climbing assistance structure Filler shown in fig. 2B.
Taking a positive photoresist as an example, in a photoresist area where a climbing auxiliary structure Filler needs to be formed, the corresponding exposure amount should be gradually reduced as the gradient is continuously increased; and correspondingly removing the part of the photoresist by adopting full exposure without setting the photoresist area of the climbing auxiliary structure Filler.
After the via hole is formed, a conductive pattern is further formed, including:
step a3, as shown in fig. 2C, a conductive material is deposited and patterned by an etching process to form the common electrode 2 ITO.
Obviously, the implementation method described above does not change the existing manufacturing process, but adds a photoresist exposure process on the basis, so that the implementation is easy, the cost required for implementation is low, and the practical value is high.
In addition, after the verification, the continuity that the public electrode 2ITO extends to the area outside the via hole in the via hole is effectively ensured by the realization mode, so that the condition that the signal transmission can be carried out only by the limited space on the two sides of the via hole in the prior art is changed, the transmission efficiency of the signal can be greatly improved, bright spots on a display picture are avoided, and the yield of the display product is improved.
Correspondingly, another implementation is that the layer at the edge of the via hole is directly manufactured into a climbing auxiliary structure, and the climbing auxiliary structure is manufactured independently without additionally increasing the process, namely, the step of forming the via hole in the embodiment includes:
and forming a via hole penetrating through at least one side edge of the multiple film layers to form a stepped structure, wherein in the stepped structure, the lower film layer is in an ascending order towards the upper film layer, and the distance of the staggered arrangement is greater than or equal to a preset threshold value.
As an exemplary introduction, assuming that the conductive pattern is still a common electrode, and the plurality of film layers include an insulating layer, an active layer, and a source-drain metal pattern, the manufacturing method of the embodiment specifically includes:
step B1, as shown in fig. 3A, sequentially forming a pixel electrode 2, an insulating layer 3, an active layer 4, and a source-drain metal pattern 5 on a substrate 1; the pixel electrode 2 is provided with a first area a connected with the common electrode, and the source-drain metal pattern 5 is provided with a second area b connected with the common electrode;
the orthographic projection of the first region a on the substrate base plate 1 is independent of the orthographic projection of the active layer 4 and the orthographic projection of the source-drain metal pattern 5 on the substrate base plate 1;
step B2, as shown in fig. 3B, forming a protective layer 6 having a first via 61 and a second via 62 on the substrate 1 on which the pixel electrode 2, the insulating layer 3, the active layer 4 and the source-drain metal pattern 5 are formed, where the first via 61 corresponds to the first area a, and the second via 62 corresponds to the second area B; the protective layer 6 between the first via hole 61 and the second via hole 62 may cover one side of the active layer 4 and the source-drain metal pattern 5 to form a climbing auxiliary structure, which may prevent the active layer 4 and the source-drain metal pattern 5 from being etched, and avoid forming the substrate structure shown in fig. 1;
step B3, as shown in fig. 3C, etching the insulating layer 3 by using the protective layer 6 as a mask, so that the insulating layer 3 forms a third via hole 31 at a position corresponding to the first region a; it should be noted that, in this step, the etching selection ratio of the protection layer 6 may be, but is not necessarily, smaller than that of the insulating layer 3, so that after the third via hole 31 is formed in the insulating layer 3, the protection layer 6 is not completely etched away;
step B4, as shown in fig. 3D, forming a common electrode 7, where the common electrode 7 is connected to the pixel electrode 2 through the third via 31 and is connected to the source-drain metal pattern 5 through the second via 62.
Obviously, in the second implementation, the right side of the via hole forms a step structure, so that the common electrode 7 can also be deposited continuously and uninterruptedly based on the step structure.
Further, as a preferable scheme of the second implementation manner, the step B2 specifically includes:
step B21, referring to fig. 4A, depositing an insulating material on the substrate base plate 1 on which the pixel electrode 2, the insulating layer 3, the active layer 4 and the source-drain metal pattern 5 are formed, to form a protective pattern layer 6;
step B22, referring to fig. 4B, applying a photoresist 8 on the protective layer 6;
step B23, referring to fig. 4C, exposing the photoresist 8 through a mask plate, and developing to form a photoresist reserved region and a photoresist unreserved region, where the photoresist unreserved region corresponds to the first region a and the second region B, and the photoresist reserved region corresponds to a region other than the first region a and the second region B;
then, the step B3 is executed to etch the protection layer 6, and the specific steps include:
step B31, referring to fig. 4D, etching the protection layer 6 in the photoresist unreserved region, so that the first via hole 61 and the second via hole 62 are formed in the protection layer 6.
Step B32, referring to fig. 4E, after the first via hole 61 and the second via hole 62 are formed, removing the photoresist 8 of the protective layer 6 between the first via hole 61 and the second via hole 62;
step B33, referring to fig. 4F, etching, by using an etching solution, a portion of the insulating layer 3 corresponding to the first region and a portion of the protective layer 6 not covered by the photoresist 8, so that the third via hole 31 is formed in the insulating layer 3, and the first via hole 61 and the second via hole 62 of the protective layer 6 are communicated with each other to form a fourth via hole 63;
in the etching process of this step, the protective layer 6 not covered by the photoresist 8 plays a certain role in protecting the insulating layer 3 and the active layer 4 below, so that the insulating layer 3 and the active layer 4 are prevented from being over-etched, and a step structure, i.e., the above-mentioned climbing assistance structure, is formed on one side of the adjacent third via hole 31 with the protective layer 6.
And then, the step B4 is executed to form a common electrode, and the specific steps include:
step B41, referring to fig. 4G, removing the remaining photoresist 8 on the protective layer 6;
step B42, referring to fig. 4H, depositing a transparent conductive material ITO to form the common electrode 7;
obviously, in this embodiment, the common electrode 7 is at the bottommost layer of the via hole position, and continuous deposition in a climbing manner is completed along the stepped structure of the insulating layer 3, the active layer 4, the source-drain metal pattern 5, and the protective layer 6, so as to avoid occurrence of fracture.
In addition, as another possible solution of this embodiment, the step B32 and the step B33 may be completed in one step, that is, in the step 33, the photoresist 8 of the protective layer 6 between the first via 61 and the second via 62 is removed by etching. Referring to fig. 4C and 4D, in step B23, the photoresist 8 of the protective layer 6 between the first via 61 and the second via 62 may be half-exposed, so as to obtain a photoresist partial-remaining region (the photoresist 8 at the middle position), which has a thickness smaller than that of the photoresist partial-remaining region (the photoresist 8 at the two side positions). When the etching liquid is used to etch the third via hole 31 in the subsequent step B33, the etching liquid can etch away the photoresist part remaining region and the protective layer 6 between the first via hole 61 and the second via hole 62, thereby reducing one manufacturing process.
The above two ways are exemplary descriptions of the manufacturing method of the embodiment, and are not limited to the protection scope of the present invention, and as other possible ways, the conductive pattern of the embodiment is not limited to the common electrode. In addition, the via hole may also be a via hole formed in any other layer or any plurality of layers.
On the other hand, another embodiment of the present invention further provides a display substrate, which is manufactured by the above manufacturing method provided by the present invention.
Obviously, based on the manufacturing method of the present invention, the conductive pattern of the display substrate of the embodiment can avoid the occurrence of fracture at the position of the via hole, thereby ensuring normal loading of signals, and preventing the display frame from easily generating undesirable phenomena such as bright spots, stripes, and the like.
In addition, the embodiment of the invention also provides a display device, which comprises the display substrate, so that the technical effects similar to those of the display substrate can be realized.
In practical applications, the display device of the present embodiment may refer to a display panel, and may also refer to: such as mobile phone, PAD, television, vehicle terminal, etc.
While the foregoing is directed to the preferred embodiment of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.
Claims (8)
1. A method for manufacturing a display substrate comprises a step of forming via holes penetrating a plurality of film layers and a step of forming a conductive pattern covering the via holes,
the step of forming the via hole includes:
forming a climbing auxiliary structure at least at the edge of the via hole;
the step of forming the conductive pattern includes:
forming a conductive pattern on the climbing auxiliary structure, so that the conductive pattern can continuously and uninterruptedly extend from the inside of the via hole to the outside of the via hole based on the climbing auxiliary structure;
the step of forming the via hole specifically comprises:
forming a via hole penetrating through at least one side edge of the plurality of film layers to form a stepped structure, wherein in the stepped structure, the lower film layer is in an ascending order towards the upper film layer, and the distance of staggered arrangement is greater than or equal to a preset threshold value;
the conductive pattern is a common electrode, the plurality of film layers are insulating layers, active layers and source-drain metal patterns, and the manufacturing method specifically comprises the following steps:
sequentially forming a pixel electrode, an insulating layer, an active layer and a source drain metal pattern on a substrate; the pixel electrode is provided with a first region used for being connected with a common electrode, the source-drain metal pattern is provided with a second region used for being connected with the common electrode, and the orthographic projection of the first region on the substrate is mutually independent of the orthographic projection of the active layer and the orthographic projection of the source-drain metal pattern on the substrate;
forming a protective layer with a first through hole and a second through hole on a substrate base plate on which the pixel electrode, the insulating layer, the active layer and the source-drain metal pattern are formed, wherein the first through hole corresponds to the first area, and the second through hole corresponds to the second area;
etching the insulating layer by taking the protective layer as a mask plate so as to form a third through hole on the insulating layer at a position corresponding to the first region; the insulating layer and the active layer form the stepped structure at one side adjacent to the third via hole;
and forming a common electrode, wherein the common electrode is connected with the pixel electrode through the third via hole and is connected with the source and drain metal pattern through the second via hole.
2. The method of manufacturing a display substrate according to claim 1,
the step of forming the via hole includes steps specifically including:
forming via holes penetrating through the plurality of film layers;
before the step of forming the conductive pattern, depositing an insulating material at the edge of the via to form a climbing assistance structure.
3. The method of manufacturing a display substrate according to claim 1,
forming a protective pattern layer with a first via hole and a second via hole on a substrate base plate on which the pixel electrode, the insulating layer, the active layer and the source-drain metal pattern are formed, wherein the protective pattern layer comprises:
depositing an insulating material on the substrate with the pixel electrode, the insulating layer, the active layer and the source drain metal pattern so as to form a protective pattern layer;
coating photoresist on the protective layer;
exposing the photoresist through a mask plate, and developing to form a photoresist reserved region and a photoresist unreserved region, wherein the photoresist unreserved region corresponds to the first region and the second region, and the photoresist reserved region corresponds to a region outside the first region and the second region;
and etching the protective layer of the photoresist unreserved region to form a first via hole and a second via hole in the protective layer.
4. The method of claim 3, wherein the step of forming the display substrate comprises the steps of,
and one side of the source-drain metal pattern adjacent to the third via hole forms the stepped structure.
5. The method of manufacturing a display substrate according to claim 3 or 4,
and etching the part of the insulating layer corresponding to the first area by using the protective layer as a mask plate, wherein the etching process comprises the following steps:
after the first via hole and the second via hole are formed, removing the photoresist of the protective layer between the first via hole and the second via hole;
etching the part of the insulating layer corresponding to the first area and the part of the protective layer which is not covered by the photoresist by using an etching solution so as to form the third through hole in the insulating layer and communicate the first through hole and the second through hole in the protective layer to form a fourth through hole;
removing the residual photoresist of the protective layer;
the common electrode is connected with the source-drain metal pattern through the fourth through hole of the protection layer and is connected with the pixel electrode through the fourth through hole of the protection layer and the third through hole of the insulating layer.
6. The method of manufacturing a display substrate according to claim 5,
the second region is an edge region of the source-drain metal pattern adjacent to the third via hole, so that one side of a protective layer formed on the source-drain metal pattern adjacent to the third via hole forms the stepped structure.
7. A display substrate manufactured by the manufacturing method of any one of claims 1 to 6.
8. A display device comprising the display substrate according to claim 7.
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| CN103488007A (en) * | 2013-09-30 | 2014-01-01 | 合肥京东方光电科技有限公司 | Array substrate, manufacturing method of array substrate and displaying device |
| CN104078470A (en) * | 2014-06-18 | 2014-10-01 | 京东方科技集团股份有限公司 | Array substrate, producing method thereof, display device |
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| CN106575063B (en) * | 2014-08-07 | 2019-08-27 | 夏普株式会社 | The manufacturing method of active-matrix substrate, liquid crystal display panel and active-matrix substrate |
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| CN103488007A (en) * | 2013-09-30 | 2014-01-01 | 合肥京东方光电科技有限公司 | Array substrate, manufacturing method of array substrate and displaying device |
| CN104078470A (en) * | 2014-06-18 | 2014-10-01 | 京东方科技集团股份有限公司 | Array substrate, producing method thereof, display device |
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