CN106935497B - High-power Pin diode and preparation method thereof - Google Patents
High-power Pin diode and preparation method thereof Download PDFInfo
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- 238000002360 preparation method Methods 0.000 title claims abstract description 12
- 239000000758 substrate Substances 0.000 claims abstract description 39
- 238000005530 etching Methods 0.000 claims abstract description 35
- 238000004519 manufacturing process Methods 0.000 claims abstract description 11
- 238000000034 method Methods 0.000 claims description 130
- 239000010410 layer Substances 0.000 claims description 59
- 238000001312 dry etching Methods 0.000 claims description 20
- 238000001039 wet etching Methods 0.000 claims description 20
- 238000005229 chemical vapour deposition Methods 0.000 claims description 19
- 239000011241 protective layer Substances 0.000 claims description 15
- 238000011065 in-situ storage Methods 0.000 claims description 14
- 239000000463 material Substances 0.000 claims description 12
- 238000001259 photo etching Methods 0.000 claims description 10
- 229910052681 coesite Inorganic materials 0.000 claims description 7
- 229910052906 cristobalite Inorganic materials 0.000 claims description 7
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N silicon dioxide Inorganic materials O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 7
- 238000004544 sputter deposition Methods 0.000 claims description 7
- 229910052682 stishovite Inorganic materials 0.000 claims description 7
- 229910052905 tridymite Inorganic materials 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 6
- 230000003647 oxidation Effects 0.000 claims description 6
- 238000007254 oxidation reaction Methods 0.000 claims description 6
- 238000000137 annealing Methods 0.000 claims description 4
- 239000012535 impurity Substances 0.000 claims description 4
- 230000001590 oxidative effect Effects 0.000 claims description 4
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 4
- 229920005591 polysilicon Polymers 0.000 claims description 4
- 230000004913 activation Effects 0.000 claims description 3
- 239000013078 crystal Substances 0.000 claims description 3
- 239000002184 metal Substances 0.000 claims description 3
- 238000005498 polishing Methods 0.000 claims description 3
- 239000000126 substance Substances 0.000 claims description 3
- 239000000969 carrier Substances 0.000 abstract description 4
- 210000002381 plasma Anatomy 0.000 description 17
- 229910052581 Si3N4 Inorganic materials 0.000 description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 6
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
- H01L29/6609—Diodes
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- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
- H01L29/861—Diodes
- H01L29/868—PIN diodes
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Abstract
The invention relates to a high-power Pin diode and a preparation method thereof, wherein the preparation method comprises the following steps: selecting an SOI substrate; etching the SOI substrate to form a first active area groove and a second active area groove on two sides of a Pin diode to be prepared; respectively forming a first P area and a second P area in the first designated area of the first active area groove and the second active area groove; respectively forming a first N area and a second N area in a second designated area of the first active area groove and the second active area groove; carrying out surface planarization treatment on the whole device comprising the SOI substrate, the first P area, the second P area, the first N area and the second N area; and manufacturing leads in third designated areas of the first active area groove and the second active area groove to finish the preparation of the Pin diode. The high-power Pin diode provided by the invention adopts a two-layer groove design, so that the current carriers in the intrinsic region are distributed more uniformly, and the performance of the device is greatly improved.
Description
Technical Field
The invention relates to the field of design and manufacture of semiconductor devices, in particular to a high-power Pin diode and a preparation method thereof.
Background
In recent years, theories of antenna broadband, miniaturization, and reconfiguration and multiplexing have been actively studied. In this context, researchers have proposed a new antenna concept, the plasmonic antenna, which is a radio frequency antenna that directs plasmons as electromagnetic radiation into a medium. The plasma antenna can change the instantaneous bandwidth of the antenna by changing the plasma density and has a large dynamic range; the frequency, beam width, power, gain and directivity dynamic parameters of the antenna can be adjusted by changing the plasma resonance, impedance, density and the like; in addition, the scattering cross section of the radar can be ignored when the plasma antenna is not excited, and the antenna is excited only in a short time of communication sending or receiving, so that the concealment of the antenna is improved.
However, most of the current research is limited to the gas plasma antenna, and the research on the solid plasma antenna is almost blank. The solid plasma generally exists in the semiconductor device, and is not wrapped by a medium tube like gaseous plasma, so that the semiconductor device has better safety and stability.
Lateral PiN diodes are important semiconductor devices for generating solid state plasmas. The theoretical research shows that when the solid plasma PiN diode is applied with direct current bias, direct current forms solid plasma consisting of free carriers on the surface of the solid plasma PiN diode, the plasma has metalloid characteristics, so that the plasma can receive, radiate and reflect electromagnetic waves, and the radiation characteristics of the plasma are closely related to the microwave transmission characteristics, concentration and distribution of the surface plasma.
When a direct current bias is applied to the currently researched PiN diode, the carrier distribution in the intrinsic region is uneven, the carrier concentration at the deeper part in the intrinsic region is lower, so that the performance of a plasma region in transmitting and radiating electromagnetic waves is attenuated, and the power density of the diode is low, so that the application of the existing PiN diode is greatly limited.
Disclosure of Invention
Therefore, in order to solve the technical defects and shortcomings in the prior art, the invention provides a high-power Pin diode and a preparation method thereof.
The embodiment of the invention provides a preparation method of a high-power Pin diode, which comprises the following steps:
(a) selecting an SOI substrate;
(b) etching the SOI substrate by utilizing an etching process to form a first active area groove and a second active area groove on two sides of the Pin diode to be prepared;
(c) respectively forming a first P area and a second P area in the first designated area of the first active area groove and the second active area groove by utilizing an in-situ doping process;
(d) respectively forming a first N area and a second N area in a second designated area of the first active area groove and the second active area groove by utilizing an in-situ doping process;
(e) carrying out surface planarization treatment on the whole device comprising the SOI substrate, the first P region, the second P region, the first N region and the second N region by utilizing a CMP (chemical mechanical polishing) process;
(f) and manufacturing leads in third designated areas of the first active area groove and the second active area groove to finish the preparation of the Pin diode.
In one embodiment of the present invention, step (a) comprises:
selecting the doping concentration to be 1 × 1014～9×1014cm-3The crystal orientation is (100) P type SOI substrate, and the material of the top layer is polysilicon with the thickness of 100 μm.
In one embodiment of the present invention, step (b) comprises:
(b1) depositing a SiN material on the SOI substrate by using a CVD (chemical vapor deposition) process to form a protective layer; (b2) forming a first active area groove pattern on the surface of the protective layer by utilizing a photoetching process;
(b3) etching the protective layer and the SOI substrate by using a dry etching process to form the first active region groove in the SOI substrate;
(b4) forming a second active area groove pattern on the surface of the protective layer by utilizing a photoetching process;
(b5) and etching the protective layer and the SOI substrate by using a dry etching process to form the second active region groove in the SOI substrate.
In one embodiment of the present invention, step (c) comprises:
(c1) growing first SiO on the surface of the first active area groove and the second active area groove by using CVD process2A layer;
(c2) by wet methodAn etching process for removing the first SiO layer in the first designated region2A layer; (c3) growing and forming a first P area and a second P area at the first designated area by utilizing an in-situ doping process;
(c4) carrying out flattening treatment on the first P area and the second P area by using a dry etching process;
(c5) removing the first SiO by wet etching process2And (3) a layer.
In one embodiment of the present invention, before the step (c1), the method further comprises:
(c11) oxidizing the side walls of the first active area groove and the second active area groove by using an oxidation process to form an oxidation layer;
(c12) and etching the oxide layer by utilizing a wet etching process to finish the planarization treatment of the side walls of the first active area groove and the second active area.
In one embodiment of the present invention, step (d) comprises:
(d1) growing a second SiO on the surface of the first active area groove and the second active area groove by using a CVD process2A layer;
(d2) removing the second SiO in the second designated area by wet etching process2A layer;
(d3) growing and forming the first N region and the second N region in the second designated region by utilizing an in-situ doping process;
(d4) carrying out planarization treatment on the first N region and the second N region by using a dry etching process;
(d5) removing the second SiO by wet etching process2And (3) a layer.
In one embodiment of the present invention, before step (f), further comprising:
(x1) depositing a third SiO region over the entire device surface including the SOI substrate, the first P region, the second P region, the first N region and the second N region using a CVD process2A layer;
(x2) performing impurity activation treatment on the first P region, the first N region and the second N region at 950-1150 ℃ by using an annealing process;
(x3) etching the third SiO using an etching process2And forming a side wall protection region on the side wall of the second active region groove.
In one embodiment of the present invention, step (x3) comprises:
(x31) using a photolithographic process on the third SiO2Forming a first active area groove pattern on the surface of the layer; (x32) etching the third SiO by a dry etching process2A layer;
(x33) using a photolithographic process on the third SiO2Forming a side wall protection area pattern on the surface of the layer;
(x34) etching the third SiO by a dry etching process2And forming the side wall protection region on the side wall of the second active region groove.
In one embodiment of the present invention, step (f) comprises:
(f1) forming a lead hole in the third designated area by using a photoetching process;
(f2) sputtering metal at the lead hole position by using a sputtering process to form the lead;
(f3) passivating and lithographically printing the PAD to form the PiN diode.
Another embodiment of the present invention provides a high power PiN diode prepared by the method of any of the above embodiments.
Compared with the prior art, the invention has the following beneficial effects:
1) the invention adopts the design of two layers of grooves, and when the direct current bias voltage is applied, the current carriers in the intrinsic region are distributed more uniformly, thereby greatly improving the performance of the device.
2) The invention has simple process and high feasibility.
Drawings
The following detailed description of embodiments of the invention will be made with reference to the accompanying drawings.
Fig. 1 is a flowchart of a method for manufacturing a high power PiN diode according to an embodiment of the present invention;
fig. 2 a-fig. 2r are schematic diagrams illustrating a method for manufacturing a high power PiN diode according to an embodiment of the invention;
fig. 3 is a schematic structural diagram of a high-power PiN diode according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but the embodiments of the present invention are not limited thereto.
Example 1:
referring to fig. 1, fig. 1 is a flowchart of a method for manufacturing a high-power PiN diode according to an embodiment of the present invention, where the method includes:
(a) selecting an SOI substrate;
(b) etching the SOI substrate by utilizing an etching process to form a first active area groove and a second active area groove on two sides of the Pin diode to be prepared;
(c) respectively forming a first P area and a second P area in the first designated area of the first active area groove and the second active area groove by utilizing an in-situ doping process;
(d) respectively forming a first N area and a second N area in a second designated area of the first active area groove and the second active area groove by utilizing an in-situ doping process;
(e) carrying out surface planarization treatment on the whole device comprising the SOI substrate, the first P region, the second P region, the first N region and the second N region by utilizing a CMP (chemical mechanical polishing) process;
(f) and manufacturing leads in third designated areas of the first active area groove and the second active area groove to finish the preparation of the Pin diode.
Preferably, step (a) may comprise:
selecting the doping concentration to be 1 × 1014～9×1014cm-3The crystal orientation is (100) P type SOI substrate, and the material of the top layer is polysilicon with the thickness of 100 μm.
Preferably, step (b) may comprise:
(b1) depositing a SiN material on the SOI substrate by using a CVD (chemical vapor deposition) process to form a protective layer; (b2) forming a first active area groove pattern on the surface of the protective layer by utilizing a photoetching process;
(b3) etching the protective layer and the SOI substrate by using a dry etching process to form the first active region groove in the SOI substrate;
(b4) forming a second active area groove pattern on the surface of the protective layer by utilizing a photoetching process;
(b5) and etching the protective layer and the SOI substrate by using a dry etching process to form the second active region groove in the SOI substrate.
Preferably, step (c) may comprise:
(c1) growing first SiO on the surface of the first active area groove and the second active area groove by using CVD process2A layer;
(c2) removing the first SiO in the first designated area by wet etching process2A layer; (c3) growing and forming a first P area and a second P area at the first designated area by utilizing an in-situ doping process;
(c4) carrying out flattening treatment on the first P area and the second P area by using a dry etching process;
(c5) removing the first SiO by wet etching process2And (3) a layer.
Preferably, step (c1) may be preceded by:
(c11) oxidizing the side walls of the first active area groove and the second active area groove by using an oxidation process to form an oxidation layer;
(c12) and etching the oxide layer by utilizing a wet etching process to finish the planarization treatment of the side walls of the first active area groove and the second active area.
Preferably, step (d) may comprise:
(d1) growing a second SiO on the surface of the first active area groove and the second active area groove by using a CVD process2A layer;
(d2) removing the second SiO in the second designated area by wet etching process2A layer;
(d3) growing and forming the first N region and the second N region in the second designated region by utilizing an in-situ doping process;
(d4) carrying out planarization treatment on the first N region and the second N region by using a dry etching process;
(d5) removing the second SiO by wet etching process2And (3) a layer.
Preferably, step (f) may be preceded by:
(x1) depositing a third SiO region over the entire device surface including the SOI substrate, the first P region, the second P region, the first N region and the second N region using a CVD process2A layer;
(x2) performing impurity activation treatment on the first P region, the first N region and the second N region at 950-1150 ℃ by using an annealing process;
(x3) etching the third SiO using an etching process2And forming a side wall protection region on the side wall of the second active region groove.
Preferably, step (x3) may include:
(x31) using a photolithographic process on the third SiO2Forming a first active area groove pattern on the surface of the layer; (x32) etching the third SiO by a dry etching process2A layer;
(x33) using a photolithographic process on the third SiO2Forming a side wall protection area pattern on the surface of the layer;
(x34) etching the third SiO by a dry etching process2And forming the side wall protection region on the side wall of the second active region groove.
Preferably, step (f) may comprise:
(f1) forming a lead hole in the third designated area by using a photoetching process;
(f2) sputtering metal at the lead hole position by using a sputtering process to form the lead;
(f3) passivating and lithographically printing the PAD to form the PiN diode.
In the embodiment, by adopting the design of two layers of grooves, when a direct current bias voltage is applied, the current carriers in the intrinsic region are distributed more uniformly, and the performance of the device is greatly improved.
Example 2:
referring to fig. 2a to fig. 2r, fig. 2a to fig. 2r are schematic diagrams of a method for manufacturing a high power PiN diode according to an embodiment of the present invention, the method includes the following steps:
referring to fig. 2a to fig. 2r, fig. 2a to fig. 2r are schematic diagrams of a method for manufacturing a lateral double-channel power PiN diode according to an embodiment of the present invention, the method includes the following steps:
step 1, selecting an SOI substrate 001 as shown in FIG. 2 a;
step 2, growing a silicon nitride layer 002 on the SOI substrate 001 by using a CVD process, as shown in FIG. 2 b;
step 3, forming a groove pattern area on the surface of the silicon nitride layer 002 by utilizing a photoetching process; etching the silicon nitride layer 002 and the SOI substrate 001 in the trench pattern region by using a dry etching process to form a first active region trench 003 and a second active region trench 004, as shown in fig. 2 c;
step 4, oxidizing the sidewalls of the first active region trench 003 and the second active region trench 004 to form an oxide layer 005, as shown in fig. 2 d;
step 5, etching the oxide layer 005 by using a wet etching process to flatten the first active area trench 003 and the second active area trench 004, as shown in fig. 2 e;
step 6, growing first SiO on the whole material surface by using CVD process2Layer 006, as shown in FIG. 2 f;
and 7, selectively etching the first SiO by using a wet etching process2Layer 006, forming the P-type active region to be grown region, as shown in fig. 2 g;
step 8, growing a first P region 007 and a second P region 008 in a region to be grown in the P type active region by using an in-situ doping process, as shown in FIG. 2 h;
step 9, performing planarization treatment on the surfaces of the first P region 007 and the second P region 008 by using a dry etching process; removing the first SiO by wet etching process2Layer 006, shown in FIG. 2 i; step 10, growing a second SiO on the whole material surface by using CVD process2Layer 009, as shown in fig. 2 j;
step 11, selectively etching the second SiO by using a wet etching process2Layer 009, forming an N-type active area to be grown region, as shown in fig. 2 k;
step 12, growing a first N region 010 and a second N region 011 in a region to be grown in the N-type active region by utilizing an in-situ doping process, as shown in FIG. 2 l;
step 13, carrying out planarization treatment on the surfaces of the first N region 010 and the second N region 011 by using a dry etching process; removing the second SiO by wet etching process2Layer 009, as shown in fig. 2 m; step 14, removing the silicon nitride layer 002 and a part of the polysilicon layer on the surface of the substrate by using a CMP process to flatten the whole material surface, as shown in FIG. 2 n;
step 15, growing a third SiO on the surface of the whole material including the SOI substrate 001 by CVD process2Layer 012, as shown in fig. 2 o;
step 16, activating impurities in the first P region 007, the second P region 008, the first N region 010 and the second N region 011 by an annealing process at the temperature of 950-;
step 17, selectively etching the third SiO by using a wet etching process2Layer, forming a wire hole 013, as shown in fig. 2 p;
step 18, sputtering Au material on the area of the lead hole 013 to form a lead 014 as shown in FIG. 2 q;
at step 19, a silicon nitride passivation layer 015 is grown over the surface of the entire material including the lead 014, as shown in fig. 2 r.
EXAMPLE III
Referring to fig. 3, fig. 3 is a schematic structural diagram of a high power PiN diode according to an embodiment of the present invention. The light emitting tube was fabricated using the fabrication method shown in fig. 2 a-2 r. Specifically, the diode includes: SOI substrate 301, first P region 302, second P region 303, first N region 304, second N region 305, lead 306, and silicon nitride passivation layer 307.
The foregoing is a more detailed description of the invention in connection with specific preferred embodiments and it is not intended that the invention be limited to these specific details. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A preparation method of a high-power Pin diode is characterized by comprising the following steps:
(a) selecting an SOI substrate;
(b) etching the SOI substrate by utilizing an etching process to form a first active area groove and a second active area groove on two side walls of the PiN diode to be prepared, wherein the first active area groove is positioned on the second active area groove;
(c) respectively forming a first P area and a second P area in a first designated area of the first active area groove and a first designated area of the second active area groove by utilizing an in-situ doping process, wherein the first P area is positioned on the first active area groove on one side, and the second P area is positioned in the second active area groove on the same side as the first P area;
(d) respectively forming a first N area and a second N area in a second designated area of the first active area groove and the second active area groove by utilizing an in-situ doping process, wherein the first N area is positioned on the first active area groove on the other side, and the second N area is positioned in the second active area groove on the same side as the first N area;
(e) carrying out surface planarization treatment on the whole device comprising the SOI substrate, the first P region, the second P region, the first N region and the second N region by utilizing a CMP (chemical mechanical polishing) process;
(f) and manufacturing leads in third designated areas of the first active area groove and the second active area groove to finish the preparation of the Pin diode.
2. The method of claim 1, wherein step (a) comprises:
selecting the doping concentration to be 1 × 1014～9×1014cm-3The crystal orientation is (100) P type SOI substrate, and the material of the top layer is polysilicon with the thickness of 100 μm.
3. The method of claim 1, wherein step (b) comprises:
(b1) depositing a SiN material on the SOI substrate by using a CVD (chemical vapor deposition) process to form a protective layer; (b2) forming a first active area groove pattern on the surface of the protective layer by utilizing a photoetching process;
(b3) etching the protective layer and the SOI substrate by using a dry etching process to form the first active region groove in the SOI substrate;
(b4) forming a second active area groove pattern on the surface of the protective layer by utilizing a photoetching process;
(b5) and etching the protective layer and the SOI substrate by using a dry etching process to form the second active region groove in the SOI substrate.
4. The method of claim 1, wherein step (c) comprises:
(c1) growing first SiO on the surface of the first active area groove and the second active area groove by using CVD process2A layer;
(c2) removing the first SiO in the first designated area by wet etching process2A layer; (c3) growing and forming a first P area and a second P area at the first designated area by utilizing an in-situ doping process;
(c4) carrying out flattening treatment on the first P area and the second P area by using a dry etching process;
(c5) removing the first SiO by wet etching process2And (3) a layer.
5. The method of claim 4, wherein prior to step (c1), further comprising:
(c11) oxidizing the side walls of the first active area groove and the second active area groove by using an oxidation process to form an oxidation layer;
(c12) and etching the oxide layer by utilizing a wet etching process to finish the planarization treatment of the side walls of the first active area groove and the second active area.
6. The method of claim 1, wherein step (d) comprises:
(d1) growing a second SiO on the surface of the first active area groove and the second active area groove by using a CVD process2A layer;
(d2) removing the second SiO in the second designated area by wet etching process2A layer;
(d3) growing and forming the first N region and the second N region in the second designated region by utilizing an in-situ doping process;
(d4) carrying out planarization treatment on the first N region and the second N region by using a dry etching process;
(d5) removing the second SiO by wet etching process2And (3) a layer.
7. The method of claim 1, further comprising, prior to step (f):
(x1) depositing a third SiO region over the entire device surface including the SOI substrate, the first P region, the second P region, the first N region and the second N region using a CVD process2A layer;
(x2) performing impurity activation treatment on the first P region, the first N region and the second N region at 950-1150 ℃ by using an annealing process;
(x3) etching the third SiO using an etching process2And forming a side wall protection region on the side wall of the second active region groove.
8. The method of claim 7, wherein step (x3) comprises:
(x31) using a photolithographic process on the third SiO2Forming a first active area groove pattern on the surface of the layer; (x32) Using DryA method etching process for etching the third SiO2A layer;
(x33) using a photolithographic process on the third SiO2Forming a side wall protection area pattern on the surface of the layer;
(x34) etching the third SiO by a dry etching process2And forming the side wall protection region on the side wall of the second active region groove.
9. The method of claim 1, wherein step (f) comprises:
(f1) forming a lead hole in the third designated area by using a photoetching process;
(f2) sputtering metal at the lead hole position by using a sputtering process to form the lead;
(f3) passivating and lithographically printing the PAD to form the PiN diode.
10. A high power PiN diode prepared by the method of any one of claims 1 to 9.
Priority Applications (1)
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