CN1069150C - Method for fabricating semiconductor device - Google Patents

Abstract

A method for forming a semiconductor device is provided. According to this method, a semiconductor device is manufactured by forming bit lines in such a manner that a silicide film surrounds the upper portion and side walls of a polysilicon pattern, and only the sides are surrounded by the polysilicon layer pattern. Compared with conventional bit lines made of polysilicon or silicide alone, the resistance of the bit line composed of polysilicon and silicide is reduced by 50% or more, resulting in improved reliability of device operation. It is beneficial to the high integration of semiconductor devices, and this method can allow a large process tolerance between the bit line and its contact hole, thereby improving the yield rate of production.

Description

Method for manufacturing semiconductor device

The present invention relates generally to methods for fabricating semiconductor devices, and more particularly to improving the electrical resistance of wires.

A typical sheet resistance of a doped polysilicon layer commonly used as a wire in a semiconductor device is about 30 to 70 Ω/□. Its contact resistance is also on the order of 30 to 70Ω/□ per contact. This sheet resistance and contact resistance cause a significant drop in the operating speed of the semiconductor device. In order to reduce sheet resistance and contact resistance, a salicide method or a method of selectively depositing a metal thin film has been used. According to such methods, a metal silicide film or a selective metal film is formed only on a wire. For example, where Ti silicide or selectively W is formed on the polysilicon layer pattern, the sheet resistance and contact resistance are significantly reduced to about 5Ω/□ and 3Ω/□ per contact, respectively. Also this method can reduce the size of the contact between the upper and lower wires and the distance between the contact and the adjacent wire, and the aspect ratio of the contact hole, that is, the ratio of diameter to height can be increased. Therefore, such reduced resistance allows reduction of process tolerances, prevents delays in operating times in semiconductor devices and enables them to be highly integrated.

For high integration of semiconductor devices, a method has been considered in which wirings such as gate electrodes and bit lines are narrowed. However, the n-fold reduction in the width of the wire leads to an n-fold increase in its resistance, which is detrimental to the operating speed of the semiconductor device. In addition, in order to keep the contact holes at a distance from each other, different factors must be carefully considered, including misalignment tolerance in mask alignment, lens deviation in exposure, critical dimension variation of the mask in photolithography for them, and Alignment between masks is included. Therefore, the size of the contact holes themselves has to be larger and the distance therebetween is larger, thus making it difficult to highly integrate the semiconductor device. It is practically impossible to form fine contact holes of 0.4 µm or less with currently used equipment.

In order to better understand the background of the present invention, a conventional method of manufacturing a semiconductor device will be described with reference to some drawings.

Referring to FIG. 1, a process for forming bitlines and bitline contacts is shown.

A first insulating film 1 is formed on the structure (not shown) of FIG. 1A having element isolation oxide films and MOS transistors formed on a silicon wafer. Then, an impurity-doped polysilicon layer 2 is formed on the first insulating film 1, followed by a metal layer 3 which can be transformed into silicide. Thereafter, the metal layer 3 is covered with an acrylic layer serving as an anti-reflection film 4 to prevent divergent reflections caused by the metal layer-metal silicide film during irradiation treatment. Finally, as shown in FIG. 1A , the anti-reflection film 4 is extended to the polysilicon layer 2 for photolithographic shaping in order to form anti-reflection film patterns, metal layer patterns and polysilicon layer patterns.

FIG. 1B illustrates the remaining processes for forming bit lines and their contact holes. First, the photolithographically shaped metal layer 3 is transformed into silicide by heat treatment. Thus, the obtained silicide film 5 constitutes the bit line 6 connected with the pattern of the underlying polysilicon layer 2 . After the antireflection film 4 is removed, a second insulating film 7 is formed on the obtained structure, and then a predetermined area is opened to form a contact hole 8 . Here, assuming that the width of the metal silicide film representing the resistance of the bit line 6 is "a", the diameter of the contact hole 8 is "f", the process tolerance between the contact hole 8 and the bit line 6 should be "(a-f) /2".

According to such a conventional method of manufacturing a semiconductor device as shown in FIGS. 1A and 1B , an anti-reflection film is required to prevent divergent reflections caused by metal layers, thereby reducing process tolerances between bit lines and contact holes. Thus, small process tolerances necessitate complex processes to prevent this real problem and make it difficult to highly integrate semiconductor devices. In addition, the bit line, having a significant thickness, was found to create a difficult troublesome step in the subsequent process, thereby degrading the yield and operational reliability of the semiconductor device.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to overcome the above-mentioned problems encountered in the prior art and to provide a method of manufacturing a semiconductor device useful for high integration of the semiconductor device.

Another object of the present invention is to provide a method for manufacturing a semiconductor device which allows a large process tolerance between bit lines and contact holes and provides a high operating speed for the semiconductor device.

Still another object of the present invention is to provide a method for manufacturing a semiconductor device by which bit lines can be formed without taking into consideration the divergent reflection of light.

The present invention is based on the discovery that by surrounding the silicide on the side of a polysilicon pattern with silicide, a thin bit line with low resistance can be formed.

According to one aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method comprises the steps of: forming a first insulating film on a semiconductor substrate; forming a pattern of a polysilicon layer on the first insulating film; depositing a metal layer on the surface of the pattern of the polysilicon layer; heat-treating the metal layer and the polysilicon layer, to form a silicide film used as a bit line; and form a contact hole by coating a second insulating film on the bit line and performing photolithography on the second insulating film.

According to another aspect of the present invention, a method for manufacturing a semiconductor device is provided. The method comprises the following steps: forming a first insulating film on a semiconductor substrate; forming a polysilicon layer and a second insulating film on the first insulating film 1 in sequence, and performing photolithographic shaping on the polysilicon layer and the second insulating film; The pattern is coated with a metal layer so that the photolithographically shaped polysilicon layer will contact the metal layer at its sidewalls and react the metal layer with the polysilicon layer to form silicide at the sidewalls of the photolithographically shaped polysilicon layer ; remove the unreacted metal layer to form a bit line composed of silicide and polysilicon layer patterns; coat the obtained structure with a third insulating film, and open in predetermined areas of the second and third insulating films to form Contact holes for bit lines.

Other objects and aspects of the present invention will become apparent from the following description of embodiments when taken in conjunction with reference to the accompanying drawings, in which:

1A and 1B are cross-sectional views illustrating a conventional method of manufacturing a semiconductor device;

2A to 2E are step-by-step cross-sectional views illustrating a method of fabricating a semiconductor device according to an embodiment of the present invention; and

3A to 3E are cross-sectional views illustrating steps in a method of fabricating a semiconductor device according to another embodiment of the present invention.

The application of the preferred embodiment of the present invention may be better understood with reference to the accompanying drawings, wherein like numerals are used for like and corresponding parts, respectively.

Referring to FIG. 2, there is shown a step-by-step process for fabricating a semiconductor device in accordance with the present invention.

In FIG. 2A, the entire upper surface of a structure (not shown, which includes an element isolation oxide film, a gate oxide film, and a series of gates and source/drain electrodes on a semiconductor substrate) A first insulating film 1 is formed. The first insulating film 1 can be a single-layer oxide film, borophosphosilicate glass (hereinafter referred to as "BPSG") or tetraethylorthosilicate (hereinafter referred to as "TEOS"), or a composite of TEOS-low temperature oxide-BPSG thing. Then, a polysilicon layer 2 is coated on the surface of the first insulating film 1 by chemical vapor deposition (hereinafter referred to as "CVD"), and then it is photolithographically shaped to form a pattern of the polysilicon layer 2 having a width "a".

Next, as shown in FIG. 2B, the obtained structure is coated with a metal layer 3 which can become silicided. Examples of such metal layers include Mo, Ta, Cr, W, Nb or Ti.

Thereafter, as shown in FIG. 2C, the metal layer 3 for silicide reacts with the pattern of the polysilicon layer 2 by heat-treating the semiconductor substrate to form a metal silicide film 5 surrounding the patterned surface of the polysilicon layer 2. Thus, the metal silicide film together with the polysilicon layer 2 constitutes a bit line wider than the pattern of the polysilicon layer 2 (ie, the width (b) of the bit line is larger than the width (a) of the pattern). At this time, the thickness of the silicide film 5 can be adjusted by the thickness of the metal layer 3 .

As shown in FIG. 2D , in order to complete the formation of the bit line 6 , the unreacted metal layer 3 left around the first insulating film 1 is removed by isotropic etching. At this time, the thickness of the bit line 6 is greater than the thickness of the pattern of the polysilicon layer 2 .

A second insulating film 7 made of oxide, BPSG or TEOS is formed on the obtained structure, and finally it is opened by photolithography at a region where a metal wire contact is formed. Accordingly, as shown in FIG. 2E, a contact hole having a diameter f is formed. Therefore, the process tolerance ((b-f)/2) between the bit line 6 and the contact hole 8 is larger than that of the conventional method because the width (b) of the bit line 6 is larger than the width (a) of the conventional method.

Turning to FIG. 3, it illustrates step-by-step processes for fabricating a semiconductor device in which a silicide film is formed only on sidewalls of bit lines in accordance with another embodiment of the present invention.

In FIG. 3A, a first insulating film 1 is formed on a structure (not shown, which includes an element isolation oxide film and a MOS transistor on a semiconductor substrate), and then a polysilicon film is sequentially formed on the first insulating film 1 by CVD. layer 2 and a second insulating film 7. Both the second insulating film 7 and the polysilicon layer 2 are photolithographically patterned to form a stack of width "a" reserved for bit lines.

Next, as shown in FIG. 3B, the obtained structure is coated with a metal layer 3 which can be silicided. Examples of the metal layer include Mo, Ta, Cr, W, Nb or Ti. As a result, the metal layer is in contact with the pattern of the polysilicon layer 2 at its side walls, not at its upper surface.

Thereafter, as shown in FIG. 3C, by heat-treating the semiconductor substrate, the metal layer 3 used for silicide reacts with the pattern of the polysilicon layer 2 at the contact region, and a metal silicide film 5 is formed at the sidewall of the pattern of the polysilicon layer 2. . Thus, the metal silicide film 5 together with the polysilicon layer 2 constitutes a bit line wider than the pattern of the polysilicon layer 2 (ie, the width (b) of the bit line is larger than the width (a) of the pattern). In this case, the thickness of the silicide film 5 can be adjusted by the thickness of the metal layer 3 .

As shown in FIG. 3D, in order to complete the formation of the bit line 6, the unreacted metal layer 3 left around the first and second insulating films 1 and 7 is removed by isotropic etching. At this time, the bit line 6 is as thick as the pattern of the polysilicon layer 2 .

As shown in FIG. 3E, a third insulating film 9 is formed on the obtained structure. A contact hole with a diameter f is formed by photolithographically opening predetermined areas on the third and second insulating films 9 and 7 for contacting metal wires. Therefore, the process tolerance ((b-f)/2) between the bit line 6 and the contact hole 8 is larger than that in the conventional method because the width (b) of the bit line 6 is larger than the width (a) in the conventional method.

As described below, according to the present invention, the bit lines are formed in such a manner that the silicide film may surround the upper portion and side walls of the polysilicon layer, or may be in contact with only the side walls of the polysilicon layer. The resistance of the obtained bit line was shown to be 50% or less of that of a conventional bit line formed only of a polysilicon layer or a silicide layer. Therefore, the reliability of the semiconductor device manufactured according to the present invention is improved, and thus the high integration of the semiconductor device is greatly improved. Also the method of the present invention significantly improves the production yield due to the large process tolerance caused by the widening of the bit lines.

The present invention has been described by way of illustration, and it is to be understood that the terminology employed is for the purpose of description rather than limitation.

Many modifications and variations of the present invention are possible in light of the above teachings. It is therefore to be understood that within the scope of the appended claims, the invention may be used otherwise than as specifically described.

Claims (3)

1. A method for manufacturing a semiconductor device, comprising the steps of: forming a first insulating film on the semiconductor substrate; forming a polysilicon layer on the first insulating film and shaping the polysilicon layer by photolithography; A metal layer is coated on the pattern obtained so that the shaped polysilicon layer is in contact with the metal layer at its upper surface and side walls, and the metal layer is reacted with the polysilicon so that the shaped polysilicon layer is formed on the upper surface and sidewalls. Silicide formation at the wall; removing the metal layer that has not reacted with the shaped polysilicon layer to form a bitline comprised of the silicide and the shaped polysilicon layer, the bitline having a width greater than the width of the shaped polysilicon layer; coating the obtained structure with a second insulating film; and The second insulating film is opened in a predetermined area to form a contact hole for a bit line. 2. The method according to claim 1, wherein said silicide film is made of a metal selected from the group consisting of Mo, Ta, Cr, W, Nb and Ti. 3. A method for manufacturing a semiconductor device, comprising the steps of: forming a first insulating film on the semiconductor substrate; sequentially forming a polysilicon layer and a second insulating film on the first insulating film, and forming the polysilicon layer and the second insulating film by photolithography; A metal layer is coated on the obtained pattern so that the shaped polysilicon layer is in contact with the metal layer at its side wall, and a part of the metal layer in contact with the polysilicon reacts with the polysilicon to form a polysilicon layer on the side wall of the formed polysilicon layer. Formation of silicide; removing the metal layer that has not reacted with the shaped polysilicon layer to form a bitline comprised of the silicide and the shaped polysilicon layer, the bitline having a width greater than the width of the shaped polysilicon layer; coating the obtained structure with a third insulating film; and The second and third insulating films are opened at predetermined regions to form contact holes for bit lines.

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