CN106896592B - Liquid crystal display panel and display device - Google Patents
Liquid crystal display panel and display device Download PDFInfo
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- CN106896592B CN106896592B CN201710078600.3A CN201710078600A CN106896592B CN 106896592 B CN106896592 B CN 106896592B CN 201710078600 A CN201710078600 A CN 201710078600A CN 106896592 B CN106896592 B CN 106896592B
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1343—Electrodes
- G02F1/134309—Electrodes characterised by their geometrical arrangement
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/1333—Constructional arrangements; Manufacturing methods
- G02F1/1345—Conductors connecting electrodes to cell terminals
- G02F1/13452—Conductors connecting driver circuitry and terminals of panels
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- G—PHYSICS
- G02—OPTICS
- G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
Abstract
The invention provides a liquid crystal display panel, which comprises an array substrate and a color film substrate, wherein the array substrate is provided with a substrate wire and a plurality of gate electrode flip-chip films, the surface of the color film substrate is provided with a common electrode layer, the area of the common electrode layer, which covers the substrate wire, is provided with a hollow structure, so that the area of the common electrode layer, which is projected to the edge area of the array substrate, is reduced, and the capacitance value between the common electrode layer and the substrate wire is adjusted; the beneficial effects are that: according to the liquid crystal display panel, the capacitance value between the common electrode layer and the substrate wiring is changed through the hollow structure on the common electrode, the resistance value difference is counteracted, and the technical problem that the voltage input into the panel is different due to the resistance value difference, so that the display phenomenon of the horizontal block is poor is solved.
Description
Technical Field
The invention relates to the technical field of liquid crystal display, in particular to a liquid crystal display panel and a display device with the same.
Background
With the development of display technology, liquid crystal displays have become the most common flat panel display devices. In the liquid crystal display, each pixel is controlled by gate lines and data lines which are crisscrossed on a substrate to realize display of an image.
At present, in order to save cost, a Gate driving circuit and a data circuit are often fabricated On the same printed circuit board, and then the circuit board is connected to a Gate Chip On Film (G-COF) for transmitting a Gate driving signal by using a Wire On Array (WOA). At least two COFs for transmitting gate driving signals are generally included in the liquid crystal display, and adjacent COFs are also connected by a WOA. Each COF is respectively connected with a group of fan-out wirings (fanout) on the substrate and is connected to each grid line through the fanout.
Since the WOA has a certain resistance value, the resistance value of the gate line connected to the subsequent COF is greater than that of the gate line connected to the previous COF, so that the waveforms of the gate driving signals on the two gate lines are different. The difference in the waveforms of the gate driving signals at the intersection of two COFs, that is, the last gate line connected to the previous COF and the first gate line connected to the next COF, is particularly obvious. Particularly, after a high temperature and high humidity reliability test, a characteristic curve of a Thin Film Transistor (TFT) may be shifted, a leakage current may be increased or a charging may be insufficient, and the waveform difference may be more significant, which may cause a linear bright spot or dark spot (mura), i.e., a horizontal block defect (H-block), to occur at a boundary of a COF of a liquid crystal display.
In summary, in the conventional lcd panel, due to the resistance difference between the substrate traces and the fan-out traces of the panel, the signal delays at different positions of the panel are different, which causes the voltage difference input into the panel, and thus causes the horizontal area defect, which affects the display effect of the lcd.
Disclosure of Invention
The invention provides a liquid crystal display panel, which adjusts the capacitance values of substrate routing and fan-out routing by changing the area of the common electrode edge area covering on an array substrate so as to offset the resistance value difference, and solves the problem that the voltage difference input into the panel is caused by the resistance value difference, so that the display phenomenon of poor horizontal blocks is caused.
In order to solve the above problems, the technical scheme provided by the invention is as follows:
the invention provides a liquid crystal display panel, comprising:
a color film substrate, wherein a common electrode layer is prepared on the surface of the color film substrate;
the array substrate is positioned on the opposite side of the color film substrate;
the array substrate edge region includes:
the driving circuit board is positioned on the upper side of the array substrate and comprises a grid driving circuit and a data circuit;
the gate electrode chip on films are positioned on the left side and the right side of the array substrate, the gate electrode chip on film positioned at the uppermost end is connected to the driving circuit board through substrate wires, and the adjacent gate electrode chip on films positioned on the same side are connected through the substrate wires;
the input end of each fan-out wire is connected with a gate electrode chip on film, and the output end of the fan-out wire is connected with a scanning line;
the substrate routing lines are arranged along the outer sides of the fan-out routing lines;
the array substrate comprises a substrate, a common electrode layer and a substrate wire, wherein a plurality of hollow structures are formed on two sides of the common electrode layer, so that the area of the common electrode layer projected on the edge area of the array substrate is reduced, and the capacitance value between the common electrode layer and the substrate wire is adjusted.
According to a preferred embodiment of the present invention, the hollow structure includes a portion covering all of the substrate routing area.
According to a preferred embodiment of the present invention, the hollow structure further includes portions corresponding to the fan-out routing areas of each group.
According to a preferred embodiment of the present invention, the hollow structure is a hole left by digging part of the electrode on the common electrode, the hole forms a plurality of electrode patterns on the common electrode, and the shape of the electrode patterns is approximately isosceles triangle rotated by 90 degrees.
According to a preferred embodiment of the present invention, one of the electrode patterns overlaps a corresponding one of the fan-out traces, wherein the electrode pattern covers areas of the traces on upper and lower sides of the fan-out trace and is related to a position of the fan-out trace on the array substrate.
According to a preferred embodiment of the present invention, the area of the plurality of sets of fan-out traces on the array substrate is larger than the area of the electrode pattern corresponding to the fan-out trace in the previous set, relative to the electrode pattern corresponding to the fan-out trace in the next set.
According to a preferred embodiment of the present invention, the electrode patterns on the left and right sides of the common electrode layer are symmetrically disposed.
According to the above object of the present invention, there is provided a liquid crystal display device comprising:
a liquid crystal display panel;
the backlight module is positioned on the opposite surface of the liquid crystal display panel;
the liquid crystal display panel includes:
a color film substrate, wherein a common electrode layer is prepared on the surface of the color film substrate;
the array substrate is positioned on the opposite side of the color film substrate;
the array substrate edge region includes:
the driving circuit board is positioned on the upper side of the array substrate and comprises a grid driving circuit and a data circuit;
the gate electrode chip on films are positioned on the left side and the right side of the array substrate, the gate electrode chip on film positioned at the uppermost end is connected to the driving circuit board through substrate wires, and the adjacent gate electrode chip on films positioned on the same side are connected through the substrate wires;
the input end of each fan-out wire is connected with a gate electrode chip on film, and the output end of the fan-out wire is connected with a scanning line;
the substrate routing lines are arranged along the outer sides of the fan-out routing lines;
the array substrate comprises a substrate, a common electrode layer and a substrate wire, wherein a plurality of hollow structures are formed on two sides of the common electrode layer, so that the area of the common electrode layer projected on the edge area of the array substrate is reduced, and the capacitance value between the common electrode layer and the substrate wire is adjusted.
According to a preferred embodiment of the present invention, the hollow structure includes a portion covering all of the substrate routing area.
According to a preferred embodiment of the present invention, the hollow structure further includes portions corresponding to the fan-out routing areas of each group.
According to a preferred embodiment of the present invention, the hollow structure is a hole left by digging part of the electrode on the common electrode, the hole forms a plurality of electrode patterns on the common electrode, and the shape of the electrode patterns is approximately isosceles triangle rotated by 90 degrees.
According to a preferred embodiment of the present invention, one of the electrode patterns overlaps a corresponding one of the fan-out traces, wherein the electrode pattern covers areas of the traces on upper and lower sides of the fan-out trace and is related to a position of the fan-out trace on the array substrate.
According to a preferred embodiment of the present invention, the area of the plurality of sets of fan-out traces on the array substrate is larger than the area of the electrode pattern corresponding to the fan-out trace in the previous set, relative to the electrode pattern corresponding to the fan-out trace in the next set.
According to a preferred embodiment of the present invention, the electrode patterns on the left and right sides of the common electrode layer are symmetrically disposed.
The invention has the beneficial effects that: compared with the liquid crystal display panel in the prior art, the liquid crystal display panel has the advantages that the hollow structures are formed on the two sides of the common electrode layer, the area of the edge area of the common electrode layer projected on the array substrate is reduced, capacitance values between the common electrode layer and substrate wiring and between the common electrode layer and fan-out wiring are changed, resistance value difference is offset, and the display phenomenon that voltage input into the panel is different due to the resistance value difference and horizontal blocks are poor is solved.
Drawings
In order to illustrate the embodiments or the technical solutions in the prior art more clearly, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the invention, and it is obvious for a person skilled in the art that other drawings can be obtained according to these drawings without creative efforts.
FIG. 1 is a schematic diagram of a conventional array substrate structure;
FIG. 2 is a schematic diagram of a common electrode layer of the LCD panel according to the present invention;
FIGS. 3a and 3b are schematic diagrams of single electrode pattern structures of the LCD panel of the present invention.
Detailed Description
The following description of the various embodiments refers to the accompanying drawings that illustrate specific embodiments in which the invention may be practiced. The directional terms mentioned in the present invention, such as [ upper ], [ lower ], [ front ], [ rear ], [ left ], [ right ], [ inner ], [ outer ], [ side ], are only referring to the directions of the attached drawings. Accordingly, the directional terms used are used for explanation and understanding of the present invention, and are not used for limiting the present invention. In the drawings, elements having similar structures are denoted by the same reference numerals.
Aiming at the existing liquid crystal display panel, the resistance value difference between the substrate routing and the fan-out routing of the panel causes the signal delay at different positions of the panel to be different, so that the voltage input into the panel is different, and further the horizontal block defect is caused.
The signal delay (RC delay) is a most basic phenomenon in the circuit science, when the circuit is composed of a resistor and a capacitor, if the potential at the point a is instantaneously changed from V1 to V2, the potential change at the point B is delayed due to the effect of the resistor (R) and the capacitor (C) in the circuit, and the voltage change relationship thereof shows an exponential change with time, and the specific formula is as follows: VB is V2- (V2-V1) exp [ -t/(RC) ], and as can be seen from the formula, the product of R and C is a voltage change factor, and the change of C can be compensated for the waveform of delay caused by the change of the resistance R. In other words, when the input waveform is abnormal due to the increase of the resistor R in the circuit, the waveform can be restored by reducing the capacitor C in the circuit.
Fig. 1 is a schematic structural diagram of a conventional array substrate.
As shown in fig. 1, the array substrate 101 includes a display region 102, and a peripheral region 103 located outside the display region 102; the peripheral region 103 includes: a driving circuit board 104, located on the upper side of the array substrate 101, including a gate driving circuit and a data circuit; a plurality of source flip-chip films located on the upper side of the array substrate 101 and connected to the data lines of the liquid crystal display panel; a plurality of gate flip-chip films 105, which are located at the left and right sides of the array substrate 101, wherein the gate flip-chip films 105 located at the uppermost end are connected to the driving circuit board 104 through substrate wires, and the adjacent gate flip-chip films 105 located at the same side are connected through the substrate wires 106; a plurality of sets of fan-out wires 108, wherein the input end of each set of fan-out wires 108 is connected with a gate flip-chip film 105, and the output end of each set of fan-out wires 108 is connected with a scanning line; the substrate traces 106 are routed along the outside of the fan-out traces 108.
FIG. 2 is a schematic structural diagram of a common electrode layer of the LCD panel according to the present invention.
As shown in fig. 2, the color filter substrate includes a common electrode layer 201, and the common electrode layer 201 is prepared on one side of the color filter substrate opposite to the array substrate; a plurality of hollow structures are formed on two sides of the common electrode layer 201, so that the area of the common electrode layer 201 projected on the edge area of the array substrate is reduced, and the capacitance between the common electrode layer 201 and the substrate routing and the capacitance between the common electrode layer 201 and the fan-out routing are adjusted.
The hollow structure is that holes are formed in the common electrode layer 201 so as to dig out part of the electrodes at corresponding positions; the hollow structure comprises a first hollow part 202 and a second hollow part 203; the first hollow-out part 202 is correspondingly located in the region where the common electrode layer 201 covers the substrate routing, so that the capacitance between the substrate routing region and the common electrode layer 201 is reduced, and the interference of the substrate routing to signals is reduced; the second hollow-out portion 203 is inserted into the first hollow-out portion 202, the second hollow-out portion 203 forms a plurality of electrode patterns 204 on the common electrode layer 201, each electrode pattern 204 corresponds to a group of fan-out traces, and each electrode pattern 204 is formed by two symmetrical second hollow-out portions 203; by changing the shape and size of the electrode patterns 204, the capacitance between each electrode pattern 204 and the corresponding fan-out trace can be adjusted.
When the grid signal is driven, the grid signal is scanned line by line or interlaced from top to bottom, the signal is transmitted to each gate electrode flip chip film from top to bottom in sequence through the substrate wire, and the strength of the signal is gradually reduced when the signal is transmitted downwards, so that the fan-out wire groups connected with the gate electrode flip chip films of corresponding line levels are required to be matched with the electrode patterns 204 with different sizes; specifically, the areas of the plurality of electrode patterns 204 formed by the second hollow-out portion 203 from the electrode pattern 204 at the upper end to the electrode pattern 204 at the lower end are sequentially increased, and a single electrode pattern 204 does not exceed the area of one group of fan-out traces.
FIGS. 3a and 3b are schematic diagrams of single electrode pattern structures of the LCD panel of the present invention.
Each group of the fan-out wires 302 corresponds to one electrode pattern 301, the input ends of the fan-out wires 302 are connected to the gate electrode flip-chip film, and the fan-out wires 302 need to be spread to a wider width after being led out from the gate electrode flip-chip film, so that the lengths of the wires positioned at the upper end and the lower end to the wires positioned in the middle are gradually shortened, when the line width is constant, the longer wires have larger resistance, and conversely, the middle wires have the smallest resistance, and therefore, the electrode patterns 301 are designed to be approximately triangular, and the problems can be solved.
As shown in fig. 3a, the electrode pattern 301 is located at an upper position, and the electrode pattern 301 is located above a set of the fan-out traces 302 to form a capacitor with the fan-out traces 302; the electrode pattern 301 has a smaller area compared to the next electrode pattern 301, and the areas of the traces covering the upper and lower sides of the fan-out trace 302 are smaller, so that the capacitance between the upper and lower traces and the common click is reduced, the resistance of the upper and lower traces is increased, and the resistance of each trace in the same group is balanced.
As shown in fig. 3b, the electrode pattern 301 is located at a lower position, and the electrode pattern 301 is located above a set of the fan-out traces 302 to form a capacitor with the fan-out traces 302; the electrode pattern 301 has a larger area compared with the previous electrode pattern 301, and the areas of the wires covering the upper and lower sides of the fan-out wire 302 are larger, so that the capacitance between the upper and lower wires and the common electrode is increased, the resistance of the upper and lower wires is reduced, and the resistance of each wire in the same group is balanced.
Finally, through the common electrode layer formed by the hollow structure, the signal strength received by the fan-out wires 302 at each level is balanced, the signals transmitted by the fan-out wires 302 connected to the grid lines are balanced, and the voltage input to the panel is uniform, so that the problem that the liquid crystal display panel displays poor pictures of horizontal blocks is solved.
According to the above object, a liquid crystal display device is provided, comprising: a liquid crystal display panel; the backlight module is positioned on the opposite surface of the liquid crystal display panel; the liquid crystal display panel includes: a color film substrate, wherein a common electrode layer is prepared on the surface of the color film substrate; the array substrate is positioned on the opposite side of the color film substrate; the array substrate edge region includes: the driving circuit board is positioned on the upper side of the array substrate and comprises a grid driving circuit and a data circuit; the gate electrode chip on films are positioned on the left side and the right side of the array substrate, the gate electrode chip on film positioned at the uppermost end is connected to the driving circuit board through substrate wires, and the adjacent gate electrode chip on films positioned on the same side are connected through the substrate wires; the input end of each fan-out wire is connected with a gate electrode chip on film, and the output end of the fan-out wire is connected with a scanning line; the substrate routing lines are arranged along the outer sides of the fan-out routing lines; the array substrate comprises a substrate, a common electrode layer and a substrate wire, wherein a plurality of hollow structures are formed on two sides of the common electrode layer, so that the area of the common electrode layer projected on the edge area of the array substrate is reduced, and the capacitance value between the common electrode layer and the substrate wire is adjusted.
The working principle of the liquid crystal display device of the preferred embodiment is the same as that of the liquid crystal display panel of the preferred embodiment, and specific reference may be made to the working principle of the liquid crystal display panel of the preferred embodiment, which is not described herein again.
The invention has the beneficial effects that: compared with the liquid crystal display panel in the prior art, the liquid crystal display panel has the advantages that the hollow structures are formed on the two sides of the common electrode layer, the area of the edge area of the common electrode layer projected on the array substrate is reduced, capacitance values between the common electrode layer and substrate wiring and between the common electrode layer and fan-out wiring are changed, resistance value difference is offset, and the display phenomenon that voltage input into the panel is different due to the resistance value difference and horizontal blocks are poor is solved.
In summary, although the present invention has been described with reference to the preferred embodiments, the above-described preferred embodiments are not intended to limit the present invention, and those skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention, therefore, the scope of the present invention shall be determined by the appended claims.
Claims (6)
1. A liquid crystal display panel, comprising:
a color film substrate, wherein a common electrode layer is prepared on the surface of the color film substrate;
the array substrate is positioned on the opposite side of the color film substrate;
the array substrate edge region includes:
the driving circuit board is positioned on the upper side of the array substrate and comprises a grid driving circuit and a data circuit;
the gate electrode chip on films are positioned on the left side and the right side of the array substrate, the gate electrode chip on film positioned at the uppermost end is connected to the driving circuit board through substrate wires, and the adjacent gate electrode chip on films positioned on the same side are connected through the substrate wires;
the input end of each fan-out wire is connected with a gate electrode chip on film, and the output end of the fan-out wire is connected with a scanning line;
the substrate routing lines are arranged along the outer sides of the fan-out routing lines;
the array substrate comprises a common electrode layer, a plurality of fan-out wirings and a plurality of hollow structures, wherein the hollow structures are formed on two sides of the common electrode layer, the area of the common electrode layer projected on the edge area of the array substrate is further reduced, the capacitance value between the common electrode layer and the substrate wirings is adjusted, the hollow structures are holes left by digging partial electrodes on the common electrode and comprise first hollow parts and second hollow parts, the first hollow parts are correspondingly located in the areas where the common electrode layer covers the substrate wirings, the second hollow parts are inserted in the first hollow parts, a plurality of electrode patterns are formed on the common electrode layer, each electrode pattern is formed by two symmetrical second hollow parts, and each electrode pattern corresponds to one group of the fan-out wirings.
2. The liquid crystal display panel according to claim 1, wherein the electrode pattern shape is approximately an isosceles triangle rotated by 90 degrees.
3. The lcd panel of claim 2, wherein one of the electrode patterns overlaps a corresponding one of the fan-out traces, and wherein the electrode pattern covers areas of the traces on upper and lower sides of the fan-out trace and is related to a position of the fan-out trace on the array substrate.
4. The LCD panel of claim 3, wherein the area of the plurality of sets of fan-out traces on the array substrate relative to the electrode patterns corresponding to the fan-out traces in the subsequent set is larger than the electrode patterns corresponding to the fan-out traces in the previous set.
5. The liquid crystal display panel according to claim 4, wherein the electrode patterns on the left and right sides of the common electrode layer are symmetrically arranged.
6. A liquid crystal display device, comprising:
a liquid crystal display panel;
the backlight module is positioned on the opposite surface of the liquid crystal display panel;
the liquid crystal display panel includes:
a color film substrate, wherein a common electrode layer is prepared on the surface of the color film substrate;
the array substrate is positioned on the opposite side of the color film substrate;
the array substrate edge region includes:
the driving circuit board is positioned on the upper side of the array substrate and comprises a grid driving circuit and a data circuit;
the gate electrode chip on films are positioned on the left side and the right side of the array substrate, the gate electrode chip on film positioned at the uppermost end is connected to the driving circuit board through substrate wires, and the adjacent gate electrode chip on films positioned on the same side are connected through the substrate wires;
the input end of each fan-out wire is connected with a gate electrode chip on film, and the output end of the fan-out wire is connected with a scanning line;
the substrate routing lines are arranged along the outer sides of the fan-out routing lines;
the array substrate comprises a common electrode layer, a plurality of fan-out wirings and a plurality of hollow structures, wherein the hollow structures are formed on two sides of the common electrode layer, the area of the common electrode layer projected on the edge area of the array substrate is further reduced, the capacitance value between the common electrode layer and the substrate wirings is adjusted, the hollow structures are holes left by digging partial electrodes on the common electrode and comprise first hollow parts and second hollow parts, the first hollow parts are correspondingly located in the areas where the common electrode layer covers the substrate wirings, the second hollow parts are inserted in the first hollow parts, a plurality of electrode patterns are formed on the common electrode layer, each electrode pattern is formed by two symmetrical second hollow parts, and each electrode pattern corresponds to one group of the fan-out wirings.
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| CN109658891B (en) * | 2019-01-30 | 2020-08-18 | 惠科股份有限公司 | Drive circuit, display panel and display device |
| CN110147013A (en) * | 2019-05-07 | 2019-08-20 | 深圳市华星光电半导体显示技术有限公司 | Color membrane substrates and liquid crystal display panel |
| CN110133929B (en) * | 2019-06-28 | 2022-04-22 | 京东方科技集团股份有限公司 | Array substrate and manufacturing method thereof, display panel and display module |
| CN113419385B (en) * | 2021-05-31 | 2022-09-27 | 北海惠科光电技术有限公司 | Display panel, preparation method thereof and display device |
| CN114171571B (en) * | 2021-12-08 | 2023-12-01 | 武汉华星光电半导体显示技术有限公司 | Display panel and mobile terminal |
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| CN103293808B (en) * | 2013-05-28 | 2016-03-09 | 深圳市华星光电技术有限公司 | A kind of display device and manufacture method thereof |
| CN104267546A (en) * | 2014-09-19 | 2015-01-07 | 京东方科技集团股份有限公司 | Array substrate and display device |
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