CN106888016B - A kind of current-steering digital-to-analog converter and current steer digital-to-analogue method for transformation - Google Patents
A kind of current-steering digital-to-analog converter and current steer digital-to-analogue method for transformation Download PDFInfo
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- CN106888016B CN106888016B CN201510932060.1A CN201510932060A CN106888016B CN 106888016 B CN106888016 B CN 106888016B CN 201510932060 A CN201510932060 A CN 201510932060A CN 106888016 B CN106888016 B CN 106888016B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M1/00—Analogue/digital conversion; Digital/analogue conversion
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Abstract
The invention discloses a kind of current-steering digital-to-analog converter and current steer digital-to-analogue method for transformation, comprising: digital input circuit is sent to line decoder and column decoder for receiving the input of numerical data, and by the numerical data；The shuffling circuit being all connected with the line decoder and column decoder is sent to the line decoder and column decoder for generating on off sequence, and by the on off sequence；The line decoder and column decoder being separately connected with the digital input circuit, in conjunction with the on off sequence, the row data and column data of the numerical data to be respectively converted into corresponding thermometer-code；And the thermometer-code of conversion is sent to current source matrix；Current source matrix, for controlling the Push And Release of electric current, output current data according to the thermometer-code is received；The current-to-voltage convertor being connect with the current source matrix, for the current data to be converted to voltage data.
Description
Technical field
The present invention relates to integrated circuit technique more particularly to a kind of current-steering digital-to-analog converter and current steer digital-to-analogue conversion sides
Method.
Background technique
The development of the communication technology, the speed of logarithm mode converter (DAC, Digital to Analog Converters) with
More stringent requirements are proposed for precision, and HD video, high quality call require high-speed DAC.Current steer drives digital analog converter
(CS DAC, Current Steering Digital to Analog Converters) has obtained this contradiction effectively
Alleviate.Different from the DAC of other structures, CS DAC structure is simple, by binary current source or current source matrix, adds two
The current switch of system number control is constituted by the thermometer-code controller that decoder changes into.The electric current of current source can lead to
(high-speed applications) are crossed in switching to the resistance being directly grounded, such as Fig. 1, or are connected on the feedback resistance by a buffer
(low-speed applications), as shown in Figure 2.In practical applications, output uses differential configuration to reduce common-mode noise to output simulation letter
Number interference.In order to improve the matching properties of current source, unit current source array is generallyd use instead of binary current source.
Fig. 2 shows the structure (current cell) of traditionally basic current source cell.Each current source cell
Including one by p-type metal-insulator semiconductor (MIS) (PMOS, Positive Channel Metal Oxide
Semiconductor) the positive current of MP and MPC composition, and by N-type metal-insulator semiconductor (MIS) (NMOS, Negative
Channel Metal Oxide Semiconductor) MN and MNC composition negative current.The input digital data of DAC is in clock
Control under pass through a decoder and be transformed into current controling signal DC and DCB, control the on and off of this current source all the way.
Resulting differential current signal IopWith IonIt is then added to and (or is directly grounded by the feedback resistance of a buffer
Resistance) on the current-to-voltage convertor (I2V) that constitutes, thus the output differential voltage OUTP and OUTN that are converted accordingly.
Fig. 3 shows the related input and output waveform of the current source cell in Fig. 2.Clk is the input clock of DAC,
Data is input digital data, and DAC current is corresponding output electric current IopOr Ion。
Due to the finite speed of circuit, the output electric current of DAC has limited rise and fall along trWith tf.When input number
When according to data being a single logic ' 1 ', exporting electric current in a clock cycle has a rising edge and a failing edge；When defeated
When fashionable a string of continuous logic ' 1 ' (such as three in Fig. 3), output electric current also can have one in this continuous ' 1 ' starting
A rising edge has a failing edge, as shown in Figure 3 at the end of.
(i.e. Fig. 3 DAC current waveform is lower is wrapped the integral of the energy of DAC final output signal and Current versus time
The area contained such as A0... ..., A3Deng) related.Assuming that an ideal current source corresponds to the electric current output face of input data ' 1 '
If product is 1, A0 corresponds to 1- Δ Ar+ Δ Af in Fig. 3, and wherein Δ Ar is the area lost due to limited rising edge, and
Δ Af is increased area due to failing edge.Usually, Δ Ar ≠ Δ Af, and due to the change with temperature and technique
Change, the two is difficult to accomplish equal.A in Fig. 31=1- Δ Ar, A2=1, A3=1+ Δ Af.So the ratio A between them1:A0,
A2:A0, A3:A0, no longer it is just the relationship of 1:1.That is, the energy of output signal can generate and input signal amplitude phase
The error of pass, so as to cause the harmonic distortion of output signal.The harmonic distortion of signal caused by such phenomenon is referred to as intersymbol
It interferes (ISI).
DAC output signal caused by a kind of above-mentioned limited rise/fall edge due to output electric current of common elimination
The method of harmonic distortion is as shown in Figure 4.Electric current shown in current graph 3 will not will opened within the entire clock cycle for another example, Fig. 4
In electric current only need to be open-minded in the part-time of a clock cycle, such as half of clock cycle shown in figure.If still
Assuming that it is 1 that the electric current that an ideal current source corresponds to input data ' 1 ', which exports area within a clock cycle, in that Fig. 4
The area A that each output electric current is covered0... ..., A3It is all 1/2- Δ Ar+ΔAf.This is eliminated the need for because of input signal amplitude
Correlated error caused by difference, i.e. harmonic distortion.As electric current this in Fig. 4 only need to be in the part-time of a clock cycle
The on-off mode opened is referred to as zero formula (RZ).It is on the other side, as the implementation method in Fig. 3 is referred to as non-return-to-zero formula
(NRZ)。
Though the RZ on-off mode of Fig. 4 eliminates harmonic distortion caused by ISI above, because it is only in clock cycle
Part-time electric current is open-minded, so the efficiency of circuit part can be lost；Secondly, the service time because of electric current shortens, so it is right
Current unit circuit, especially after the requirement of speed of buffer of I2V can increase with the shortening of switch time, i.e., it is electric
The power consumption on road can rise.
Summary of the invention
In order to solve the above technical problems, the embodiment of the invention provides a kind of current-steering digital-to-analog converter and current steer digital-to-analogues
Method for transformation.
Current-steering digital-to-analog converter provided in an embodiment of the present invention, comprising:
Digital input circuit, for receiving the input of numerical data, and by the numerical data be sent to line decoder and
Column decoder；
The shuffling circuit being all connected with the line decoder and column decoder is opened for generating on off sequence, and by described
It closes sequence and is sent to the line decoder and column decoder；
The line decoder and column decoder being separately connected with the digital input circuit are used in conjunction with the on off sequence,
The row data and column data of the numerical data are respectively converted into corresponding thermometer-code；And the thermometer-code of conversion is sent
To current source matrix；
Current source matrix, for controlling the Push And Release of electric current, output current data according to the thermometer-code is received；
The current-to-voltage convertor being connect with the current source matrix, for the current data to be converted to voltage number
According to.
In the embodiment of the present invention, the current-steering digital-to-analog converter further include: clock selection circuit, for controlling clock
Frequency.
In the embodiment of the present invention, the current source matrix is made of multiple current source cells；The current source cell includes:
PMOS circuit, NMOS circuit, a pair of of common source common drain switch MPSW1 and MPSW2, another pair common source common drain switch
MPSW3 and MPSW4；A pair of of common source common drain switch MNSW1 and MNSW2, another pair common source common drain switch MNSW3 and
MNSW4。
In the embodiment of the present invention, the grid of MPSW1 meets DC, and the grid of MPSW2 meets DCB, and drain electrode meets IOP；The grid of MPSW3
DBC is met, the grid of MPSW4 meets DBCB, and drain electrode meets ION, MPSW1, MPSW2 and MPSW3, MPSW4 source electrode connect in common PMOS
On bias current sources MP and MPC；
The grid of MNSW1 meets DC, and the grid of MNSW2 meets DCB, and drain electrode meets ION；The grid of MNSW3 connects DBC, the grid of MNSW4
Pole meets DBCB, and drain electrode meets IOP；MNSW1, MNSW2 and MNSW3, MNSW4 source electrode connect in common NMOS bias current sources MN and
On MNC；IOPAnd IONIt is connected to the both ends of current-to-voltage convertor I2V；
Wherein, switch control signal DC, DCB, DBC, DBCB by 2 numerical datas generation.
In the embodiment of the present invention, described switch control signal DC, DCB, DBC, DBCB are respectively as follows:
DC=shuffle × data；
DCB=shuffleb × data；
DBC=shuffle × datab；
DBCB=shuffleb × datab；
Wherein, shuffle and shuffleb is the on off sequence, and data and datab are the numerical data.
In the embodiment of the present invention, when clock frequency is identical as digital data rates, each pair of switch is in the on off sequence
Selection under every half of clock cycle it is open-minded in turn；
When clock frequency be digital data rates half when, it is each pair of switch under the selection of the on off sequence with it is current when
The half period of clock is open-minded in turn.
In the embodiment of the present invention, the current-to-voltage convertor is the feedback resistance formed using buffer, or is straight
The resistance of ground connection.
Current steer digital-to-analogue method for transformation provided in an embodiment of the present invention includes:
The input of numerical data is received, and generates on off sequence；
In conjunction with the on off sequence, the row data and column data of the numerical data are respectively converted into corresponding thermometer
Code；
According to the thermometer-code is received, the Push And Release of electric current, output current data are controlled；
The current data is converted into voltage data.
The embodiment of the present invention utilizes CS DAC current source unit and shuffling circuit, the current steer of chances disturbance such as realizes
It is absolutely accurate to guarantee that the electric current of the situation of the corresponding N number of continuous logic ' 1 ' of input digital data and single logic ' 1 ' exports by DAC
N times of relationship to solve the harmonic distortion problems of nonreturn to zero code DAC generated because of rising and falling edges, while being kept away again
Exempt to introduce the additional power consumption introduced as zero code DAC.The technical solution of the embodiment of the present invention such as proposes at the chances disturbance
(EP, Equal Perturbation) current switch control mode, output signal harmonic wave caused by the above-mentioned ISI for CS DAC
Problem of dtmf distortion DTMF, by improving clock frequency, with double along data are acquired, to realize the RZ current switch in a data period twice
Mode；Or clock frequency is not improved, the on-off mode of NRZ is alternately realized with two-way current switch.Which is for switch electricity
Stream has the characteristics that limited up and down along allowing each logic ' 1 ' in numerical data to have equal number of up and down
Edge, to eliminate harmonic distortion caused by ISI.On the other hand, the embodiment of the present invention is because within a clock cycle to output
The disturbance of signal is small, so will not cause the extra demand to circuit power consumption.
Detailed description of the invention
Fig. 1 is the basic block diagram of current steering DAC；
Fig. 2 is the current source cell figure of traditional current source matrix；
Fig. 3 is the schematic diagram of traditional C/S DAC input clock and data waveform and output current wave and current error；
Fig. 4 is the schematic diagram of traditional follow-on current output waveform and elimination ISI error；
Fig. 5 is that the current steer digital-to-analogue of the embodiment of the present invention turns the structure composition schematic diagram of device；
Fig. 6 is the current source cell schematic diagram of the current source matrix of the embodiment of the present invention；
Fig. 7 is the output current wave and elimination ISI error of the current switch mode with approximation NRZ of the embodiment of the present invention
Schematic diagram；
Fig. 8 is that the embodiment of the present invention with the data to continuous logic ' 1 ' introduces the unlatching in turn of two-way current switch
With the output current wave of the mode of closing and the schematic diagram of elimination ISI error；
Fig. 9 is the flow diagram of the current steer digital-to-analogue method for transformation of the embodiment of the present invention.
Specific embodiment
The characteristics of in order to more fully hereinafter understand the embodiment of the present invention and technology contents, with reference to the accompanying drawing to this hair
The realization of bright embodiment is described in detail, appended attached drawing purposes of discussion only for reference, is not used to limit the embodiment of the present invention.
The current-steering digital-to-analog converter of the embodiment of the present invention is a kind of chances disturbance CS DAC such as novel, with twice number
The clock frequency of digital data generates two RZ current waveforms by two-way current switch within a data period, takes its result phase
Add, pieces together an approximation NRZ output waveform.It shuffles (shuffle) circuit alternatively, introducing one in switching logic control module,
By the open and close to two-way current switch in turn, thus in each of corresponding input data data logic ' 1 '
Electric current output all introduces a rising edge and a failing edge, realizes the elimination to harmonic distortion caused by ISI.
Fig. 5 is the structure composition schematic diagram of the current-steering digital-to-analog converter of the embodiment of the present invention, as shown in figure 5, the electricity
Flowing rudder D/A converter includes:
Digital input circuit 51 is sent to line decoder for receiving the input of numerical data, and by the numerical data
52 and column decoder 53；
The shuffling circuit 54 being all connected with the line decoder 52 and column decoder 53, for generating on off sequence, and will
The on off sequence is sent to the line decoder 52 and column decoder 53；
The line decoder 52 and column decoder 53 being separately connected with the digital input circuit 51, in conjunction with the switch
The row data and column data of the numerical data are respectively converted into corresponding thermometer-code by sequence；And by the thermometer of conversion
Code is sent to current source matrix 55；
Current source matrix 55 exports electric current number for controlling the Push And Release of electric current according to the thermometer-code is received
According to；
The current-to-voltage convertor (I2V) 56 being connect with the current source matrix 55, for converting the current data
For voltage data.
The current-steering digital-to-analog converter further include: clock selection circuit 57, for controlling the frequency of clock.
The current source matrix 55 is made of multiple current source cells；The current source cell includes: p-type metal insulator
Semiconductor PMOS circuit, N-type metal-insulator semiconductor (MIS) NMOS circuit, a pair of of common source common drain switch MPSW1 and MPSW2,
Another pair common source common drain switch MPSW3 and MPSW4；A pair of of common source common drain switch MNSW1 and MNSW2, another pair are total
Source electrode common drain switch MNSW3 and MNSW4.
The grid of MPSW1 meets DC, and the grid of MPSW2 meets DCB, and drain electrode meets IOP；The grid of MPSW3 connects DBC, the grid of MPSW4
Pole meets DBCB, and drain electrode meets ION, MPSW1, MPSW2 and MPSW3, MPSW4 source electrode connect in common pmos bias current source MP and
On MPC；
The grid of MNSW1 meets DC, and the grid of MNSW2 meets DCB, and drain electrode meets ION；The grid of MNSW3 connects DBC, the grid of MNSW4
Pole meets DBCB, and drain electrode meets IOP；MNSW1, MNSW2 and MNSW3, MNSW4 source electrode connect in common NMOS bias current sources MN and
On MNC；IOPAnd IONIt is connected to the both ends of current-to-voltage convertor I2V；
IOPAnd IONIt is connected to the both ends of I2V, specifically, IOPAnd IONTwo input terminals of simulation BUF are connected to, the two of BUF are simulated
A input terminal and output end transboundary resistance and capacitor, play the role of Current Voltage device (I2V), the output end of I2V exports mould
Quasi- voltage.
Wherein, switch control signal DC, DCB, DBC, DBCB by 2 numerical datas generation.
Described switch control signal DC, DCB, DBC, DBCB are respectively as follows:
DC=shuffle × data；
DCB=shuffleb × data；
DBC=shuffle × datab；
DBCB=shuffleb × datab；
Wherein, shuffle and shuffleb is the on off sequence, and data and datab are the numerical data.
When clock frequency is identical as digital data rates, when each pair of switch is every half under the selection of the on off sequence
The clock period is open-minded in turn；
When clock frequency be digital data rates half when, it is each pair of switch under the selection of the on off sequence with it is current when
The half period of clock is open-minded in turn.
The current-to-voltage convertor 56 is the feedback resistance formed using buffer, or the resistance to be directly grounded.
In the embodiment of the present invention, referring to Fig. 5, compared with traditional structure Fig. 1, the novel current steer number of the embodiment of the present invention
Mould method for transformation increases one on current switch Quality Initiative road and shuffles (shuffle) circuit, and selectable increase a period of time
Clock selection circuit.Corresponding, the matrix unit circuit of power supply source matrix of the invention is as shown in Figure 6.Shuffling circuit generates
Successively staggered acquisition current supply switch order, is supplied to line decoder and column decoder.After space decoding and column decoding
Thermometer-code be transmitted to current source matrix.The output end connection I2V of current source matrix realizes the conversion of current vs voltage.
It is the circuit structure diagram of the current source cell of the embodiment of the present invention such as Fig. 6, is divided into the part PMOS and the part NMOS,
Switch is formed by stacking by the output of four groups of signals DC, DCB, DBC, DBCB 2 DAC generated.MPSW1 and MPSW2 is a pair of total
Source electrode common drain switch.The grid of MPSW1 meets DC, and the grid of MPSW2 meets DCB, and drain electrode meets IOP；MPSW3 and MPSW4 is another pair
Common source common drain switch.The grid of MPSW3 meets DBC, and the grid of MPSW4 meets DBCB, and drain electrode meets ION, MPSW1, MPSW2 and
The source electrode of MPSW3, MPSW4 connect on common pmos bias current source MP and MPC.MNSW1 and MNSW2 is that a pair of of common source is total
Drain switch.The grid of MNSW1 meets DC, and the grid of MNSW2 meets DCB, and drain electrode meets ION；MNSW3 and MNSW4 is another pair common source
Common drain switch.The grid of MNSW3 meets DBC, and the grid of MNSW4 meets DBCB, and drain electrode meets IOP.MNSW1, MNSW2 and MNSW3,
The source electrode of MNSW4 connects on common NMOS bias current sources MN and MNC.IOPAnd IONIt is connected to the both ends of I2V.I2V can be logical
The feedback resistance for crossing a buffer is also possible to the resistance being directly grounded.I2V difference output be exactly DAC output OUTP and
OUTN completes the conversion from digital to analogy.IOPAnd IONIt is connected to the both ends of I2V, specifically, IOPAnd IONIt is connected to the two of simulation BUF
A input terminal simulates two input terminals and output end transboundary resistance and capacitor of BUF, plays the work of Current Voltage device (I2V)
With the output end of I2V exports analog voltage.
In the unit line of Fig. 6, switch control signal DC=shuffle × data, DCB=shuffleb × data,
DBC=shuffle × datab, DBCB=shuffleb × datab.So in each data data period, reversal by
The logical value of data determines which flows to Iop, which flows to Ion.And be actually flow through each pair of current-controlled switch MPSW1 and
MPSW2, MPSW3 and MPSW4, MNSW1 and MNSW2, MNSW3 and MNSW4 which then determined by the logical value of shuffle.
When the control clock CLK frequency divided is identical as data rate, above-mentioned each pair of switch can be under the selection of shuffle per half
A clock cycle is open-minded in turn；Equally when the control clock CLK frequency divided is data rate half, above-mentioned each pair of switch
It also can be open-minded in turn with present every half of clock cycle under the selection of shuffle.So shuffle module is just as shuffling
Effect equally makes two switch ceaselessly cycle alternation open and close of each pair of current switch.
Fig. 7 shows the output of the current source basic unit of Fig. 6 when control clock CLK frequency is identical as the rate of data
Current waveform and current error.It can be seen that under the selection of shuffle module, for example switch MPSW1 is in upper half of clock week
Phase first opens, and switch MPSW2 is then in close state at this time；In lower half of clock cycle, switch MPSW1 is closed, and is switched
MPSW2 is opened；Next clock cycle, switch MPSW1 were opened again in upper half of clock cycle, and switch MPSW2 is then closed.Due to every
To open and close alternating of the switch within each data period, area coverage (A of each current source within a data periodi
+A’i, i=0 ... ..., 3) and it is 1-2 × Δ Ar+2×ΔAf.So though what the data format in data is, all correspondences
' 1 ' electric current output be all it is equal, that is, eliminate harmonic distortion caused by ISI.On when due among each pair of switch alternately
Rise lose the addition of electric current caused by with failing edge along caused electric current can be right with partial offset, so the disturbance to circuit is smaller
Circuit power consumption is also without obvious additional demand.
Situation when Fig. 8 is rate half of the control clock CLK frequency for data.It is similar with above-mentioned analysis, in shuffle
Under the selection of module, each pair of current-controlled switch is also through every half of clock cycle (i.e. a data period) alternate open and close.
As seen from Figure 8, area coverage (A of each current source within a data periodi+A’i, i=0 ... ..., 3) and it is 1- Δ Ar
+ΔAf, equally eliminate the harmonic distortion due to caused by ISI.And the method in maximum perturbation caused by circuit and Fig. 2 to passing
The method of system is identical, so not increasing the additional demand to power consumption.
It should be understood that the structure of the chances disturbance CS DAC such as proposed by the present invention, is clock selection circuit, electricity of shuffling
Road (shuffle), symmetrical current source matrix combination invention two kinds of embodiments, thus also can the new embodiment of diffraction
And the present invention is included and covers.
Fig. 9 is the flow diagram of the current steer digital-to-analogue method for transformation of the embodiment of the present invention, the current steer number in this example
Mould method for transformation is applied in above-mentioned current-steering digital-to-analog converter, as shown in figure 9, the described method comprises the following steps:
Step 901: receiving the input of numerical data, and generate on off sequence.
Specifically, digital input circuit receives the input of numerical data, and the numerical data is sent to line decoder
And column decoder.
The shuffling circuit being all connected with the line decoder and column decoder generates on off sequence, and by the on off sequence
It is sent to the line decoder and column decoder.
Step 902: in conjunction with the on off sequence, the row data and column data of the numerical data being respectively converted into accordingly
Thermometer-code.
The on off sequence in conjunction with the line decoder and column decoder that the digital input circuit is separately connected, will be described
The row data and column data of numerical data are respectively converted into corresponding thermometer-code；And the thermometer-code of conversion is sent to electric current
Source matrix.
Step 903: according to the thermometer-code is received, controlling the Push And Release of electric current, output current data.
Current source matrix controls the Push And Release of electric current, output current data according to the thermometer-code is received.
Step 904: the current data is converted into voltage data.
The current data is converted to voltage data by the current-to-voltage convertor connecting with the current source matrix.
In above scheme, the current source matrix is made of multiple current source cells；The current source cell includes: PMOS
Circuit, NMOS circuit, a pair of of common source common drain switch MPSW1 and MPSW2, another pair common source common drain switch MPSW3 and
MPSW4；A pair of of common source common drain switch MNSW1 and MNSW2, another pair common source common drain switch MNSW3 and MNSW4.
The grid of MPSW1 meets DC, and the grid of MPSW2 meets DCB, and drain electrode meets IOP；The grid of MPSW3 connects DBC, the grid of MPSW4
Pole meets DBCB, and drain electrode meets ION, MPSW1, MPSW2 and MPSW3, MPSW4 source electrode connect in common pmos bias current source MP and
On MPC；
The grid of MNSW1 meets DC, and the grid of MNSW2 meets DCB, and drain electrode meets ION；The grid of MNSW3 connects DBC, the grid of MNSW4
Pole meets DBCB, and drain electrode meets IOP；MNSW1, MNSW2 and MNSW3, MNSW4 source electrode connect in common NMOS bias current sources MN and
On MNC；IOPAnd IONIt is connected to the both ends of I2V；
Wherein, switch control signal DC, DCB, DBC, DBCB by 2 numerical datas generation.
Specifically, IOPAnd IONIt is connected to the both ends of I2V, specifically, IOPAnd IONIt is connected to two input terminals of simulation BUF, simulation
Two input terminals and output end of BUF transboundary resistance and capacitor, play the role of Current Voltage device (I2V), the output end of I2V
Export analog voltage.
Described switch control signal DC, DCB, DBC, DBCB are respectively as follows:
DC=shuffle × data；
DCB=shuffleb × data；
DBC=shuffle × datab；
DBCB=shuffleb × datab；
Wherein, shuffle and shuffleb is the on off sequence, and data and datab are the numerical data.
When clock frequency is identical as digital data rates, when each pair of switch is every half under the selection of the on off sequence
The clock period is open-minded in turn；
When clock frequency be digital data rates half when, it is each pair of switch under the selection of the on off sequence with it is current when
The half period of clock is open-minded in turn.
It will be appreciated by those skilled in the art that current steer digital-to-analogue method for transformation shown in Fig. 9 can refer to aforementioned currents rudder number
The associated description of mode converter and understand.
It, in the absence of conflict, can be in any combination between technical solution documented by the embodiment of the present invention.
In several embodiments provided by the present invention, it should be understood that disclosed method and smart machine, Ke Yitong
Other modes are crossed to realize.Apparatus embodiments described above are merely indicative, for example, the division of the unit, only
Only a kind of logical function partition, there may be another division manner in actual implementation, such as: multiple units or components can be tied
It closes, or is desirably integrated into another system, or some features can be ignored or not executed.In addition, shown or discussed each group
Can be through some interfaces at the mutual coupling in part or direct-coupling or communication connection, equipment or unit it is indirect
Coupling or communication connection, can be electrical, mechanical or other forms.
Above-mentioned unit as illustrated by the separation member, which can be or may not be, to be physically separated, aobvious as unit
The component shown can be or may not be physical unit, it can and it is in one place, it may be distributed over multiple network lists
In member；Some or all of units can be selected to achieve the purpose of the solution of this embodiment according to the actual needs.
In addition, each functional unit in various embodiments of the present invention can be fully integrated into a second processing unit,
It is also possible to each unit individually as a unit, can also be integrated in one unit with two or more units；
Above-mentioned integrated unit both can take the form of hardware realization, can also add the form of SFU software functional unit real using hardware
It is existing.
The above description is merely a specific embodiment, but scope of protection of the present invention is not limited thereto, any
Those familiar with the art in the technical scope disclosed by the present invention, can easily think of the change or the replacement, and should all contain
Lid is within protection scope of the present invention.
Claims (11)
1. a kind of current-steering digital-to-analog converter characterized by comprising
The numerical data for receiving the input of numerical data, and is sent to line decoder and column are translated by digital input circuit
Code device；
The shuffling circuit being all connected with the line decoder and column decoder, for generating on off sequence, and by the switch sequence
Column are sent to the line decoder and column decoder, wherein the on off sequence is for following two switches of each pair of current switch
Ring is alternately opened and closed；
The line decoder and column decoder being separately connected with the digital input circuit are used in conjunction with the on off sequence, by institute
The row data and column data for stating numerical data are respectively converted into corresponding thermometer-code；And the thermometer-code of conversion is sent to electricity
Source matrix is flowed, wherein the thermometer-code allows each logic ' 1 ' in the numerical data to have equal number of up and down
Edge；
Current source matrix, according to the thermometer-code, controls the Push And Release of electric current, output electricity for receiving the thermometer-code
Flow data；
The current-to-voltage convertor being connect with the current source matrix, for the current data to be converted to voltage data.
2. current-steering digital-to-analog converter according to claim 1, which is characterized in that the current-steering digital-to-analog converter also wraps
It includes: clock selection circuit, for controlling the frequency of clock.
3. current-steering digital-to-analog converter according to claim 1, which is characterized in that the current source matrix is by multiple electric currents
Set of source at；The current source cell includes: p-type metal-insulator semiconductor (MIS) PMOS circuit, N-type metal-insulator semiconductor (MIS)
NMOS circuit, a pair of of common source common drain switch MPSW1 and MPSW2, another pair common source common drain switch MPSW3 and MPSW4；
A pair of of common source common drain switch MNSW1 and MNSW2, another pair common source common drain switch MNSW3 and MNSW4.
4. current-steering digital-to-analog converter according to claim 3, which is characterized in that
The grid of MPSW1 meets DC, and the grid of MPSW2 meets DCB, and drain electrode meets IOP；The grid of MPSW3 meets DBC, and the grid of MPSW4 connects
DBCB, drain electrode meet ION, MPSW1, MPSW2 and MPSW3, MPSW4 source electrode connect in common pmos bias current source MP and MPC
On；
The grid of MNSW1 meets DC, and the grid of MNSW2 meets DCB, and drain electrode meets ION；The grid of MNSW3 meets DBC, and the grid of MNSW4 connects
DBCB, drain electrode meet IOP；MNSW1, MNSW2 and MNSW3, MNSW4 source electrode connect in common NMOS bias current sources MN and MNC
On；IOPAnd IONIt is connected to the both ends of current-to-voltage convertor I2V；
Wherein, switch control signal DC, DCB, DBC, DBCB by two numerical datas generation.
5. current-steering digital-to-analog converter according to claim 4, which is characterized in that the switch control signal DC, DCB,
DBC, DBCB are respectively as follows:
DC=shuffle × data；
DCB=shuffleb × data；
DBC=shuffle × datab；
DBCB=shuffleb × datab；
Wherein, shuffle and shuffleb is the on off sequence, and data and datab are the numerical data.
6. current-steering digital-to-analog converter according to claim 5, which is characterized in that
When clock frequency is identical as digital data rates, when each pair of current switch is every half under the selection of the on off sequence
The clock period is open-minded in turn；
When clock frequency be digital data rates half when, each pair of current switch under the selection of the on off sequence with it is current when
The half period of clock is open-minded in turn.
7. current-steering digital-to-analog converter according to claim 1, which is characterized in that the current-to-voltage convertor is to utilize
The feedback resistance that buffer is formed, or the resistance to be directly grounded.
8. a kind of current steer digital-to-analogue method for transformation characterized by comprising
The input of numerical data is received, and generates on off sequence, wherein the on off sequence is for making each pair of current switch
Two switch cycles are alternately opened and closed；
In conjunction with the on off sequence, the row data and column data of the numerical data are respectively converted into corresponding thermometer-code,
Wherein the thermometer-code allows each logic ' 1 ' in the numerical data to have equal number of up and down edge；
According to the thermometer-code is received, the Push And Release of electric current, output current data are controlled；
The current data is converted into voltage data.
9. a kind of current-steering digital-to-analog converter characterized by comprising
The numerical data for receiving the input of numerical data, and is sent to line decoder and column are translated by digital input circuit
Code device；
The shuffling circuit being all connected with the line decoder and column decoder, for generating on off sequence, and by the switch sequence
Column are sent to the line decoder and column decoder；
The line decoder and column decoder being separately connected with the digital input circuit are used in conjunction with the on off sequence, by institute
The row data and column data for stating numerical data are respectively converted into corresponding thermometer-code；And the thermometer-code of conversion is sent to electricity
Flow source matrix；
Current source matrix, according to the thermometer-code, controls the Push And Release of electric current, output electricity for receiving the thermometer-code
Flow data；
The current-to-voltage convertor being connect with the current source matrix, for the current data to be converted to voltage data；
The current source matrix is made of multiple current source cells；The current source cell includes: p-type metal-insulator semiconductor (MIS)
PMOS circuit, N-type metal-insulator semiconductor (MIS) NMOS circuit, a pair of of common source common drain switch MPSW1 and MPSW2, another pair
Common source common drain switch MPSW3 and MPSW4；A pair of of common source common drain switch MNSW1 and MNSW2, another pair common source are total
Drain switch MNSW3 and MNSW4；
The grid of MPSW1 meets DC, and the grid of MPSW2 meets DCB, and drain electrode meets IOP；The grid of MPSW3 meets DBC, and the grid of MPSW4 connects
DBCB, drain electrode meet ION, MPSW1, MPSW2 and MPSW3, MPSW4 source electrode connect in common pmos bias current source MP and MPC
On；
The grid of MNSW1 meets DC, and the grid of MNSW2 meets DCB, and drain electrode meets ION；The grid of MNSW3 meets DBC, and the grid of MNSW4 connects
DBCB, drain electrode meet IOP；MNSW1, MNSW2 and MNSW3, MNSW4 source electrode connect in common NMOS bias current sources MN and MNC
On；IOPAnd IONIt is connected to the both ends of current-to-voltage convertor I2V；
Wherein, switch control signal DC, DCB, DBC, DBCB by two numerical datas generation.
10. current-steering digital-to-analog converter according to claim 9, which is characterized in that the switch control signal DC, DCB,
DBC, DBCB are respectively as follows:
DC=shuffle × data；
DCB=shuffleb × data；
DBC=shuffle × datab；
DBCB=shuffleb × datab；
Wherein, shuffle and shuffleb is the on off sequence, and data and datab are the numerical data.
11. current-steering digital-to-analog converter according to claim 10, which is characterized in that
When clock frequency is identical as digital data rates, each pair of switch every half of clock week under the selection of the on off sequence
Phase is open-minded in turn；
When clock frequency is digital data rates half, each pair of switch is under the selection of the on off sequence with present clock
The half period is open-minded in turn.
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| CN201510932060.1A CN106888016B (en) | 2015-12-15 | 2015-12-15 | A kind of current-steering digital-to-analog converter and current steer digital-to-analogue method for transformation |
| PCT/CN2016/088184 WO2017101302A1 (en) | 2015-12-15 | 2016-07-01 | Current steering digital-to-analogue converter and current steering digital-to-analogue conversion method, and storage medium |
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| CN201510932060.1A CN106888016B (en) | 2015-12-15 | 2015-12-15 | A kind of current-steering digital-to-analog converter and current steer digital-to-analogue method for transformation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1306347A (en) * | 2000-01-17 | 2001-08-01 | 华为技术有限公司 | D/A converter with current helm structure for 12c logic |
| CN101299610A (en) * | 2008-06-16 | 2008-11-05 | 湖南大学 | High speed digital-analog converter with ten bits current rudder structure |
| CN103840832A (en) * | 2014-02-21 | 2014-06-04 | 上海华力微电子有限公司 | Current rudder type digital-to-analogue conversion circuit with burr inhibiting ability |
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| EP1374406B1 (en) * | 2000-09-11 | 2006-03-08 | Broadcom Corporation | Method and apparatus for mismatch shaping of an oversampled converter |
| US7079063B1 (en) * | 2005-04-18 | 2006-07-18 | Analog Devices, Inc. | System and method for tri-level logic data shuffling for oversampling data conversion |
| CN101237238B (en) * | 2007-12-29 | 2011-05-18 | 湖南大学 | CMOS current helm DA converter based on switch current technology |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1306347A (en) * | 2000-01-17 | 2001-08-01 | 华为技术有限公司 | D/A converter with current helm structure for 12c logic |
| CN101299610A (en) * | 2008-06-16 | 2008-11-05 | 湖南大学 | High speed digital-analog converter with ten bits current rudder structure |
| CN103840832A (en) * | 2014-02-21 | 2014-06-04 | 上海华力微电子有限公司 | Current rudder type digital-to-analogue conversion circuit with burr inhibiting ability |
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Application publication date: 20170623 Assignee: Xi'an Chris Semiconductor Technology Co. Ltd. Assignor: SHENZHEN ZTE MICROELECTRONICS TECHNOLOGY CO., LTD. Contract record no.: 2019440020036 Denomination of invention: Current-steering digital-analog converter and current-steering digital analog conversion method Granted publication date: 20181204 License type: Common License Record date: 20190619 |