CN106887252A - Eeprom memory and its operating method - Google Patents
Eeprom memory and its operating method Download PDFInfo
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- CN106887252A CN106887252A CN201710004047.9A CN201710004047A CN106887252A CN 106887252 A CN106887252 A CN 106887252A CN 201710004047 A CN201710004047 A CN 201710004047A CN 106887252 A CN106887252 A CN 106887252A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
- G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/26—Sensing or reading circuits; Data output circuits
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- Engineering & Computer Science (AREA)
- Computer Security & Cryptography (AREA)
- Read Only Memory (AREA)
Abstract
The invention discloses a kind of eeprom memory, each byte selection circuit simultaneous selection multiple byte, corresponding digit is x × n；Column select circuit, is selected for the corresponding position of x × n row；Data are wiped and writing unit, and data erasing and write-in are used for for being input into a byte data；First data read-out unit, for reading a selected byte data；Second data read-out unit, for reading non-selected (x 1) individual byte data；Data register, for data erasing and the data of writing unit and the data of the second data read-out unit to be combined into x byte data；In data erasing and ablation process, x byte data of data register is input in the memory cell of corresponding same a line by column select circuit, and realization is to the erasing of the memory cell of a selected byte or writes.The present invention can reduce the crosstalk between the number and the different memory cell of reduction of byte selection circuit.
Description
Technical field
The present invention relates to semiconductor integrated circuit manufacture field, more particularly to a kind of eeprom memory；The present invention is also
It is related to a kind of operating method of eeprom memory.
Background technology
As shown in figure 1, being the schematic diagram of existing eeprom memory；Storage array as shown in dotted line frame 101, storage array
Formed according to row and column arrangement by multiple memory cell.
One byte is generally made up of n memory cell, and a byte is selected by a byte selection circuit in Fig. 1
Select, four byte selection circuits, the respectively 102a of byte selection circuit one, the 102b of byte selection circuit two, word are shown in Fig. 1
The section 102c of the selection circuit three and 102d of byte selection circuit four.In the prior art, due to a byte and a byte selection electricity
Road is corresponding, therefore the digit for corresponding to a byte in Fig. 1 per a line is that n is, shows four rows in Fig. 1 altogether, respectively as marked
Shown in 101a, 101b, 101c and 101d.
The bit line that column select circuit 103 is used for corresponding to the position to byte is selected, and n bar bit lines is had, in Fig. 1
Shown in BL1, BL2 to BL (n-1) and BLn.
Data are wiped and writing unit 104 is wiped and write for providing n-bit data for selected byte.
Data read-out unit 105 is used to read the data of selected byte, and the digit for reading each time is n i.e. one
The digit of byte.
Byte selection circuit can be made up of a selection transistor.
Understand as shown in Figure 1, n memory cell of same byte is being physically adjacent.Same byte it is each
After position is chosen by byte selection circuit, n memory cell of same byte carries out the storage operations such as erasable reading simultaneously, adjacent
Crosstalk is easily formed between position.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of eeprom memory, can reduce the number of byte selection circuit
Crosstalk between mesh and the different memory cell of reduction.Therefore, the present invention also provides a kind of operating method of eeprom memory.
In order to solve the above technical problems, the eeprom memory that the present invention is provided includes：
Multiple byte selection circuits, each byte selection circuit is used for simultaneous selection multiple byte；Make each byte
It it is n, the byte number of each byte selection circuit simultaneous selection is x, then corresponding to a byte selection circuit
Digit be x × n；The row of storage array as corresponding to the corresponding byte selection circuit x × n memory cell arrangement and
Into；The row of the storage array are formed by the memory cell arrangement of the identical bits of each byte selection circuit, described to deposit
The columns for storing up array is x × n.
Column select circuit, is selected for the corresponding position of x × n row.
Data are wiped and writing unit, for being input into a selected byte number for needing to carry out data erasing and write-in
According to.
First data read-out unit, for reading a selected byte data.
Second data read-out unit, goes together and non-selected (x-1) individual byte number for reading with selected byte
According to.
One byte data and the second data read-out unit of data register, the data erasing and writing unit
(x-1) individual byte data be all input to the data register in be combined into x byte data；In data erasing and ablation process
In, x byte data of the data register is input to the storage of corresponding same a line by the column select circuit
In unit, the erasing or write-in to the memory cell of a selected byte are realized.
It is that each byte selection circuit is made up of selection transistor respectively further to improve.
It is that the n-bit data in the same described byte in same a line is non-conterminous further to improve.
Further improving is, in data erasing process, first to the selected a line of byte selection circuit
The data of common x × n memory cell are all wiped；Then, the byte for carrying out data erasing is needed to carry out by selected
Data protection is not written into, and is written to x byte data of the data register by the column select circuit corresponding
With in the memory cell of a line.
Further improving is, in data writing process, first to the selected a line of byte selection circuit
The data of common x × n memory cell are all wiped；Then, by the column select circuit by x word of the data register
Joint number evidence is written in the memory cell of corresponding same a line.
Further improving is, in data read process, the byte to be read is selected by the byte selection circuit
Corresponding row, the row corresponding to the byte of all readings are selected by the column select circuit, are then counted by described first
According to sensing element by the data read-out of a selected byte.
In order to solve the above technical problems, the operating method of the eeprom memory of present invention offer includes three kinds of operation moulds
Formula, respectively data read operation, data write operation, data erasing operation.
The data read operation includes such as step：
Row corresponding to the byte to be read is selected by the byte selection circuit.
Row corresponding to the byte of all readings are selected by the column select circuit.
By the first data read-out unit by the data read-out of a selected byte.
Further improving is, the data write operation includes such as step：
Row corresponding to the byte to be write is selected by the byte selection circuit.
By the row corresponding to the byte that column select circuit selection need not be write.
(x-1) the individual byte data that need not will be write by the second data read-out unit is read.
From the byte data that data erasing and writing unit input need to be write.
Data erasing is individual with (x-1) of a byte data of writing unit and the second data read-out unit
Byte data is combined into x byte data in being all input to the data register.
X byte data of the selected row of byte selection circuit is all wiped.
X byte data in the data register is written in the selected row of byte selection circuit.
Further improving is, the data erasing operation includes such as step：
Row corresponding to the byte to be wiped is selected by the byte selection circuit.
By the row corresponding to the byte that column select circuit selection need not be wiped.
(x-1) the individual byte data that need not will be wiped by the second data read-out unit is read.
A byte data is input into from data erasing and writing unit.
Data erasing is individual with (x-1) of a byte data of writing unit and the second data read-out unit
Byte data is combined into x byte data in being all input to the data register.
X byte data of the selected row of byte selection circuit is all wiped.
The byte for carrying out data erasing is needed to carry out data protection or be not written into by selected, afterwards, will be described
X byte data in data register is written in the selected row of byte selection circuit.
Each byte selection circuit energy simultaneous selection multiple byte of the invention, therefore quilt simultaneously can be formed using multiple bytes
The row of selection, and the setting for passing through column select circuit and the first data read-out unit can be realized n of selected byte
Data read-out.
Can be realized the (x- altogether of non-selected byte by the setting of column select circuit and the second data read-out unit
1) × n-bit data reads, and these (x-1) × n-bit datas are used to carry out non-selected byte in erasing and ablation process
Write-back after reading, makes the data of non-selected byte not be destroyed；In column select circuit and the base of the second data read-out unit
On plinth, in conjunction with the n-bit data data erasing of one byte for the treatment of and the data register of writing unit and storage x × n-bit data
Device, can realize carrying out data erasing and write-in to selected byte.
So eeprom memory of the present invention can be good at realizing reading, erasing and the write-in to byte, while can be real
Existing byte selection circuit simultaneous selection multiple byte, can so save the number of byte selection circuit, and this can save electricity
The area and cost on road.
Simultaneously as a byte selection circuit energy simultaneous selection multiple byte, the byte that such multiple is selected simultaneously
In same a line, can realize by same byte everybody it is non-conterminous be disposed in corresponding row, due to same word
Section everybody is non-conterminous, so as to eliminate the reading cross-interference issue of adjacent bit.The elimination of the reading cross-interference issue of adjacent bit means together
What the spacing of adjacent bit byte can be done in a line is smaller, and the area so as to make storage array reduces, further reduces cost.
Brief description of the drawings
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description：
Fig. 1 is the schematic diagram of existing eeprom memory；
Fig. 2 is the schematic diagram of embodiment of the present invention eeprom memory.
Specific embodiment
As shown in Fig. 2 being the schematic diagram of embodiment of the present invention eeprom memory, embodiment of the present invention eeprom memory
Including：
Multiple byte selection circuits, show four byte selection circuits in Fig. 2, the respectively 2a of byte selection circuit one,
The 2b of byte selection circuit two, the 2c of byte selection circuit three and the 2d of byte selection circuit four.Each byte selection circuit is used for same
When the multiple bytes of selection；It is n to make each byte, and the byte number of each byte selection circuit simultaneous selection is x, then
Digit corresponding to one byte selection circuit is x × n.The row of storage array is by the corresponding byte selection circuit institute
Corresponding x × n memory cell arrangement is formed, and shows four rows in Fig. 2 altogether, respectively as shown in mark 1a, 1b, 1c and 1d, can
To find out, x byte is included in every a line.Due to having multiple bytes in same a line, therefore digit between each byte can be with
Mutually stagger so that same byte everybody non-conterminous namely adjacent two be belonging to different bytes, so the present invention is real
The n-bit data in the same described byte in same a line for applying example is non-conterminous.
The row of the storage array are formed by the memory cell arrangement of the identical bits of each byte selection circuit, institute
The columns for stating storage array is x × n；The storage array is as shown in dotted line frame 1.
Each byte selection circuit is made up of selection transistor respectively.
Column select circuit 3, is selected for the corresponding position of x × n row, and each corresponds to a bit line, have x ×
N bar bit lines, as shown in the BL1 in Fig. 1, BL2, BL3, BL4 to BL (xn-2), BL (xn-1) and BLxn, wherein xn represent x ×
n。
Data are wiped and writing unit 4, for being input into a selected byte for needing to carry out data erasing and write-in
Data, namely it is used for data erasing and write-in for being input into a byte data.One byte data is total n, for more shape
The sign of elephant, shows common n, place corresponding to data erasing and writing unit 4 in the data erasing of Fig. 2 and writing unit 4
The digit of the data of reason.
First data read-out unit 5a, for reading a selected byte data, the first data read-out unit of Fig. 2
Reading n is also show in 5a.
Second data read-out unit 5b, goes together and non-selected (x-1) individual byte for reading with selected byte
Data；Reading (x-1) × n is also show in the second data read-out unit 5b of Fig. 2, corresponding to (x-1) individual byte data.
One byte data and the second data read-out list of data register 6, the data erasing and writing unit 4
(x-1) individual byte data of first 5b is combined into x byte data, the data register of Fig. 2 in being all input to the data register 6
Be also show in 6 it is common x × n, corresponding to x byte data.In data erasing and ablation process, the data register 6
X byte data be input in the memory cell of corresponding same a line by the column select circuit 3, realize to selected
The erasing or write-in of the memory cell of the byte selected.
In data erasing process, storage common x × n to the selected a line of byte selection circuit first
The data of unit are all wiped；Then, the byte for carrying out data erasing is needed to carry out data protection or do not write by selected
Enter, x byte data of the data register 6 is written to described in corresponding same a line by the column select circuit 3
In memory cell.
In data writing process, storage common x × n to the selected a line of byte selection circuit first
The data of unit are all wiped；Then, x byte data of the data register 6 is written to by the column select circuit 3
In the memory cell of corresponding same a line.
In data read process, the row corresponding to the byte to be read is selected by the byte selection circuit, led to
The row that the column select circuit 3 selects corresponding to the byte of all readings are crossed, then by the first data read-out unit 5a
By the data read-out of a selected byte.
The operating method of the eeprom memory of the embodiment of the present invention one is used for the EEPROM of the embodiment of the present invention described in Fig. 2 one
Memory is operated, including three kinds of operator schemes, respectively data read operation, data write operation, data erasing operation.
The data read operation includes such as step：
Row corresponding to the byte to be read is selected by the byte selection circuit.
Row corresponding to the byte of all readings are selected by the column select circuit 3.
By the first data read-out unit 5a by the data read-out of a selected byte.
The data write operation includes such as step：
Row corresponding to the byte to be write is selected by the byte selection circuit.
By the row corresponding to the byte that the selection of the column select circuit 3 need not be write.
(x-1) the individual byte data that need not will be write by the second data read-out unit 5b is read.
From the byte data that data erasing and the input of writing unit 4 need to be write.
By data erasing and a byte data and the (x- of the second data read-out unit 5b of writing unit 4
1) individual byte data is combined into x byte data in being all input to the data register 6.
X byte data of the selected row of byte selection circuit is all wiped.
X byte data in the data register 6 is written in the selected row of byte selection circuit.
The data erasing operation includes such as step：
Row corresponding to the byte to be wiped is selected by the byte selection circuit.
By the row corresponding to the byte that the selection of the column select circuit 3 need not be wiped.
(x-1) the individual byte data that need not will be wiped by the second data read-out unit 5b is read.
A byte data is input into from data erasing and writing unit 4.
By data erasing and a byte data and the (x- of the second data read-out unit 5b of writing unit 4
1) individual byte data is combined into x byte data in being all input to the data register 6.
X byte data of the selected row of byte selection circuit is all wiped.
The byte for carrying out data erasing is needed to carry out data protection or be not written into by selected, afterwards, will be described
X byte data in data register 6 is written in the selected row of byte selection circuit.
The present invention has been described in detail above by specific embodiment, but these are not constituted to limit of the invention
System.Without departing from the principles of the present invention, those skilled in the art can also make many deformations and improvement, and these also should
It is considered as protection scope of the present invention.
Claims (9)
1. a kind of eeprom memory, it is characterised in that including：
Multiple byte selection circuits, each byte selection circuit is used for simultaneous selection multiple byte；It is n to make each byte
Position, the byte number of each byte selection circuit simultaneous selection is x, then the position corresponding to a byte selection circuit
Number is x × n；X × n memory cell arrangement of the row of storage array as corresponding to the corresponding byte selection circuit is formed；
The row of the storage array are formed by the memory cell arrangement of the identical bits of each byte selection circuit, the storage battle array
The columns of row is x × n；
Column select circuit, is selected for the corresponding position of x × n row；
Data are wiped and writing unit, for being input into a selected byte data for needing to carry out data erasing and write-in；
First data read-out unit, for reading a selected byte data；
Second data read-out unit, goes together and non-selected (x-1) individual byte data for reading with selected byte；
Data register, a byte data and the second data read-out unit of the data erasing and writing unit
(x-1) individual byte data is combined into x byte data in being all input to the data register；In data erasing and ablation process
In, x byte data of the data register is input to the storage of corresponding same a line by the column select circuit
In unit, the erasing or write-in to the memory cell of a selected byte are realized.
2. eeprom memory as claimed in claim 1, it is characterised in that：Each byte selection circuit is brilliant by selection respectively
Body pipe is constituted.
3. eeprom memory as claimed in claim 1, it is characterised in that：In the same described byte in same a line
N-bit data is non-conterminous.
4. eeprom memory as claimed in claim 1, it is characterised in that：In data erasing process, first to an institute
The data for stating the common x × n memory cell of the selected a line of byte selection circuit are all wiped；Then, by selected needs
A byte for carrying out data erasing carries out data protection or is not written into, by the column select circuit by the data register
X byte data be written in the memory cell of corresponding same a line.
5. eeprom memory as claimed in claim 1, it is characterised in that：In data writing process, first to an institute
The data for stating the common x × n memory cell of the selected a line of byte selection circuit are all wiped；Then, by the column selection
Be written to x byte data of the data register in the memory cell of corresponding same a line by circuit.
6. eeprom memory as claimed in claim 1, it is characterised in that：In data read process, by the byte
Row corresponding to the selection circuit selection byte to be read, selects the byte institute of all readings right by the column select circuit
The row answered, then by the first data read-out unit by the data read-out of a selected byte.
7. a kind of operating method of eeprom memory as claimed in claim 1, it is characterised in that including three kinds of operation moulds
Formula, respectively data read operation, data write operation, data erasing operation；
The data read operation includes such as step：
Row corresponding to the byte to be read is selected by the byte selection circuit；
Row corresponding to the byte of all readings are selected by the column select circuit；
By the first data read-out unit by the data read-out of a selected byte.
8. the operating method of eeprom memory as claimed in claim 7, it is characterised in that the data write operation includes
Such as step：
Row corresponding to the byte to be write is selected by the byte selection circuit；
By the row corresponding to the byte that column select circuit selection need not be write；
(x-1) the individual byte data that need not will be write by the second data read-out unit is read；
From the byte data that data erasing and writing unit input need to be write；
By data erasing and a byte data and (x-1) individual byte of the second data read-out unit of writing unit
Data are combined into x byte data in being all input to the data register；
X byte data of the selected row of byte selection circuit is all wiped；
X byte data in the data register is written in the selected row of byte selection circuit.
9. the operating method of eeprom memory as claimed in claim 7, it is characterised in that the data erasing operation includes
Such as step：
Row corresponding to the byte to be wiped is selected by the byte selection circuit；
By the row corresponding to the byte that column select circuit selection need not be wiped；
(x-1) the individual byte data that need not will be wiped by the second data read-out unit is read；
A byte data is input into from data erasing and writing unit；
By data erasing and a byte data and (x-1) individual byte of the second data read-out unit of writing unit
Data are combined into x byte data in being all input to the data register；
X byte data of the selected row of byte selection circuit is all wiped；
The byte for carrying out data erasing is needed to carry out data protection or be not written into by selected, afterwards, by the data
X byte data in register is written in the selected row of byte selection circuit.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710004047.9A CN106887252B (en) | 2017-01-04 | 2017-01-04 | EEPROM memory and operation method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710004047.9A CN106887252B (en) | 2017-01-04 | 2017-01-04 | EEPROM memory and operation method thereof |
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| CN106887252A true CN106887252A (en) | 2017-06-23 |
| CN106887252B CN106887252B (en) | 2020-02-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111091860A (en) * | 2019-12-26 | 2020-05-01 | 普冉半导体（上海）有限公司 | EEPROM memory |
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| KR101703106B1 (en) * | 2011-01-04 | 2017-02-06 | 삼성전자주식회사 | Non-volatile memory device of performing partial-erase operation and apparatuses having the same |
| US9257169B2 (en) * | 2012-05-14 | 2016-02-09 | Samsung Electronics Co., Ltd. | Memory device, memory system, and operating methods thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111091860A (en) * | 2019-12-26 | 2020-05-01 | 普冉半导体（上海）有限公司 | EEPROM memory |
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