CN106887252B - EEPROM memory and operation method thereof - Google Patents

EEPROM memory and operation method thereof Download PDF

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CN106887252B
CN106887252B CN201710004047.9A CN201710004047A CN106887252B CN 106887252 B CN106887252 B CN 106887252B CN 201710004047 A CN201710004047 A CN 201710004047A CN 106887252 B CN106887252 B CN 106887252B
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data
byte
selection circuit
erasing
bytes
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CN106887252A (en
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张可钢
陈华伦
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Huahong Grace Semiconductor Manufacturing Corp
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/22—Safety or protection circuits preventing unauthorised or accidental access to memory cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits

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  • Engineering & Computer Science (AREA)
  • Computer Security & Cryptography (AREA)
  • Read Only Memory (AREA)

Abstract

The invention discloses an EEPROM memory, each byte selection circuit selects a plurality of bytes simultaneously, the corresponding digit is x multiplied by n; a column selection circuit for selecting bits corresponding to the x × n columns; a data erasing and writing unit for inputting one byte of data for data erasing and writing; a first data reading unit for reading the selected one byte data; a second data reading unit for reading the unselected (x-1) byte data; a data register for splicing the data of the data erasing and writing unit and the data of the second data reading unit into x byte data; in the data erasing and writing process, x bytes of data of the data register are input into the corresponding memory cells in the same row through the column selection circuit, and the erasing or writing of the selected memory cells of one byte is realized. The invention can reduce the number of byte selection circuits and reduce the crosstalk between different memory cells.

Description

EEPROM memory and operation method thereof
Technical Field
The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to an EEPROM (electrically erasable programmable read-Only memory); the invention also relates to an operation method of the EEPROM.
Background
FIG. 1 is a schematic diagram of a conventional EEPROM memory; the memory array is shown in dashed line 101 and is formed by arranging a plurality of memory cells in rows and columns.
One byte is generally formed of n-bit memory cells, one byte is selected by one byte selection circuit in fig. 1, and four byte selection circuits, namely a byte selection circuit one 102a, a byte selection circuit two 102b, a byte selection circuit three 102c, and a byte selection circuit four 102d, are shown in fig. 1. In the prior art, since one byte corresponds to one byte selection circuit, the number of bits, i.e., n, corresponding to one byte per line in fig. 1 is shown as n, and four lines are shown in fig. 1, as indicated by the marks 101a, 101b, 101c, and 101d, respectively.
The column selection circuit 103 is used for selecting bit lines corresponding to bits of a byte, and has n bit lines, as shown in BL1, BL2 to BL (n-1) and BLn in fig. 1.
The data erase and write unit 104 is used to provide n bits of data for the selected byte to be erased and written.
The data reading unit 105 is configured to read data of a selected byte, and the number of bits read each time is n bits, that is, the number of bits of one byte.
The byte selection circuit can be composed of one selection transistor.
As shown in fig. 1, the n-bit memory cells of the same byte are physically adjacent. After each bit of the same byte is selected by the byte selection circuit, the n-bit memory cells of the same byte simultaneously perform memory operations such as erasing, writing and reading, and crosstalk is easily formed between adjacent bits.
Disclosure of Invention
The present invention provides an EEPROM memory, which can reduce the number of byte selection circuits and reduce crosstalk between different memory cells. Therefore, the invention also provides an operation method of the EEPROM.
In order to solve the above technical problem, the EEPROM memory provided by the present invention includes:
a plurality of byte selection circuits, each for selecting a plurality of bytes simultaneously; making each byte be n bits, and making the number of bytes simultaneously selected by each byte selection circuit be x, then the number of bits corresponding to one byte selection circuit is x × n; the rows of the memory array are formed by arranging the x multiplied by n bit memory cells corresponding to the byte selection circuits; the memory array is arranged by arranging the memory cells of the same bit of each byte selection circuit, and the number of the memory array columns is x × n.
And the column selection circuit is used for selecting the bits corresponding to the x multiplied by n columns.
And the data erasing and writing unit is used for inputting the selected one byte of data needing data erasing and writing.
And a first data reading unit for reading the selected one byte data.
And a second data reading unit for reading (x-1) byte data which is in the same row as the selected byte and is not selected.
A data register to which one byte data of the data erasing and writing unit and (x-1) byte data of the second data reading unit are input to be spliced into x byte data; in the data erasing and writing process, the x bytes of data of the data register are input into the corresponding memory cells in the same row through the column selection circuit, so that the memory cells of the selected byte are erased or written.
In a further improvement, each of the byte selection circuits is composed of a selection transistor.
In a further improvement, the n bits of data in the same byte in the same row are not adjacent.
In the process of data erasing, firstly, erasing the data of a row of memory cells with x × n bits selected by one byte selection circuit; then, data protection or non-writing is carried out on the selected byte needing data erasing, and x bytes of data of the data register are written into the corresponding storage units in the same row through the column selection circuit.
In the process of data writing, firstly, erasing the data of a row of x × n-bit memory cells selected by one byte selection circuit; then, the x bytes of data of the data register are written into the memory cells of the corresponding same row by the column selection circuit.
In a further improvement, in the data reading process, the row corresponding to the byte to be read is selected by the byte selection circuit, the columns corresponding to all the read bytes are selected by the column selection circuit, and then the data of the selected byte is read out by the first data reading unit.
In order to solve the above technical problems, the operation method of the EEPROM provided by the present invention includes three operation modes, which are a data read operation, a data write operation, and a data erase operation.
The data reading operation comprises the following steps:
the row corresponding to the byte to be read is selected by the byte selection circuit.
And selecting the columns corresponding to all the read bytes by the column selection circuit.
Reading out the selected one byte of data by the first data readout unit.
In a further refinement, the data write operation includes the steps of:
the row corresponding to the byte to be written is selected by the byte selection circuit.
And selecting the column corresponding to the byte which does not need to be written by the column selection circuit.
(x-1) byte data which is not required to be written is read out by the second data reading unit.
One byte of data to be written is input from the data erasing and writing unit.
Inputting one byte data of the data erasing and writing unit and (x-1) byte data of the second data reading unit into the data register to be spliced into x byte data.
All x bytes of data of the row selected by the byte selection circuit are erased.
Writing x bytes of data in the data register into the row selected by the byte selection circuitry.
In a further refinement, the data erase operation includes the steps of:
the row corresponding to the byte to be erased is selected by the byte selection circuit.
And selecting the column corresponding to the byte which does not need to be erased by the column selection circuit.
(x-1) byte data which does not require erasing is read out by the second data reading unit.
One byte of data is input from the data erasing and writing unit.
Inputting one byte data of the data erasing and writing unit and (x-1) byte data of the second data reading unit into the data register to be spliced into x byte data.
All x bytes of data of the row selected by the byte selection circuit are erased.
And performing data protection or non-writing on the selected byte needing data erasing, and then writing the x bytes of data in the data register into the row selected by the byte selection circuit.
Each byte selection circuit of the present invention can simultaneously select a plurality of bytes, so that a simultaneously selected row can be formed using a plurality of bytes, and n-bit data reading of the selected byte can be realized by the arrangement of the column selection circuit and the first data reading unit.
The column selection circuit and the second data reading unit are arranged to realize the reading of total (x-1) x n bit data of unselected bytes, and the (x-1) x n bit data are used for writing back the unselected bytes after reading in the erasing and writing processes, so that the data of the unselected bytes are not damaged; on the basis of the column selection circuit and the second data reading unit, the data erasing and writing unit for processing n-bit data of one byte and the data register for storing x × n-bit data are combined, so that data erasing and writing can be carried out on the selected byte.
Therefore, the EEPROM can well realize reading, erasing and writing the bytes, and simultaneously realize that one byte selection circuit simultaneously selects a plurality of bytes, thereby saving the number of the byte selection circuits and saving the area and the cost of the circuit.
Meanwhile, one byte selection circuit can simultaneously select a plurality of bytes, so that a plurality of simultaneously selected bytes are positioned in the same row, the situation that each bit of the same byte is not adjacent and is separately arranged in the corresponding row can be realized, and the reading crosstalk problem of adjacent bits can be eliminated because each bit of the same byte is not adjacent. The elimination of the read crosstalk problem of adjacent bits means that the spacing between adjacent bits in the same row can be made smaller, thereby reducing the area of the memory array and further reducing the cost.
Drawings
The invention is described in further detail below with reference to the following figures and detailed description:
FIG. 1 is a schematic diagram of a prior art EEPROM memory;
FIG. 2 is a schematic diagram of an EEPROM memory according to an embodiment of the invention.
Detailed Description
As shown in fig. 2, which is a schematic diagram of an EEPROM memory according to an embodiment of the present invention, the EEPROM memory according to the embodiment of the present invention includes:
a plurality of byte selection circuits, four byte selection circuits are shown in fig. 2, which are byte selection circuit one 2a, byte selection circuit two 2b, byte selection circuit three 2c and byte selection circuit four 2d, respectively. Each byte selection circuit is used for simultaneously selecting a plurality of bytes; and making each byte be n bits, and making the number of bytes simultaneously selected by each byte selection circuit be x, so that the number of bits corresponding to one byte selection circuit is x × n. The rows of the memory array are formed by arranging the x × n bit memory cells corresponding to the byte selection circuits, and fig. 2 shows four rows in total, as indicated by the labels 1a, 1b, 1c, and 1d, respectively. Because the same row is provided with a plurality of bytes, the bit numbers of the bytes can be staggered, so that each bit of the same byte is not adjacent, namely the adjacent two bits belong to different bytes, and the n-bit data in the same byte in the same row in the embodiment of the invention are not adjacent.
The memory array is formed by arranging the memory cells with the same bits of each byte selection circuit, and the number of the memory array columns is x multiplied by n; the memory array is shown in dashed box 1.
Each of the byte selection circuits is composed of a selection transistor.
The column selection circuit 3 is used for selecting bits corresponding to x × n columns, each bit corresponding to one bit line, and x × n bit lines are provided, as shown in BL1, BL2, BL3, BL4 to BL (xn-2), BL (xn-1), and BLxn in fig. 1, where xn represents x × n.
The data erasing and writing unit 4 is configured to input a selected byte of data that needs to be erased and written, that is, to input a byte of data for data erasing and writing. The byte data has n bits in total, and for better illustration, the data erasing and writing unit 4 of fig. 2 shows n bits in total, and the data erasing and writing unit 4 correspondingly processes the number of bits of the data.
A first data read unit 5a for reading the selected one byte of data, the reading of n bits also being shown in the first data read unit 5a of fig. 2.
A second data reading unit 5b for reading (x-1) byte data which is in the same row as the selected byte and is not selected; also shown in second data sensing unit 5b of FIG. 2 is the sensing of (x-1) xn bits, corresponding to (x-1) bytes of data.
The data register 6, to which one byte data of the data erasing and writing unit 4 and (x-1) byte data of the second data reading unit 5b are input, is spliced into x byte data, and the data register 6 of fig. 2 also shows a total of x × n bits, corresponding to the x byte data. In the data erasing and writing process, the x bytes of data of the data register 6 are input into the corresponding memory cells in the same row through the column selection circuit 3, so that the memory cells of the selected byte are erased or written.
In the process of data erasing, firstly, erasing the data of a row of x × n-bit memory cells selected by one byte selection circuit; then, one selected byte needing data erasing is subjected to data protection or non-writing, and x bytes of data of the data register 6 are written into the corresponding memory cells in the same row through the column selection circuit 3.
In the process of data writing, firstly, erasing the data of a row of x × n-bit memory cells selected by one byte selection circuit; then, the x bytes of data of the data register 6 are written into the memory cells of the corresponding same row by the column selection circuit 3.
In the data reading process, the row corresponding to the byte to be read is selected by the byte selection circuit, the columns corresponding to all the read bytes are selected by the column selection circuit 3, and then the data of the selected byte is read out by the first data readout unit 5 a.
The operation method of the EEPROM according to the embodiment of the present invention is used for operating the EEPROM according to the embodiment of the present invention shown in fig. 2, and includes three operation modes, namely, a data read operation, a data write operation, and a data erase operation.
The data reading operation comprises the following steps:
the row corresponding to the byte to be read is selected by the byte selection circuit.
The column corresponding to all the read bytes is selected by the column selection circuit 3.
The data of the selected one byte is read out by the first data read-out unit 5 a.
The data writing operation comprises the following steps:
the row corresponding to the byte to be written is selected by the byte selection circuit.
The column corresponding to the byte which does not need to be written is selected by the column selection circuit 3.
(x-1) byte data which is not required to be written is read out by the second data read-out unit 5 b.
One byte of data to be written is input from the data erasing and writing unit 4.
One byte data of the data erasing and writing unit 4 and (x-1) byte data of the second data reading unit 5b are inputted into the data register 6 to be spliced into x byte data.
All x bytes of data of the row selected by the byte selection circuit are erased.
The x bytes of data in the data register 6 are written into the row selected by the byte selection circuitry.
The data erasing operation comprises the following steps:
the row corresponding to the byte to be erased is selected by the byte selection circuit.
The column corresponding to the byte which does not need to be erased is selected by the column selection circuit 3.
(x-1) byte data which do not require erasing are read out by the second data read-out unit 5 b.
One byte of data is input from the data erasing and writing unit 4.
One byte data of the data erasing and writing unit 4 and (x-1) byte data of the second data reading unit 5b are inputted into the data register 6 to be spliced into x byte data.
All x bytes of data of the row selected by the byte selection circuit are erased.
After data protection or non-writing of a selected byte requiring data erasure, x bytes of data in the data register 6 are written into the row selected by the byte selection circuit.
The present invention has been described in detail with reference to the specific embodiments, but these should not be construed as limitations of the present invention. Many variations and modifications may be made by one of ordinary skill in the art without departing from the principles of the present invention, which should also be considered as within the scope of the present invention.

Claims (8)

1. An EEPROM memory, comprising:
a plurality of byte selection circuits, each for selecting a plurality of bytes simultaneously; making each byte be n bits, the number of bytes simultaneously selected by each byte selection circuit is x, the number of bits corresponding to one byte selection circuit is x × n, and the n bits of data in the same byte in the same row are not adjacent; the rows of the memory array are formed by arranging the x multiplied by n bit memory cells corresponding to the byte selection circuits; the memory array is formed by arranging the memory cells with the same bits of each byte selection circuit, and the number of the memory array columns is x multiplied by n;
a column selection circuit for selecting bits corresponding to the x × n columns;
the data erasing and writing unit is used for inputting one byte of data which needs to be erased and written;
a first data reading unit for reading the selected one byte data;
a second data reading unit for reading (x-1) byte data which is in the same row as the selected byte and is not selected;
a data register to which one byte data of the data erasing and writing unit and (x-1) byte data of the second data reading unit are input to be spliced into x byte data; in the data erasing and writing process, the x bytes of data of the data register are input into the corresponding memory cells in the same row through the column selection circuit, so that the memory cells of the selected byte are erased or written.
2. The EEPROM memory of claim 1, wherein: each of the byte selection circuits is composed of a selection transistor.
3. The EEPROM memory of claim 1, wherein: in the process of data erasing, firstly, erasing the data of a row of x × n-bit memory cells selected by one byte selection circuit; then, data protection or non-writing is carried out on the selected byte needing data erasing, and x bytes of data of the data register are written into the corresponding storage units in the same row through the column selection circuit.
4. The EEPROM memory of claim 1, wherein: in the process of data writing, firstly, erasing the data of a row of x × n-bit memory cells selected by one byte selection circuit; then, the x bytes of data of the data register are written into the memory cells of the corresponding same row by the column selection circuit.
5. The EEPROM memory of claim 1, wherein: in the data reading process, the row corresponding to the byte to be read is selected through the byte selection circuit, the columns corresponding to all the read bytes are selected through the column selection circuit, and then the data of the selected byte is read out through the first data reading unit.
6. A method of operating an EEPROM memory as claimed in claim 1, characterized by comprising three operation modes, namely a data read operation, a data write operation, a data erase operation;
the data read operation includes the steps of:
selecting a row corresponding to a byte to be read through the byte selection circuit;
selecting columns corresponding to all read bytes through the column selection circuit;
reading out the selected one byte of data by the first data readout unit.
7. The method of operating an EEPROM memory of claim 6, wherein the data write operation comprises the steps of:
selecting a row corresponding to a byte to be written through the byte selection circuit;
selecting a column corresponding to a byte which does not need to be written by the column selection circuit;
reading out (x-1) byte data that does not need to be written by the second data reading unit;
inputting one byte of data to be written from the data erasing and writing unit;
inputting one byte data of the data erasing and writing unit and (x-1) byte data of the second data reading unit into the data register to be spliced into x byte data;
erasing all x bytes of data of the row selected by the byte selection circuit;
writing x bytes of data in the data register into the row selected by the byte selection circuitry.
8. The method of operating an EEPROM memory of claim 6, wherein the data erasing operation includes the steps of:
selecting a row corresponding to a byte to be erased through the byte selection circuit;
selecting a column corresponding to a byte which does not need to be erased through the column selection circuit;
reading out (x-1) byte data that does not require erasing by the second data reading unit;
inputting one byte of data from the data erasing and writing unit;
inputting one byte data of the data erasing and writing unit and (x-1) byte data of the second data reading unit into the data register to be spliced into x byte data;
erasing all x bytes of data of the row selected by the byte selection circuit;
and performing data protection or non-writing on the selected byte needing data erasing, and then writing the x bytes of data in the data register into the row selected by the byte selection circuit.
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102592668A (en) * 2011-01-04 2012-07-18 三星电子株式会社 Non-volatile memory device of performing partial-erase operation, memthod thereof, and apparatuses having the same
CN103426467A (en) * 2012-05-14 2013-12-04 三星电子株式会社 Memory device, memory system, and operating methods thereof

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102592668A (en) * 2011-01-04 2012-07-18 三星电子株式会社 Non-volatile memory device of performing partial-erase operation, memthod thereof, and apparatuses having the same
CN103426467A (en) * 2012-05-14 2013-12-04 三星电子株式会社 Memory device, memory system, and operating methods thereof

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