CN106877724A - A kind of inverter delay compensation method based on critical current control - Google Patents
A kind of inverter delay compensation method based on critical current control Download PDFInfo
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- CN106877724A CN106877724A CN201710186160.3A CN201710186160A CN106877724A CN 106877724 A CN106877724 A CN 106877724A CN 201710186160 A CN201710186160 A CN 201710186160A CN 106877724 A CN106877724 A CN 106877724A
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- control
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- inverter
- critical current
- current control
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Classifications
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M7/00—Conversion of ac power input into dc power output; Conversion of dc power input into ac power output
- H02M7/42—Conversion of dc power input into ac power output without possibility of reversal
- H02M7/44—Conversion of dc power input into ac power output without possibility of reversal by static converters
- H02M7/48—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M7/53—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M7/537—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters
- H02M7/5387—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration
- H02M7/53871—Conversion of dc power input into ac power output without possibility of reversal by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only, e.g. single switched pulse inverters in a bridge configuration with automatic control of output voltage or current
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J3/00—Circuit arrangements for ac mains or ac distribution networks
- H02J3/38—Arrangements for parallely feeding a single network by two or more generators, converters or transformers
- H02J3/381—Dispersed generators
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Inverter Devices (AREA)
Abstract
The invention discloses a kind of inverter delay compensation method based on critical current control, belong to converters technical field.Inverter based on critical current control realizes the Sofe Switch of switching tube by controlling inductive current two-way flow, and actually controls time delay that the non-ideal factors such as the comparator used in circuit, PWM module and drive circuit produce and the Dead Time of Sofe Switch process to bring the control deviation of inductive current.Traditional dead area compensation mode is generally directed to fixed-frequency control, and ignore the parasitic capacitance of switching tube, it is not suitable for critical current control, it is of the invention to consider all control time delay and the influences of Dead Time in critical current control comprehensively, the control deviation of inductive current can be accurately compensated, improves the waveform quality of output grid-connected current.
Description
Technical field
The present invention relates to a kind of inverter delay compensation method based on critical current control, belong to converters
Technical field.
Background technology
Combining inverter is with a wide range of applications in the occasion such as generation of electricity by new energy and distributed power generation.Improve inverter
Switching frequency be combining inverter design important trend, improving switching frequency can reduce the volume of passive element, and then
The power density of combining inverter can be improved.However, improving switching frequency can not only increase switching loss, can also bring tighter
The electromagnetic interference problem of weight.
The application of soft switch technique can effectively reduce switching loss, contribute to the raising of switching frequency, reduce inverter
Volume, while electromagnetic interference can also be reduced.Current soft switch technique is broadly divided into passive type soft switch technique and active
Soft switch technique.Passive type soft switch technique mainly includes passive flexible switch technology and active soft switching technology.But passive type
Soft switch technique is required for extra device and auxiliary circuit, not only increases volume, cost and the weight of combining inverter, also
Increased the complexity of control.And the active soft switch technique for being based on critical current control can not increase any extra device
In the case of part and circuit, by controlling the two-way flow in each switch periods of inverter side inductive current, power switch is realized
The no-voltage of pipe is open-minded, and accompanying drawing 1 gives the inductive current waveform diagram under main circuit topology and the control strategy.Accompanying drawing
1 (a) is main circuit topology, i.e. full bridge inverter, without any additional devices of increase and auxiliary circuit.Accompanying drawing 1 (b) is the control
The lower inverter side inductive current waveform diagram of strategy, inductive current two-way flow in each switch periods are made, negative current is
Switching tube realizes that ZVS provides condition.
The features such as in order to using the flexible and convenient of software prediction control, accuracy and rapidity of hardware reset control,
Critical current control strategy is realized with the numerical model analysis control mode that hardware reset control is combined using software prediction control.
In line voltage positive half period, inductive current coenvelope line is controlled by software calculating service time, under switched inductors electric current
The control of envelope is realized by hardware reset, such as shown in accompanying drawing 2 (a).Because actual control circuit and power switch tube drives
The presence of the control time delay that the non-ideal factors such as circuit are produced, has larger between the upper and lower envelope of inductive current and expected setting
Deviation, causes output current to be distorted, and output current wave quality is reduced, such as shown in accompanying drawing 2 (b).Mend in traditional dead band
Mode is repaid mainly for fixed switching frequency, is typically ignored switching tube and is exported the influence of parasitic capacitance, and be based on critical current
The switching frequency of the control strategy of pattern is change, and utilizes inductive current in Dead Time to parasitic capacitance discharge and recharge
The Sofe Switch of switching tube is realized, actual inductive current has certain deviation, therefore traditional compensation way discomfort in Dead Time
For critical current Schema control.
The content of the invention
The purpose of the present invention is directed to the inverter based on critical current control and causes defeated by control time delay and Dead Time
Go out grid-connected current aberration problems and traditional dead area compensation mode defect, there is provided a kind of accurate time delay and Dead Time it is real-time
Compensation method.
The purpose of the present invention is achieved through the following technical solutions：
A kind of inverter delay compensation method based on critical current control is by real-time calculating compensation control time delay and extremely
Area's time corrects the deviation of inductive current, so as to solve the problems, such as distortion and the Zero-crossing Distortion of grid-connected current.The compensation of delay
Method calculates control time delay and Dead Time by DC bus-bar voltage and the output voltage of sampling, in real time causes the inclined of controlled quentity controlled variable
Difference, the service time of inductive current reset line, the software prediction control to hardware reset control compensates, so as to eliminate inductance
The control deviation of electric current.
The present invention has the advantages that：
(1) additional hardware circuit need not be increased, is only calculated in real time by software and realized time delay and dead area compensation；
(2) by time delay and dead band real-Time Compensation, output current wave quality is improved, the total harmonic wave for reducing output current loses
Very.
Brief description of the drawings
Accompanying drawing 1 is main circuit topology and the inverter side inductive current waveform diagram based on critical current control；
Accompanying drawing 2 is prolonged using the numerical model analysis control mode and control of hardware reset control and software prediction control combination
When and Dead Time to inductive current and the influence schematic diagram of output current；
Accompanying drawing 3 is the voltage current waveform that hardware reset control and software prediction control breaker in middle pipe switch handoff procedure
Figure；
Accompanying drawing 4 is the modal graph that switching tube switchs handoff procedure when hardware reset is controlled；
Accompanying drawing 5 is the modal graph that switching tube switchs handoff procedure when software prediction is controlled；
Accompanying drawing 6 is inverter output current and inductive current simulation waveform before and after time delay and dead area compensation, wherein, accompanying drawing
6 (a) is the current waveform for not adding time delay and dead area compensation, and output current THD is 3.43%, and accompanying drawing 6 (b) prolongs to add reset control
When and dead area compensation current waveform, output current THD be 2.98%, accompanying drawing 6 (c) for plus PREDICTIVE CONTROL with reset control time delay
With the current waveform of dead area compensation, output current THD is 1.12%；
Accompanying drawing 7 is inverter output current and inductive current experimental waveform figure under semi-load before and after time delay and dead area compensation,
Wherein, accompanying drawing 7 (a) be under semi-load plus time delay and dead area compensation current waveform, output current THD is respectively 3.8%, accompanying drawing
7 (b), to add PREDICTIVE CONTROL and reset control time delay and the current waveform of dead area compensation under semi-load, output current THD is 1.2%；
Accompanying drawing 8 is inverter output current and inductive current experimental waveform figure under fully loaded before and after time delay and dead area compensation,
Wherein, accompanying drawing 8 (a) is the current waveform for not adding time delay and dead area compensation under being fully loaded with, and output current THD is 2.8%, accompanying drawing 8 (b)
To be fully loaded with the current waveform of lower plus PREDICTIVE CONTROL and reset control time delay and dead area compensation, output current THD is 1.2%；
Accompanying drawing 9 is the inverter delay compensation method implementing procedure figure based on critical current control
Designation in the figures above：VdcIt is d-c bus voltage value, VgIt is line voltage virtual value, Q1、Q2、Q3、Q4
Respectively four switching tubes of full bridge inverter, LsIt is inverter side switched inductors, CoIt is output filter capacitor, LoFor output is filtered
Ripple inductance, iLsIt is inverter side switched inductors electric current, IBIt is inductive current reset line current value, Δ iLower、ΔiUpperIt is respectively hard
Part reset control and the inductive current control deviation of software prediction control, ioIt is output current, CMP is that High Speed Analog comparator is defeated
Go out, PWM is switching tube Q1、Q2Corresponding pwm signal, vGS1、vGS2Respectively switching tube Q1、Q2Drive signal, vds1、vds2Point
Wei not switching tube Q1、Q2Drain-source voltage, tdLower、tdUpperRespectively switching tube Q1、Q2Corresponding Dead Time, t, t0~
t14It is the time.
Specific embodiment
Technical scheme is described in detail with reference to accompanying drawing.
Inverter delay compensation method of the present invention based on critical current control is according to control time delay and Dead Time to electricity
The influence of inducing current, output current, calculates the compensation rate of inductive current in real time, eliminates the control deviation of inductive current.Divide below
Inductive current control deviation caused by analysis control time delay and Dead Time.
The control mode that resets I：As shown in accompanying drawing 4 (a), switching tube Q2、Q4Conducting, inverter side inductive current linear decline is main
There are following three phases：
[the t of stage one0-t1]：t0The lower limit that moment inverter side inductive current linearly decreases to the setting of High Speed Analog comparator is answered
Place value.By the big signal response time t of comparatorCMPComparator exports fault-signal to PWM module afterwards.PWM module is by event
Barrier triggering response time tFLTAfter reset itself when base and overturn PWM output signal.
[the t of stage two1-t2]：t1Moment PWM output signal overturns.Through the shut-off time delay t of overdrive circuitoffDRVAfterwards, Q2's
Drive signal begins to decline.
[the t of stage three2-t3]：By turn-off time tfDRVAfterwards, t3Moment switching tube Q2Drive signal drop to its driving gate
Sill voltage vt, switching tube Q2Shut-off.
Mode II：As shown in accompanying drawing 4 (b), switching tube Q2After shut-off, inverter side inductive current starts switch tube Q1、Q2's
Junction capacity carries out discharge and recharge, switching tube Q1、Q2Drain-source voltage difference linear decline, linear rise：
[the t of stage four3-t4]：t4Moment switching tube Q2Drain-source voltage rise to line voltage vg, now inverter side inductance
Both end voltage is zero, and inductive current reaches maximum negative value, and (switching tube equivalent junction capacitance is Cs)。
[the t of stage five4-t5]：Switching tube Q1Drain-source voltage continue linear decline, t5Moment drain-source voltage drops to
Zero.
Mode III：As shown in accompanying drawing 4 (c), switching tube Q1Drain-source voltage drop to zero after, its body diode starts
Conducting：
[the t of stage six5-t6]：After base resets during PWM module, by the Dead Time t for settingdLowOutput switch pipe Q afterwards1's
Pwm signal.
t6-t5=tdLower-toffDRV-tfDRV-tZVSLower (3)
Can be drawn according to model analysis, the lower limit reset values of setting to inductive current are dropped to from inverter side inductive current
The time for reaching maximum negative value is exactly the time delay summation resetted in control, it can be deduced that compensate size of current accordingly：
tdlyLower=tCMP+tFLT+toffDRV+tfDRV+tCLower (4)
When the drain-source voltage of switching tube drops to zero, corresponding drive signal begins to ramp up, it can be deduced that realize soft opening
Minimum dead band size (the Δ t of passtrnDRVTo turn off time delay and opening the difference of time delay)：
Inverter side inductive current coenvelope line is using each several part time delay situation of PREDICTIVE CONTROL and the reset control of lower envelope line
System is similar, modal graph as shown in Figure 5, unlike PREDICTIVE CONTROL base when not having a High Speed Analog comparator reset PWM module
Time delay, and total time delay of PREDICTIVE CONTROL is the upper and lower envelope of inverter side inductive current corresponding time and switching tube pwm signal
Difference between service time：
Computing hardware can be resetted control time delay and the inductive current deviation brought of dead band in real time according to formula (5), to electricity
Inducing current reset line is compensated, according to formula (7) can the time delay of software for calculation PREDICTIVE CONTROL and dead band in real time, during to opening
Between compensate, the time delay of two kinds of control modes and dead area compensation can eliminate the control deviation of inductive current, improve output simultaneously
The waveform quality of net electric current.
Accompanying drawing 6 gives the output current and inductive current simulation waveform of inverter before and after time delay and dead area compensation.
Reset in the case of control and PREDICTIVE CONTROL time delay and dead band all uncompensations, the upper and lower envelope of inductive current exceedes default bag
Winding thread, output current distortion is serious, and its THD is up to 3.43%, such as shown in accompanying drawing 6 (a)；Adding reset control time delay and dead band benefit
After repaying, reset line is expected -1A under inductive current, and output current THD is reduced to 2.98%, but also larger distortion, such as attached
Shown in Fig. 6 (b)；At the same time plus after reset control and PREDICTIVE CONTROL time delay and dead area compensation, the upper and lower envelope of inductive current is full
The expected setting of foot, output current is reduced to 1.14% without substantially distortion, its THD, such as shown in accompanying drawing 6 (c).
Accompanying drawing 7 is not add current waveform figure of the inverter under semi-load and full-load run before compensation, it can be seen that actual electricity
Inducing current has relatively large deviation with default envelope, causes output current to have substantially distortion, and sine degree is poor, output current THD
Up to 3.8%, 2.8%.Accompanying drawing 8 is to add current waveform figure of the inverter under semi-load and full-load run after compensation, can be seen
The inductive current gone out after compensation is basically identical with default envelope, and the distortion of output current is greatly improved, and improves just
String degree, output current THD drops to 1.2%.Inverter delay compensation method based on critical current control can be mended accurately
The control deviation of inductive current is repaid, distortion and the Zero-crossing Distortion of output current is greatly reduced, the waveform quality of output current is improved.
Above content described in this specification is only illustration made for the present invention.Technology belonging to of the invention
The technical staff in field can be made various modifications or supplement to described specific embodiment or be substituted using similar mode, only
Without departing from the content of description of the invention or to surmount scope defined in the claims, guarantor of the invention all should be belonged to
Shield scope.
Claims (3)
- It is 1. a kind of to mix the combining inverter delay compensation method for controlling based on critical current, it is characterised in that：By calculating the influence for controlling time delay and dead band to inductive current in real time, change switching tube and open or turn-off time reality Now accurate compensation control time delay and dead time effect, improve output grid-connected current waveform quality.
- 2. according to claim 1 it is a kind of based on critical current control inverter delay compensation method, it is characterised in that：Main power circuit topology is using full-bridge inverter, half-bridge inverter or other any inversions for realizing critical current control Device topology.
- 3. according to claim 1,2 it is a kind of based on critical current control inverter delay compensation method, it is characterised in that：Modulation system using unipolarity modulation, bipolar modulation, unipolarity and bipolarity hybrid modulation or other realize it is critical The modulation system of current control.
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110995033A (en) * | 2019-12-27 | 2020-04-10 | 华南理工大学 | PWM rectifier current prediction control method with dead zone compensation |
| CN111837337A (en) * | 2018-03-16 | 2020-10-27 | 罗伯特·博世有限公司 | Method and device for setting dead time of switching element of half bridge and inverter |
| CN113067335A (en) * | 2021-04-12 | 2021-07-02 | 西安麦格米特电气有限公司 | Current compensation method and circuit adopting critical current control strategy |
| CN114336881A (en) * | 2022-01-05 | 2022-04-12 | 南方电网电力科技股份有限公司 | Battery management active equalization frequency reduction control method and related device |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000014014A (en) * | 1998-06-29 | 2000-01-14 | Matsushita Electric Works Ltd | Inverter device |
| CN102307017A (en) * | 2011-09-16 | 2012-01-04 | 浙江大学 | Control method applied to active-clamp flyback miniature photovoltaic grid-connected inverter device |
| CN103414368A (en) * | 2013-07-25 | 2013-11-27 | 西安交通大学 | Dead-zone compensation method of three-phase inverter |
| CN104638957A (en) * | 2014-12-25 | 2015-05-20 | 南京航空航天大学 | Grid-connected inverter zero crossing point current distortion suppression method of unipolar critical current continuous control strategy |
| CN106100412A (en) * | 2016-03-21 | 2016-11-09 | 南京航空航天大学 | A kind of based on critical current mode continuous control strategy inverter light load efficiency optimization method |
-
2017
- 2017-03-20 CN CN201710186160.3A patent/CN106877724A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2000014014A (en) * | 1998-06-29 | 2000-01-14 | Matsushita Electric Works Ltd | Inverter device |
| CN102307017A (en) * | 2011-09-16 | 2012-01-04 | 浙江大学 | Control method applied to active-clamp flyback miniature photovoltaic grid-connected inverter device |
| CN103414368A (en) * | 2013-07-25 | 2013-11-27 | 西安交通大学 | Dead-zone compensation method of three-phase inverter |
| CN104638957A (en) * | 2014-12-25 | 2015-05-20 | 南京航空航天大学 | Grid-connected inverter zero crossing point current distortion suppression method of unipolar critical current continuous control strategy |
| CN106100412A (en) * | 2016-03-21 | 2016-11-09 | 南京航空航天大学 | A kind of based on critical current mode continuous control strategy inverter light load efficiency optimization method |
Non-Patent Citations (1)
| Title |
|---|
| 魏涛: ""高效光伏并网微型逆变器研究"", 《中国优秀硕士学位论文全文数据库 工程科技II辑》 * |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111837337A (en) * | 2018-03-16 | 2020-10-27 | 罗伯特·博世有限公司 | Method and device for setting dead time of switching element of half bridge and inverter |
| CN110995033A (en) * | 2019-12-27 | 2020-04-10 | 华南理工大学 | PWM rectifier current prediction control method with dead zone compensation |
| CN110995033B (en) * | 2019-12-27 | 2021-05-14 | 华南理工大学 | PWM rectifier current prediction control method with dead zone compensation |
| CN113067335A (en) * | 2021-04-12 | 2021-07-02 | 西安麦格米特电气有限公司 | Current compensation method and circuit adopting critical current control strategy |
| CN114336881A (en) * | 2022-01-05 | 2022-04-12 | 南方电网电力科技股份有限公司 | Battery management active equalization frequency reduction control method and related device |
| CN114336881B (en) * | 2022-01-05 | 2023-08-29 | 南方电网电力科技股份有限公司 | Battery management active equalization down-conversion control method and related device |
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