CN106875974A - A kind of OTP storage devices and the method for accessing otp memory - Google Patents
A kind of OTP storage devices and the method for accessing otp memory Download PDFInfo
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- CN106875974A CN106875974A CN201710156206.7A CN201710156206A CN106875974A CN 106875974 A CN106875974 A CN 106875974A CN 201710156206 A CN201710156206 A CN 201710156206A CN 106875974 A CN106875974 A CN 106875974A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
- G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
- G11C2216/26—Floating gate memory which is adapted to be one-time programmable [OTP], e.g. containing multiple OTP blocks permitting limited update ability
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Abstract
The invention discloses a kind of OTP（Disposable programmable）Storage device and the method for accessing otp memory, the operation to otp memory is realized according to methods and apparatus of the present invention, and according to the configurable interface sequence that otp memory instruction produces correspondence different instruction that accesses.Simultaneously, in to otp memory programming operation, propose a kind of brand-new, efficient, programmed method of high reliability, the method that the programming of 16 subpulses is at most allowed up to same address is taken for the redundancy treatment to OTP program address and in programming operation, easily occurs programming error when high degree solves the problems, such as to access otp memory, the reliability of otp memory is substantially increased, at utmost realizes utilizing otp memory.
Description
Technical field
The present invention relates to a kind of disposable programmable（OTP, One Time Programable）Memory area, especially relates to
And a kind of method and apparatus for accessing otp memory.
Background technology
With continuing to develop for electronic information society, data storage requirement amount shows explosive growth.With MASK（Cover
Film）And Flash（Flash memory）Memory is compared, and otp memory has the advantage of the two concurrently, existing certain flexibility, and cost is again not
It is too high.Also therefore in embedded system or chip internal, as not modifiable information after storage one-time programming or pair plus
The storage of close chip keys information plays irreplaceable effect.Otp memory is highly suitable for application-specific data
Secondary programmable storage, in an on-chip system（SOC, System On Chip）, it is necessary to store many specific disposable in system
Information, such as chip serial number, interface close information and the key information about chip secure etc., and these information are being entirely
Programming does not allow client to go to change in system test chip after entering, and these information need not be wiped, i.e., can not after one-time programming
Modification.Reticle is made using MASK masks, flexibility is too poor, it is again too high using Flash flash memories cost.Therefore, deposited using OTP
Reservoir stores this kind of customizing messages, at utmost reduces hardware and research and development expense.
Otp memory is programmed and is read and during other access, it is necessary to a hardware control, access OTP is deposited
The concrete operations of reservoir determine whether effective instruction and are converted to the specific sequential for accessing otp memory by analysis instruction, press
Interface sequence according to otp memory part completes reading, programming, reset, sleep, wake operation.Fig. 2 is to access otp memory
Block diagram, including the various instructions of otp memory are accessed, the hardware control needs to be produced accordingly according to different access instructions
Sequential, completes the access to otp memory.
The characteristics of due to otp memory to storage and the cost not high of some customizing messages, it is subject to more in memory area
It is widely applied to get over.Hardware circuit is based on providing different sequence circuits driving otp memories according to different instructions, realizes
Access to otp memory part.Otp memory part due to the factor of itself, the error-prone in reading and programming process, such as
Error rate is reduced in where OTP being programmed and read, the reliability of otp memory, the technology as otp memory field is improved
Difficult point.Secondly, as safety chip is more and more widely applied, after otp memory is realized to the programming of key information, it is undesirable to
User reads its key information, therefore is accomplished by doing it specially treated when OTP key informations are read, and it is special how to do
Treatment is so as to ensure that the key information for being stored in OTP does not get compromised, it is ensured that chip secure technology is also current accessed otp memory skill
The scheme that art is short of.Furthermore, increase fault-tolerant hardware circuit unit in otp memory chip internal and largely increased
Otp memory chip area, and it is portable bad.These shortcomings all greatly increase access otp memory the research and development time and
Cost.
The content of the invention
The technical problems to be solved by the invention are to provide a kind of method and apparatus for accessing otp memory, it is therefore an objective to can
Otp memory is accessed with flexible configuration different instruction and the access otp memory interface sequence of corresponding instruction is produced, it is right to complete
The programming of otp memory, reading, reset, wake-up, sleep operation.The inventive method is used to OTP programming operations, largely
Otp memory yield is improve, solves the problems, such as that OTP is error-prone in programming process, drastically increase otp memory part
Reliability.And the important information key information to storing in OTP has made correspondingly scrambling treatment when reading, and protects data
Security.
In order to solve the above technical problems, the invention provides a kind of method for accessing otp memory, comprising the following steps：
Step 1：Defining series of instructions is used to operate otp memory；
Step 2：Upper electricity reads otp memory regional information, including otp memory pattern information, otp memory interface envelope
Close information, otp memory system realm closing information, the closing of otp memory user area information and key field information；
Step 3：The instruction of the defined operation otp memory of parsing, when accessing otp memory according to the order-driven for parsing
Sequence；
Step 4：Into board mode of operation, otp memory programming key instruction is sent, parsing programs key instruction, and by OTP
Timing sequencer produces the corresponding access otp memory interface sequence of the instruction, and key data is programmed in otp memory,
Key information is read, the key information to reading out carries out scrambling treatment；
Step 5：Into normal mode of operation, the instruction of otp memory programming information is sent, program chip serial number, OTP sequential hair
Raw device produces programming otp memory sequential, and chip serial number is programmed into corresponding region in otp memory；
Step 6：The instruction of otp memory programming information is sent, by command decoder to Instruction decoding, and is occurred by OTP sequential
Device produces programming otp memory sequential, is sent to otp memory part, completes DLL closing information and programing system region
Information.
Further, the series of instructions operation otp memory that defines includes：CPU or board pattern configurations are provided
The different instruction of otp memory is accessed, the series of instructions is used to operate otp memory, completes the volume to otp memory
Journey, reads, and resets, the operation such as wake-up.The series of instructions includes：Otp memory sleep pattern, otp memory wake up mould
Formula, reset otp memory, otp memory programming information, otp memory programming key, reading otp memory and otp memory
Self test mode；
The instruction of the defined operation otp memory of the parsing includes：
Definition accesses the specific instruction of otp memory；
Instructed etc. otp memory to be visited；
Check otp memory instruction；And
Judge to access whether otp memory instruction is effective instruction, OTP timing sequencers be then sent to if effective instruction,
Then terminate the access of otp memory if illegal command；
The OTP timing sequencers, for produce for produce parse effective access otp memory instruction it is specific when
Sequence；
Otp memory programming key instruction or the instruction of otp memory programming information, using to otp memory program address
Redundancy treatment and is taken that the programming operation of same address is implemented that 16 subpulses can be allowed up in programming operation and compiles
The method of journey.
The distribution of the address to otp memory programming operation carries out redundancy treatment, including：
When carrying out a data programming operation to otp memory, this data are mapped to 4 physical address of otp memory simultaneously
Program successively, if wherein being programmed successfully no less than 3 bit address, then it is assumed that a data for being configured is programmed successfully, otherwise it is assumed that
This data are not programmed successfully.
Each data program operation in described 4 physical address to otp memory includes：
The configuration address to be programmed, program address is equal to the initial programming address for providing；
Apply 3 programming pulse voltages in initial programming address location；
Apply to continue to 1 programming pulse voltage on the basis of 3 programming pulse voltages；
Programming verification operation；
Whether the data that the data judging obtained by programming verification operation is programmed are 1, wherein, the data of otp memory programming
It is " 1 " that unprogrammed data are " 0 ", if programming data is " 1 ", then it represents that this programming operation success to the address, continues
The programming operation of next address is performed in the method, if programming data is " 0 ", performs next step；
Determine whether to have added 16 programming pulse voltages in the position, if being not up in the specified otp memory address location
Added 16 program voltages, then continue to pulse voltage, often applies pulsatile once voltage and is programmed whether data are " 1 "
Judge, then judge whether programming pulse voltage is programmed to the cycle criterion of 16 times；If having added 16 program voltages also in the position
Be data be " 0 ", then program fail.
Present invention also offers a kind of device including otp memory and access otp memory, wherein, the OTP storages
Device includes：Chip serial number region, for storage chip sequence number；Interface closed area, for storing relevant interface closing letter
Breath；Otp memory mode of operation：Operator scheme for storing otp memory, including board mode of operation and normal work mould
Formula；System lock control area, the control information for storing closed system region；User closes control area, for storing
The control information of user area；System key region, for storing key information region；And user area, for storing user
The information to be stored.
The method have the benefit that：The method and apparatus of otp memory are accessed there is provided a kind of, and can be led to
CPU or the instruction of board both of which flexible configuration different operating are crossed, and when producing the access otp memory interface of corresponding instruction
Sequence.Strict encryption is carried out outside otp memory part to customizing messages key information, so as to be effectively guaranteed chip
Security.The method that programming pulse voltage is repeatedly applied using address fault-tolerant processing and in same program address to OTP programmings,
Ensure data correct programming to otp memory corresponding region, solve the problems, such as that OTP is error-prone in programming process, it is ensured that number
According to correctness, largely improve otp memory yield, greatly strengthen access otp memory part reliability.
Brief description of the drawings
Fig. 1 is otp memory regional distribution chart according to an embodiment of the invention.
Fig. 2 is the operational block diagram of access otp memory according to an embodiment of the invention.
Fig. 3 is OTP storage control circuits block diagram according to an embodiment of the invention.
Fig. 4 is electric reading circuit operational flowchart on otp memory according to an embodiment of the invention.
Fig. 5 is otp memory command decoder analysis instruction method according to an embodiment of the invention.
Fig. 6 is otp memory programming according to an embodiment of the invention, the address distribution of read operation and redundancy treatment
Figure.
Fig. 7 is the programmed algorithm flow of otp memory programmed algorithm modular circuit according to an embodiment of the invention
Figure.
Specific embodiment
The present invention is further detailed explanation with reference to the accompanying drawings and detailed description.Present invention is mainly used for visit
Ask otp memory, realize the different operating to otp memory, including programming, read, reset, waking up, sleep, OTP test oneself behaviour
Make.When being programmed to otp memory, easy programming error causes the data can not to be correctly stored in otp memory part, the present invention
Propose to the treatment of program address redundancy, meanwhile, same program address can be allowed to apply to be up to 16 programming pulse voltages, sternly
Ensure that in programming data correct programming to otp memory part lattice, programming key information is carried out using board mode of operation
It is programmed in otp memory, when key information is read, using scrambling circuit to the key that is read out from otp memory part
Information is scrambled, so as to ensure the high safety of key information, meets the protection requirement of its specific information.Details are as follows.
Referring to Fig. 1, in the embodiment of the present invention, the area distribution of otp memory is：Chip serial number region, for storing
Chip serial number；Interface closed area, for storing relevant interface closing information；Otp memory mode of operation：For storing
The operator scheme of otp memory, including board mode of operation and normal mode of operation；System lock control area, for storing
The control information in closed system region；User closes control area, the control information for storing user area；System key area
Domain, for storing key information region；User area, for storing user's information to be stored.
Referring to Fig. 2, to access the block diagram of otp memory, realize including the operation of otp memory：Program, read, answer
Position, wake-up, sleep, OTP self-test operations, are completed, by OTP controller circuit as shown in Fig. 2 the otp memory to be accessed refers to
Order includes as follows：
Otp memory sleep pattern, makes OTP be in sleep pattern, i.e., current OTP is in off position, can carry out not
The instruction is placed in when with otp memory, the power consumption of system is reduced, the configuration of the instruction can be complete by CPU or board pattern
Into；
Otp memory awakening mode, by OTP from sleep mode wakeup, when operation otp memory part is needed, such as toward OTP storages
Device programming data, need otp memory is switched into awakening mode from sleep pattern first when reading data, the instruction is matched somebody with somebody
Putting can be by CPU or board Pattern completion；
Reset otp memory, needed to reset otp memory before otp memory is operated, and was cut between instruction
It is also required to the operation reset otp memory part that resets to it when changing, the configuration of the instruction can be by CPU or board mould
Formula is completed；
Otp memory programming information, needs to configure the instruction, such as chip serial number, chip interface when to OTP programming operations
Closing information, the programming of system information instruct the programming operation for completing otp memory by configuring OTP_PROGRAMINFO, should
The configuration of instruction can be by CPU or board Pattern completion；
Otp memory programs key, just for storage of the key information in otp memory is programmed, in order to ensure key information
Strict safety, the instruction must be configured by board pattern；
Otp memory is read, the read operation to otp memory regional information is performed, the configuration of the instruction can be by CPU
Or board Pattern completion；
Otp memory self test mode, performs the selftest to otp memory part, and the configuration of the instruction can be by CPU or machine
Platform Pattern completion.
A kind of device for accessing otp memory, including the CPU that is sequentially connected or board complete instruction configuration, upper electricity and read
Circuit, bus control circuit, MUX circuit, OTP timing generator circuits, programmed algorithm modular circuit, scrambling circuit,
Otp memory part, all modules are realized using digital logic circuit；
The CPU or board mode configuration circuit：For the instruction of configuration access otp memory；
The upper electric reading circuit：For during electricity, reading the information of otp memory regional, bag first on otp memory
Include otp memory pattern information, otp memory interface closing information, otp memory system realm closing information, otp memory
Close information and key field information in user area；
The bus control circuit：Including command register circuit and command decoder circuit, for loading CPU or board institute
The series of instructions of configuration, and parse the instruction of defined operation otp memory；Command register circuit is used to store CPU
Or the series of instructions that board is configured, the instruction translation that command decoder circuit realiration will be configured is into specific effective instruction
And it is sent to MUX.
The MUX：Produced for selecting upper electric reading circuit to read information command to be sent to the OTP time sequential routines
The instruction of controller or bus control circuit is sent to the OTP time sequential routines and produces controller；
The OTP timing generator circuits：For the specific sequence circuit for producing different access otp memory to instruct, including again
Position, wake-up, programming, reading, sleep operation, the instruction generation of the concrete operations otp memory configured according to CPU or board are right
The access otp memory sequence circuit answered, is sent to otp memory part interface；
The programmed algorithm modular circuit：For the programming operation to otp memory, solution programs easily to go out in otp memory
Wrong problem, when otp memory operation is programmed, the address to be programmed to otp memory carries out superfluous the algorithm circuit realiration
Remaining treatment and take the applying can to allow 16 treatment of programming pulse voltage the programming of each data, the modular circuit is by total
Word circuit realiration, adoption status machine control realization programmed algorithm.
The scrambling circuit：It is encrypted for reading key information from otp memory, i.e. the key to reading
The scrambled circuit of data is scrambled so that key data seen by user is not the data for being really programmed to otp memory,
So as to be protected safely to key information.
It is OTP storage control circuits block diagram according to an embodiment of the invention referring to Fig. 3.Otp memory is accessed, it is first
First need to issue operational order to otp memory using CPU or board pattern.To send instructions under otp memory including：Normally
Mode of operation and board test pattern, normal mode of operation are that the instruction of otp memory, board are operated using CPU configurations
Test pattern is then issued using ATE board to operational order.The present invention uses CPU or board both of which
Neatly otp memory is realized to access.By MUX（MUX）The instruction that circuit is configured to CPU or board is passed
Deliver to bus control unit；Shown in Figure 2, the instruction that CPU or board are configured includes：Otp memory sleep pattern, OTP are deposited
Reservoir awakening mode, reset otp memory, otp memory programming information, otp memory programming key, reading otp memory
And otp memory self test mode.The instruction that CPU or board configure these operation otp memories is sent to bus marco mould
Block circuit, these instruction storages are in bus control circuit ground command register, and the command decoder by bus control module is electric
The instruction of the defined operation otp memory of road parsing, the effective instruction that will parse ground concrete operations otp memory passes through
MUX circuit is sent to OTP timing sequencers.When upper electric reading circuit realizes upper electricity, to otp memory regional, i.e. Fig. 1 institutes
The otp memory distributed intelligence shown is read out；Read operation order is passed through MUX by upper electric reading circuit（MUX）Electricity
Road is sent to OTP timing sequencers, produces and reads sequential, realizes the reading to otp memory regional；Command decoder electricity
After the access otp memory instruction parsing that road is configured to CPU or board, the effective otp memory that accesses is produced to instruct to OTP
Timing sequencer, the specific sequential for realizing configured instruction by timing sequencer is generated, complete according to the instruction sequencing for being configured
The access of paired otp memory.Programmed algorithm modular circuit shown in Fig. 3, for otp memory programming key instruction or OTP
When memory program information command is to otp memory programming operation, using algorithm of the invention, algorithm circuit realiration is in programming
When otp memory is operated, the address to be programmed to otp memory carries out redundancy treatment and takes the programming of each data to apply
Plus 16 treatment of programming pulse voltage can be allowed, the modular circuit is realized by full-digital circuit, adoption status machine control realization
Programmed algorithm.When being read out to otp memory key information, the present invention is directed to the particular/special requirement of key information, strict right
Key information is maintained secrecy, it is ensured that chip secure, takes scrambling circuit to carry out at scrambling the data read from otp memory
Reason so that key data seen by user is not the data for being really programmed to otp memory, so as to be carried out safely to key information
Protection.
A kind of method for accessing otp memory, including：
1）According to the concrete operations to be accessed otp memory, grasped using cpu model or board pattern definition series of instructions
Make otp memory；For programming key information, in order to ensure the strict safety of key information, the instruction of configuration programming key is only
Can be carried out using board pattern.The configuration of remaining instruction can use cpu model（That is normal mode of operation）Or board pattern.
The series of instructions of the access otp memory that can be configured includes：Otp memory sleep pattern, otp memory wake up mould
Formula, reset otp memory, otp memory programming information, otp memory programming key, reading otp memory and OTP storages
Device self test mode.
2）Upper electricity reads OTP regional information, electric reading circuit is gone up as shown in Figure 1 and is completed, thereon electric reading circuit behaviour
Make flow chart as shown in fig. 7, comprises OTP pattern informations, OTP interfaces closing information, OTP system realms closing information, OTP user
Region close information and key field information, wherein, read key field information for did scrambling after information, it is ensured that key
The security of information.
Referring to Fig. 3, first using the instruction of CPU or board defining operation otp memory, read by upper electric reading circuit
Otp memory regional information, otp memory regional information is referring to Fig. 1.
Referring to Fig. 4, realize reading electricity on otp memory, including：Chip electrification reset, it is upper electricity wake up otp memory,
Electrification reset otp memory, reading otp memory pattern information, reading otp memory interface message, reading otp memory system
System area information, reading user area information, reading key field information, into OTP sleep patterns, upper electricity reads OTP storages
Device regional terminates.
3）The instruction of the defined operation otp memory of parsing, OTP sequential is accessed according to the order-driven for parsing；Adopt
The specific instruction that CPU or board are configured is sent to command decoder circuit with command decoder, Instruction decoding includes：Definition
Whether the specific instruction of OTP is accessed well, waits OTP to be visited to instruct, check OTP instructions, judge to access OTP instructions effectively to refer to
Order, OTP timing sequencers are then sent to if effective instruction, produce the sequential of corresponding instruction, complete to visit otp memory
Ask；If illegal command does not continue executing with below step then, terminate accessing otp memory.So-called illegal command includes：In programming
The instruction of OTP programming informations is sent during key information, the instruction of configuration programming key, matches somebody with somebody under cpu model in the normal mode of operation
The instruction of OTP self test modes is put, self test mode instruction equally can only also be directed to board pattern.
It is otp memory command decoder analysis instruction method according to an embodiment of the invention referring to Fig. 5, parsing
The instruction of defined operation otp memory includes：
Definition accesses the specific instruction of otp memory；
Instructed etc. otp memory to be visited；
Check otp memory instruction；And
Judge to access whether otp memory instruction is effective instruction, OTP timing sequencers be then sent to if effective instruction,
Otp memory operational order is performed, the access of otp memory is then terminated if illegal command.
4）Into board mode of operation, otp memory programming key instruction is sent, parsing programs key instruction, and by OTP
Timing sequencer produces the corresponding access otp memory interface sequence of the instruction, and key data is programmed in otp memory.
Key information because it has particularity, it is necessary to ensure the safety of its information, therefore when key information is programmed, it is necessary to use machine
Platform mode of operation completes key information and is programmed to otp memory corresponding region；Key information is read, to the key letter for reading out
Breath carries out scrambling treatment, prevents from being really programmed to the information leakage of otp memory part, the security of strict guarantee key.
5）It is the otp memory storage and distribution figure of the embodiment of the present invention referring to Fig. 1 into normal mode of operation, therefore needs
Now, the instruction of OTP programming informations is sent to OTP relevant ranges programming information, program chip serial number, OTP timing sequencers
Programming otp memory sequential is produced, chip serial number is programmed to corresponding region in otp memory.
6）In the normal mode of operation, the instruction of otp memory programming information is sent, instruction is translated by command decoder
Code, and programming otp memory sequential is produced by OTP timing sequencers, otp memory part is delivered to, complete DLL closing letter
Breath, programing system area information.
It is error-prone when to otp memory programming data in order to solve the problems, such as, the reliability of otp memory is increased,
To otp memory programming key instruction or the operation of otp memory programming information instruction, processed using address redundancy of the invention
And the data of same address are allowed up to 16 applyings of programming pulse voltage.
It is at the otp memory programming of one embodiment of the invention, the address distribution of read operation and redundancy referring to Fig. 6
Reason figure.First, programming operation carries out fault-tolerant processing to the address of otp memory, i.e., often program 4 OTP of a data correspondence and deposit
The physical address of reservoir, and each is programmed to 4 physical address successively, when being wherein all programmed to no less than 3 bit address
Just it is believed that this data for being configured are programmed successfully during work(, otherwise it is assumed that this data program fail.Shown in Fig. 6, the present invention
The address that otp memory is accessed in embodiment is made up of 13 bit address, including system address, logic bit address and physically
Location.System address and logic bit address are to choose a specific region of otp memory.For program address, one logically
Location maps 4 redundancies of physical address, and once to 4 for each of address is programmed, when being wherein no less than 3 bit address all
Program when successfully just it is believed that this data for being configured are programmed successfully, otherwise it is assumed that this data program fail.
Wherein, each data program operation in described 4 physical address to otp memory includes, referring to Fig. 7, bag
Include：
Open otp memory programmed algorithm；
The configuration address to be programmed, program address is equal to the initial programming address for providing；
Apply 3 programming pulse voltages in the initial programming address location for providing, and remember N（Represent record programming pulse number of times）Deng
In 0 time；
Apply to continue to 1 programming pulse voltage on the basis of 3 programming pulse voltages；
Programming verification operation；
Whether the data that the data judging obtained by programming verification operation is programmed are 1（Otp memory programming data is " 1 ", not
The data of programming are " 0 "）If programming data is " 1 ", then it represents that this programming operation success to the address, continue according to this
Method performs the programming operation of next address.If programming data is " 0 ", next step is performed；
Determine whether to have added 16 programming pulse voltages in the position, judge that number of times is counted by N.If being deposited in the specified OTP
Memory address position is not up to added 16 program voltages, then continue to pulse voltage, and N now adds one；Often apply an arteries and veins
Rush voltage（I.e. N often increases by one）It is programmed whether data are the judgement of " 1 ", then judges whether programming pulse voltage is programmed to 16
Secondary cycle criterion, in 16 programming pulse operations etc verification of programming data success, then the address date is programmed successfully；If
The position has added 16 program voltages or data are " 0 ", then program fail.
According to above-mentioned programmed method, in the normal mode of operation, otp memory interface closing information, system realm are completed
The program storage operation of information, realizes the access to otp memory.
Finally it should be noted that：The above embodiments are merely illustrative of the technical solutions of the present invention rather than is limited,
Although being described in detail to the present invention with reference to preferred embodiment, it will be understood by those within the art that：Its according to
Technical scheme can so be modified or equivalent, and these modifications or equivalent can not also make to repair
Technical scheme after changing departs from the spirit and scope of technical solution of the present invention.
Claims (10)
1. it is a kind of access otp memory method, including：
Step 1：Defining series of instructions is used to operate otp memory；
Step 2：Upper electricity reads otp memory regional information, including otp memory pattern information, otp memory interface envelope
Close information, otp memory system realm closing information, the closing of otp memory user area information and key field information；
Step 3：The instruction of the defined operation otp memory of parsing, when accessing otp memory according to the order-driven for parsing
Sequence；
Step 4：Into board mode of operation, otp memory programming key instruction is sent, parsing programs key instruction, and by OTP
Timing sequencer produces the corresponding access otp memory interface sequence of the instruction, and key data is programmed in otp memory,
Key information is read, the key information to reading out carries out scrambling treatment；
Step 5：Into normal mode of operation, the instruction of otp memory programming information is sent, program chip serial number, OTP sequential hair
Raw device produces programming otp memory sequential, and chip serial number is programmed into corresponding region in otp memory；
Step 6：The instruction of otp memory programming information is sent, by command decoder to Instruction decoding, and is occurred by OTP sequential
Device produces programming otp memory sequential, is sent to otp memory part, completes DLL closing information and programing system region
Information.
2. the method for accessing otp memory as claimed in claim 1, it is characterised in that the series of instructions includes：OTP
Memory sleep pattern, otp memory awakening mode, reset otp memory, otp memory programming information, otp memory are compiled
Journey key, reading otp memory and otp memory self test mode.
3. the method for accessing otp memory as claimed in claim 1, it is characterised in that the defined operation OTP of the parsing
The instruction of memory includes：
Definition accesses the specific instruction of otp memory；
Instructed etc. otp memory to be visited；
Check otp memory instruction；And
Judge to access whether otp memory instruction is effective instruction, OTP timing sequencers are then sent to if effective instruction.
4. the method that otp memory is accessed such as claim 3, it is characterised in that described judgement accesses otp memory instruction is
The no access for being effective instruction, otp memory then being terminated if illegal command.
5. the method for accessing otp memory as claimed in claim 1, it is characterised in that the OTP timing sequencers, is used for
The specific sequential of effective access otp memory instruction that generation is parsed.
6. the method for accessing otp memory as claimed in claim 1, it is characterised in that the otp memory programming key refers to
Order or the instruction of otp memory programming information, are taken using the redundancy treatment to otp memory program address and in programming operation
The method for implementing n times pulse program to the programming operation of same address, wherein N is less than or equal to 16.
7. the method for accessing otp memory as claimed in claim 6, it is characterised in that the step 4 or step 5 are also wrapped
Including carries out redundancy treatment to the distribution of the address of otp memory programming operation, and the redundancy treatment includes：
When carrying out a data programming operation to otp memory, this data are mapped to 4 physical address of otp memory simultaneously
Program successively, if wherein being programmed successfully no less than 3 bit address, then it is assumed that a data for being configured is programmed successfully, otherwise it is assumed that
This data are not programmed successfully.
8. the method for accessing otp memory as claimed in claim 7, it is characterised in that described to 4 physics of otp memory
Each data program operation in address includes：
The configuration address to be programmed, program address is equal to the initial programming address for providing；
Apply 3 programming pulse voltages in initial programming address location；
Apply to continue to 1 programming pulse voltage on the basis of 3 programming pulse voltages；
Programming verification operation；
Whether the data that the data judging obtained by programming verification operation is programmed are 1, wherein, the data of otp memory programming
It is " 1 " that unprogrammed data are " 0 ", if programming data is " 1 ", then it represents that this programming operation success to the address, continues
The programming operation of next address is performed in the method, if programming data is " 0 ", performs next step；
Determine whether to have added 16 programming pulse voltages in the position, if being not up in the specified otp memory address location
Added 16 program voltages, then continue to pulse voltage, often applies pulsatile once voltage and is programmed whether data are " 1 "
Judge, then judge whether programming pulse voltage is programmed to the cycle criterion of 16 times；If having added 16 program voltages also in the position
Be data be " 0 ", then program fail.
9. the method for accessing otp memory as claimed in claim 1, it is characterised in that the otp memory includes：Chip
Serial number area, for storage chip sequence number；Interface closed area, for storing relevant interface closing information；Otp memory
Mode of operation：Operator scheme for storing otp memory, including board mode of operation and normal mode of operation；System lock
Control area, the control information for storing closed system region；User closes control area, the control for storing user area
Information processed；System key region, for storing key information region；And user area, for storing user's letter to be stored
Breath.
10. the device of a kind of OTP storage devices, including otp memory and access otp memory, wherein, the otp memory
Including：Chip serial number region, for storage chip sequence number；Interface closed area, for storing relevant interface closing information；
Otp memory mode of operation：Operator scheme for storing otp memory, including board mode of operation and normal mode of operation；
System lock control area, the control information for storing closed system region；User closes control area, for storing user
The control information in region；System key region, for storing key information region；And user area, wanted for storing user
The information of storage.
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Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108170607A (en) * | 2018-01-03 | 2018-06-15 | 上海传英信息技术有限公司 | The control device and control method of OTP switches |
| CN109286546A (en) * | 2018-11-20 | 2019-01-29 | 成都信息工程大学 | A kind of multiple spot access type intelligent interconnection equipment and interconnected communication method |
| CN110275845A (en) * | 2019-06-29 | 2019-09-24 | 江苏芯盛智能科技有限公司 | Memory control methods, device and electronic equipment |
| CN112286468A (en) * | 2020-12-28 | 2021-01-29 | 湖北芯擎科技有限公司 | Access control method and device of storage device and electronic equipment |
| CN112306559A (en) * | 2019-07-26 | 2021-02-02 | 珠海零边界集成电路有限公司 | Storage starting system and method |
| CN113312224A (en) * | 2021-06-08 | 2021-08-27 | 合肥磐芯电子有限公司 | MCU for testing OTP type and testing method thereof |
| CN114489516A (en) * | 2022-02-08 | 2022-05-13 | 合肥芯颖科技有限公司 | Data storage device and method |
Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050105331A1 (en) * | 2003-11-13 | 2005-05-19 | Lee Chul-Ho | Memory system having flash memory where a one-time programmable block is included |
| US20100202183A1 (en) * | 2009-02-06 | 2010-08-12 | Sidense Corp. | High reliability otp memory |
| US20110107010A1 (en) * | 2009-10-29 | 2011-05-05 | Freescale Semiconductor, Inc. | One-time programmable memory device and methods thereof |
| CN102360316A (en) * | 2011-10-20 | 2012-02-22 | 深圳芯邦科技股份有限公司 | Method and device for operating startup procedure in one-time programmable storage |
| CN102364430A (en) * | 2010-09-17 | 2012-02-29 | 杭州士兰微电子股份有限公司 | Microcontroller for supporting multi-programming on one time programmable memory and programming method |
| US20130235644A1 (en) * | 2012-03-11 | 2013-09-12 | Shine C. Chung | System and method of in-system repairs or configurations for memories |
| US20160276043A1 (en) * | 2015-03-22 | 2016-09-22 | Shine C. Chung | Intergrated OTP Memory for Providing MTP Memory |
| US20170040067A1 (en) * | 2015-08-03 | 2017-02-09 | Samsung Electronics Co., Ltd. | Method of programming one-time programmable (otp) memory device and method of testing semiconductor integrated circuit including the same |
-
2017
- 2017-03-16 CN CN201710156206.7A patent/CN106875974B/en active Active
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050105331A1 (en) * | 2003-11-13 | 2005-05-19 | Lee Chul-Ho | Memory system having flash memory where a one-time programmable block is included |
| US20100202183A1 (en) * | 2009-02-06 | 2010-08-12 | Sidense Corp. | High reliability otp memory |
| US20110107010A1 (en) * | 2009-10-29 | 2011-05-05 | Freescale Semiconductor, Inc. | One-time programmable memory device and methods thereof |
| CN102364430A (en) * | 2010-09-17 | 2012-02-29 | 杭州士兰微电子股份有限公司 | Microcontroller for supporting multi-programming on one time programmable memory and programming method |
| CN102360316A (en) * | 2011-10-20 | 2012-02-22 | 深圳芯邦科技股份有限公司 | Method and device for operating startup procedure in one-time programmable storage |
| US20130235644A1 (en) * | 2012-03-11 | 2013-09-12 | Shine C. Chung | System and method of in-system repairs or configurations for memories |
| US20160276043A1 (en) * | 2015-03-22 | 2016-09-22 | Shine C. Chung | Intergrated OTP Memory for Providing MTP Memory |
| US20170040067A1 (en) * | 2015-08-03 | 2017-02-09 | Samsung Electronics Co., Ltd. | Method of programming one-time programmable (otp) memory device and method of testing semiconductor integrated circuit including the same |
Non-Patent Citations (2)
| Title |
|---|
| XIAN LI等: ""Reliable Antifuse One-Time-Programmable Scheme With Charge Pump for Postpackage Repair of DRAM"", 《IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS》, vol. 23, no. 9, pages 1956 - 1960, XP011667173, DOI: 10.1109/TVLSI.2014.2354836 * |
| 何亚璠: ""大容量OTP存储器的设计与研究"", 中国优秀硕士学位论文全文数据库•信息科技辑》, vol. 2016, no. 3, pages 1 - 68 * |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108170607A (en) * | 2018-01-03 | 2018-06-15 | 上海传英信息技术有限公司 | The control device and control method of OTP switches |
| CN108170607B (en) * | 2018-01-03 | 2021-05-18 | 上海传英信息技术有限公司 | Control device and control method of OTP switch |
| CN109286546A (en) * | 2018-11-20 | 2019-01-29 | 成都信息工程大学 | A kind of multiple spot access type intelligent interconnection equipment and interconnected communication method |
| CN109286546B (en) * | 2018-11-20 | 2023-08-29 | 深圳市卓越信息技术有限公司 | Multi-point access type intelligent interconnection equipment and interconnection communication method |
| CN110275845A (en) * | 2019-06-29 | 2019-09-24 | 江苏芯盛智能科技有限公司 | Memory control methods, device and electronic equipment |
| CN112306559A (en) * | 2019-07-26 | 2021-02-02 | 珠海零边界集成电路有限公司 | Storage starting system and method |
| CN112286468A (en) * | 2020-12-28 | 2021-01-29 | 湖北芯擎科技有限公司 | Access control method and device of storage device and electronic equipment |
| CN113312224A (en) * | 2021-06-08 | 2021-08-27 | 合肥磐芯电子有限公司 | MCU for testing OTP type and testing method thereof |
| CN114489516A (en) * | 2022-02-08 | 2022-05-13 | 合肥芯颖科技有限公司 | Data storage device and method |
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