CN112306559A - Storage starting system and method - Google Patents
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- CN112306559A CN112306559A CN201910682233.7A CN201910682233A CN112306559A CN 112306559 A CN112306559 A CN 112306559A CN 201910682233 A CN201910682233 A CN 201910682233A CN 112306559 A CN112306559 A CN 112306559A
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- 230000007958 sleep Effects 0.000 claims description 67
- 230000006266 hibernation Effects 0.000 claims description 5
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- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/44—Arrangements for executing specific programs
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Abstract
The invention provides a storage startup system and a method, wherein a microcontroller in the storage startup system is awakened when receiving an awakening command sent by external equipment, and sends an information reading command to a storage controller after being awakened, the storage controller is awakened when receiving the awakening command sent by the external equipment, awakens a memory according to the received information reading command, reads startup information in the memory and sends the startup information to the microcontroller after the memory is awakened, the microcontroller completes self startup based on the startup information and starts the memory and the storage controller based on the startup information to enable the storage startup system to enter a working state, thereby solving the problem that the microcontroller cannot acquire the startup information in the memory in the non-awakened state after the memory enters the non-awakened state, so that the storage startup system cannot enter the working state from the non-awakened state, the storage startup system is smoothly switched from the un-awakening state to the working state.
Description
Technical Field
The invention relates to the field of computer application, in particular to a storage starting system and a storage starting method.
Background
Because the BOOT code necessary for starting the storage starting system is stored in the memory, when the modules such as the microcontroller, the storage controller and the like enter an un-awakened state with low power consumption, the memory is still in a working state with normal power consumption, so that when the microcontroller and the storage controller are awakened by external equipment, the microcontroller starts the microcontroller according to the BOOT code stored in the memory read by the storage controller, thereby starting the storage starting system. Although the memory itself may enter the non-wake-up state with low power consumption to save power consumption, in the present situation, if the microcontroller configures the memory into the non-wake-up state through the memory controller before entering the low power consumption, after the microcontroller and the memory controller are woken up from the non-wake-up state, because the memory is still in the non-wake-up state, the microcontroller cannot read the BOOT code stored in the memory and necessary for booting the system through the memory controller, thereby causing the memory booting system to hang up. Therefore, there are problems that: after the memory enters the non-awakening state, the microcontroller cannot acquire the starting information in the memory in the non-awakening state, so that the storage starting system cannot enter the working state from the non-awakening state.
Disclosure of Invention
The invention provides a storage starting system and a storage starting method, which solve the problem that after a memory enters an un-awakened state in the prior art, a microcontroller cannot acquire starting information in the memory in the un-awakened state, so that the storage starting system cannot enter a working state from the un-awakened state.
In order to achieve the above purpose, the embodiment of the invention adopts the following technical scheme:
a storage boot system comprises a memory, a microcontroller and a storage controller;
the memory is used for storing starting information;
the microcontroller is used for being awakened under an awakening command input by external equipment and sending an information reading command to the storage controller after being awakened;
the memory controller is used for being awakened under the awakening command input by external equipment, receiving the information reading command sent by the microcontroller after being awakened, awakening the memory according to the information reading command, reading the starting information stored in the memory after the memory is awakened, and sending the starting information to the microcontroller;
the microcontroller is also used for finishing self starting based on the starting information and starting the memory and the memory controller based on the starting information.
In a preferred option of the embodiment of the present invention, in the storage booting system, the storage controller includes a pre-wake-up module, the pre-wake-up module is electrically connected to the memory, and the pre-wake-up module is configured to send a level signal to the memory when the memory is in an un-wake-up state and the storage controller fails to read the booting information stored in the memory, so that the memory is woken up based on the level signal.
In a preferred option of the embodiment of the present invention, in the memory boot system, the memory controller is an OTP microcontroller, and the memory is an OTP memory.
A storage boot method is applied to the storage boot system, and when the storage boot system is in an un-awakened state, the following steps are executed:
the storage controller of the storage boot system and the microcontroller of the storage boot system are awakened under an awakening command input by external equipment respectively;
after being awakened, the microcontroller sends an information reading command to the storage controller;
the storage controller receives the information reading command after being awakened, awakens a memory of the storage starting system according to the information reading command, reads starting information stored in the memory and sends the starting information to the microcontroller after the memory is awakened;
and the microcontroller completes self starting based on the starting information and starts the memory and the memory controller based on the starting information so as to enable the memory starting system to enter a working state.
In a preferred option of the embodiment of the present invention, in the storage booting method, the non-awake state includes a sleep state.
In a preferred option of the embodiment of the present invention, in the storage boot method, before the step of executing the wake-up command input by the external device to wake up the storage controller and the microcontroller, the method further includes:
when the microcontroller and the storage controller in the working state receive a sleep command sent by an external device, the microcontroller controls the storage controller to configure the memory according to the sleep command so as to enable the memory to enter the sleep state, and after the memory enters the sleep state, the storage controller and the microcontroller enter the sleep state, so that the storage starting system enters the sleep state.
In a preferred option of the embodiment of the present invention, in the storage boot method, power consumption of the storage boot system in the hibernation state is lower than power consumption of the storage boot system in the operating state.
In a preferred option of the embodiment of the present invention, in the above storage booting method, the waking up the memory by the storage controller according to the information reading command includes:
the memory controller executes the information reading command, reads the starting information stored in the memory in the dormant state, and changes the bus signal of the memory starting system from high level to low level when reading fails, so as to trigger a pre-awakening module in the memory controller, so that the pre-awakening module sends a level signal to the memory to awaken the memory, and the memory controller changes the bus signal of the memory starting system from low level to high level after the memory is awakened.
In a preferred option of the embodiment of the present invention, in the memory boot method, when the memory controller changes a bus signal of the memory boot system from a high level to a low level, the memory is in a read/write invalid state.
In a preferred option of the embodiment of the present invention, in the memory boot method, when the memory controller changes a bus signal of the memory boot system from a low level to a high level, the memory is in a read/write operation active state.
In a preferred option of the embodiment of the present invention, in the storage BOOT method, the BOOT information in the memory includes a BOOT code, where the BOOT code is a code that is run when the storage BOOT system enters the operating state from the sleep state.
The invention provides a storage startup system and a method, a microcontroller in the storage startup system is awakened when receiving an awakening command sent by external equipment, and sends an information reading command to a storage controller after being awakened, the storage controller is awakened when receiving the awakening command sent by the external equipment, and awakens a memory according to the received information reading command, after the memory is awakened, the microcontroller completes self startup based on read startup information in the memory, and starts the memory and the storage controller based on the startup information to enable the storage startup system to enter a working state, thereby solving the problem that the microcontroller cannot acquire startup information in the memory in an un-awakened state after the memory enters the un-awakened state, so that the storage startup system cannot enter the working state from the un-awakened state, the storage startup system is smoothly switched from the un-awakening state to the working state.
Drawings
The scope of the present disclosure will be better understood from the following detailed description of exemplary embodiments, which is to be read in connection with the accompanying drawings. Wherein the included drawings are:
fig. 1 is a connection block diagram of a storage boot system according to an embodiment of the present invention.
Fig. 2 is a schematic flowchart of a storage booting method according to an embodiment of the present invention.
Fig. 3 is a timing diagram of a sleep wake-up logic of a storage boot system according to an embodiment of the present invention.
Icon: 100-storage boot system; 120-a memory; 140-a microcontroller; 160-a memory controller; 162-pre-wake-up module.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments.
Thus, the following detailed description of the embodiments of the present invention, presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures. In the description of the present invention, the terms "first", "second", and the like are used only for distinguishing the description, and are not intended to be construed as only or implying relative importance.
Referring to fig. 1, an embodiment of the present invention provides a memory booting system 100, which includes a memory 120, a microcontroller 140, and a memory controller 160.
The memory 120 is used for storing startup information; the microcontroller 140 is configured to wake up under a wake-up command input by an external device, and send an information read command to the memory controller 160 after being woken up; the memory controller 160 is configured to be woken up by the wake-up command input by an external device, receive the information reading command sent by the microcontroller 140 after being woken up, wake up the memory 120 according to the information reading command, and read the start-up information stored in the memory 120 and send the start-up information to the microcontroller 140 after the memory 120 is woken up; the microcontroller 140 is further configured to complete self-boot based on the boot information, and boot the memory 120 and the memory controller 160 based on the boot information.
It is understood that the microcontroller 140 is electrically connected to the memory controller 160, and the memory controller 160 is electrically connected to the memory 120.
It is understood that the memory 120 includes random access memory and read only memory; the microcontroller 140 includes an MCU; the memory controller 160 is a device that necessarily controls the access of the memory 120 according to a certain timing rule, and the memory controller 160 converts a command issued by the microcontroller 140 into a signal that can be recognized by the memory 120, and performs address decoding and data format conversion between the microcontroller 140 and the memory 120.
It can be understood that the BOOT information stored in the memory 120 is information that must be read and run from power-on to a smooth entry into an operating state of the storage BOOT system 100, and in this embodiment, the BOOT information includes, but is not limited to, a version number, a system type, a system directory, a BIOS version of the storage BOOT system 100, and a BOOT code stored in the memory 120.
Specifically, in this embodiment, the external device is an input device that can send a command to the storage booting system 100, and includes but is not limited to a keyboard, a mouse, a pen input device, a scanner, a digital camera, and a digital video camera, and the external device can send the command to the storage booting system 100 by a manner that includes but is not limited to voice, image, key, and network remote.
In this embodiment, the memory controller 160 includes a pre-wake-up module 162, the pre-wake-up module 162 is electrically connected to the memory 120, and the pre-wake-up module 162 is configured to send a level signal to the memory 120 when the memory is in an un-wake-up state and the memory controller 160 fails to read the boot information stored in the memory 120, so that the memory 120 is woken up based on the level signal.
In this embodiment, the memory controller 160 is an OTP microcontroller, and the memory 120 is an OTP memory.
In particular, the OTP microcontroller is used to control the OTP memory, which is a special memory, and the OTP memory only supports one-time programming, and cannot be changed and cleared again once the programming is successful, and normally, the OTP memory is already programmed in production, so that the OTP microcontroller can only perform a read operation on the OTP memory during use.
With reference to fig. 2, an embodiment of the present invention further provides a storage booting method, which is applied to the storage booting system 100, and the storage booting method includes steps S110 to S140.
In step S110, the memory controller 160 and the microcontroller 140 are respectively awakened by an awakening command input by an external device.
It is understood that before step S110 is executed, the storage booting system 100 should be in an un-awake state, wherein the un-awake state includes any one of a sleep state, a standby state or a sleep state.
It is understood that the power consumption of the storage booting system 100 in the hibernation state is lower than the power consumption of the storage booting system 100 in the operation state.
It is understood that the power consumption of the storage booting system 100 in the hibernation state is lower than the power consumption of the storage booting system 100 in the sleep state; the power consumption of the storage booting system 100 in the sleep state is lower than the power consumption of the storage booting system 100 in the standby state; the power consumption of the storage booting system 100 in the standby state is lower than the power consumption of the storage booting system 100 in the operating state.
Optionally, in this embodiment, the non-awake state is the sleep state.
Before step S110 is executed, the storage booting method according to the embodiment of the present invention further includes that when the microcontroller 140 and the storage controller 160 in the working state receive a sleep command sent by an external device, the microcontroller 140 controls the storage controller 160 to configure the storage 120 according to the sleep command, so that the storage 120 enters a sleep state, and after the storage 120 enters the sleep state, the storage controller 160 and the microcontroller 140 enter the sleep state, so that the storage booting system 100 enters the sleep state.
It is understood that the storage booting system 100 may be in any one of the operating state, the sleep state and the standby state before entering the hibernation state.
It is understood that the configuration mode of the microcontroller 140 controlling the memory controller 160 to configure the memory 120 according to the sleep command includes a software configuration mode. The microcontroller 140 controlling the memory controller 160 to perform the software configuration on the memory 120 according to the sleep command comprises: the microcontroller 140 sends a sleep configuration command to the memory controller 160 according to the sleep command, the memory controller 160 receives the sleep configuration command and analyzes the sleep configuration command to obtain sleep configuration parameters, and configures the memory 120 according to the sleep configuration parameters, and the configured memory 120 enters the sleep state.
In step S120, the microcontroller 140 sends an information reading command to the memory controller 160 after being awakened.
It is understood that, after being woken up, the microcontroller 140 needs to read the boot information stored in the memory 120 through the memory controller 160 and boot the memory boot system 100 based on the boot information, and therefore, the microcontroller 140 needs to send an information read command to the memory controller 160 to read the boot information.
In step S130, the memory controller 160 receives the information reading command after being awakened, wakes up the memory 120 according to the information reading command, and reads the start information in the memory 120 and sends the start information to the microcontroller 140 after the memory 120 is awakened.
In this embodiment, the waking up the memory 120 by the memory controller 160 according to the information reading command includes: the memory controller 160 executes the information reading command, reads the boot information in the memory 120 in the sleep state, and changes the bus signal of the memory boot system 100 from a high level to a low level when the reading fails, so as to trigger the pre-wake-up module 162 in the memory controller 160, so that the pre-wake-up module 162 sends a level signal to the memory 120 to wake up the memory 120, and after the memory 120 is woken up, the memory controller 160 changes the bus signal of the memory boot system 100 from the low level to the high level.
In this embodiment, when the memory controller 160 changes the bus signal of the memory booting system 100 from high level to low level, the memory 120 is in an invalid state for read and write operations.
In this embodiment, when the memory controller 160 changes the bus signal of the memory booting system 100 from low level to high level, the memory 120 is in a valid state for read and write operations.
Specifically, when the memory 120 is an OTP memory and the memory controller 160 is an OTP microcontroller, the OTP microcontroller can only read the OTP memory, when the OTP microcontroller is woken up to receive the information reading command, the reading fails when the reading operation is performed on the start information in the OTP memory in the sleep state according to the information reading command, and when the reading fails, the OTP microcontroller changes the bus signal of the memory start-up system 100 from a high level to a low level, and at this time, the OTP memory is in an invalid read operation state, and at the same time, the change of the bus signal triggers the pre-wake-up module 162 in the OTP microcontroller to send a level signal to the OTP memory to wake up the OTP memory, and when the memory is woken up, the OTP microcontroller changes the bus signal of the memory start-up system 100 from a low level to a high level, at this time, the OTP memory is switched from the invalid state to the valid state, and the OTP microcontroller reads the start information in the OTP memory and sends the start information to the microcontroller 140.
In step S140, the microcontroller 140 completes self-boot based on the boot information, and boots the memory 120 and the memory controller 160 based on the boot information, so that the memory boot system 100 enters the operating state.
In this embodiment, the BOOT information in the memory 120 includes a BOOT code, where the BOOT code is a code that is executed when the storage BOOT system 100 enters the operating state from the sleep state.
Specifically, the startup information in the memory 120 further includes calibration parameters of the power supply or the clock, the number of the microcontroller 140, and the software code version information.
It can be understood that the BOOT code is a code having a system BOOT function, a power-on self-test function, a device driver, and the like, and the microcontroller 140 may support the storage BOOT system 100 to perform operations such as root file system loading, NFS mount, and image file check during BOOT by running the BOOT code, so as to ensure normal BOOT of the memory 120, the microcontroller 140, and the storage controller 160, and thus the storage BOOT system 100 smoothly enters the operating state after normal BOOT.
Referring to fig. 3, the present invention describes the sleep and wake-up of the microcontroller 140, the memory controller 160, and the memory 120 in the memory booting system 100, and the bus signals related to the readable and writable states of the memory 120.
In fig. 3, when the level signals of the control pins of the microcontroller 140 and the memory controller 160 are at a high level, it indicates that the microcontroller 140 and the memory controller 160 are in a non-sleep state, and when the level signals of the control pins of the microcontroller 140 and the memory controller 160 are at a low level, it indicates that the microcontroller 140 and the memory controller 160 are in the sleep state or the power-off state.
When the level signal of the control pin of the memory 120 is at a high level, it indicates that the memory 120 is in the sleep state, and when the level signal of the control pin of the memory 120 is at a low level, it indicates that the memory 120 is in the non-sleep state.
In this embodiment, the non-sleep state may be any one of the operating state, the standby state, and the sleep state.
The bus signal is a bus signal of the memory boot system 100, and when the bus signal is at a high level, it indicates that the read/write operation performed by the memory controller 160 on the memory 120 is valid, and when the bus signal is at a low level, it indicates that the read/write operation performed by the memory controller 160 on the memory 120 is invalid.
In fig. 3, when the level signals of the control pins of the microcontroller 140 and the memory controller 160 are at a high level, it indicates that the microcontroller 140 and the memory controller 160 are in a non-sleep state, and when the level signals of the control pins of the microcontroller 140 and the memory controller 160 are at a low level, it indicates that the microcontroller 140 and the memory controller 160 are in a sleep state or a power-off state.
When the level signal of the control pin of the memory 120 is at a high level, it indicates that the memory 120 is in the sleep state, and when the level signal of the control pin of the memory 120 is at a low level, it indicates that the memory 120 is in the non-sleep state.
In this embodiment, the non-sleep state may be any one of the operating state, the standby state, and the sleep state.
The bus signal is a bus signal of the memory boot system 100, and when the bus signal is at a high level, it indicates that the read/write operation performed by the memory controller 160 on the memory 120 is valid, and when the bus signal is at a low level, it indicates that the read/write operation performed by the memory controller 160 on the memory 120 is invalid.
Specifically, referring to fig. 3, the storage boot system 100 is powered on and booted at a point a, and the microcontroller 140 and the storage controller 160 are switched from the power-off state to the working state, that is, the microcontroller 140 and the storage controller 160 are switched from the power-off state to the non-sleep state, where the level signals of the control pins of the microcontroller 140 and the storage controller 160 are changed from the low level to the high level.
When the storage boot system 100 in the working state receives a sleep command sent by an external device at point B, the microcontroller 140 controls the storage controller 160 to configure the storage 120 according to the sleep command, so that the storage 120 enters a sleep state, at this time, a level signal of a control pin of the storage 120 changes from a low level to a high level, and at this time, the microcontroller 140 and the storage controller 160 do not yet enter the sleep state, so that the level signals of the control pins of the microcontroller 140 and the storage controller 160 are still at the high level.
At point C, the microcontroller 140 and the memory controller 160 enter a sleep state and power down, and the level signals of the control pins of the microcontroller 140 and the memory controller 160 change from high level to low level, at which time the memory booting system 100 enters the sleep state.
After the microcontroller 140 and the memory controller 160 are woken up by the wake-up command sent by the external device at point D1, the microcontroller 140 and the memory controller 160 enter the working state from the sleep state, and the level signals of the control pins of the microcontroller 140 and the memory controller 160 change from low level to high level.
At point D2, the memory controller 160 executes the information read command, and since the memory 120 is in the sleep state at this time, the read/write operation on the memory 120 is invalid, the memory controller 160 reads the startup information in the memory 120 in the sleep state, and when the read fails, changes the bus signal from high level to low level, and the bus signal changed to low level triggers the pre-wake-up module 162 in the memory controller 160 to wake up the memory 120.
At point E, the pre-wake-up module 162 completes waking up the memory 120, the memory 120 enters the working state from the sleep state, and the level signal of the control pin of the memory 120 changes from high level to low level.
At point F, the memory 120 enters the operating state from the sleep state, and the memory controller 160 changes the bus signal from the low level to the high level, so that the memory controller 160 can successfully read the boot information stored in the memory 120, and the microcontroller 140 can boot the memory 120, the microcontroller 140, and the memory controller 160 according to the boot information, so as to enable the memory boot system 100 to enter the operating state.
In summary, according to the storage boot system 100 and the method provided by the present invention, after the microcontroller 140 in the storage boot system 100 receives a wake-up command sent by an external device, is woken up, and sends an information reading command to the storage controller 160 after being woken up, the storage controller 160 is woken up when receiving the wake-up command sent by the external device, wakes up the memory 120 according to the received information reading command, and after the memory 120 is woken up, reads the boot information in the memory 120 and sends the boot information to the microcontroller 140, the microcontroller 140 completes its boot based on the boot information, and starts the memory 120 and the storage controller 160 based on the boot information to enable the storage boot system 100 to enter the working state, thereby solving the problem that after the memory 120 enters the non-wake-up state, the microcontroller 140 cannot acquire the startup information in the memory 120 in the non-awakened state, which results in a problem that the storage startup system 100 cannot enter the working state from the non-awakened state, thereby realizing smooth switching of the storage startup system 100 from the non-awakened state to the working state. Further, in the present invention, the microcontroller 140, the memory controller 160, and the memory 120 of the memory booting system 100 may all enter a sleep state, so as to reduce system power consumption and achieve the purpose of saving power consumption.
Although the embodiments of the present invention have been described above, the above descriptions are only for the convenience of understanding the present invention, and are not intended to limit the present invention. It will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention as defined by the appended claims.
Claims (11)
1. A storage starting system is characterized by comprising a storage, a microcontroller and a storage controller;
the memory is used for storing starting information;
the microcontroller is used for being awakened under an awakening command input by external equipment and sending an information reading command to the storage controller after being awakened;
the memory controller is used for being awakened under the awakening command input by external equipment, receiving the information reading command sent by the microcontroller after being awakened, awakening the memory according to the information reading command, reading the starting information stored in the memory after the memory is awakened, and sending the starting information to the microcontroller;
the microcontroller is also used for finishing self starting based on the starting information and starting the memory and the memory controller based on the starting information.
2. The memory booting system of claim 1, wherein the memory controller includes a pre-wake-up module electrically connected to the memory, the pre-wake-up module being configured to send a level signal to the memory to wake up the memory based on the level signal when the memory is in an un-wake-up state and the memory controller fails to read the booting information stored in the memory.
3. The memory activation system of claim 2, wherein the memory controller is an OTP microcontroller and the memory is an OTP memory.
4. A storage boot method applied to the storage boot system according to any one of claims 1 to 3, the storage boot method comprising: when the storage starting system is in an un-awakened state, executing the following steps:
the storage controller of the storage boot system and the microcontroller of the storage boot system are awakened under an awakening command input by external equipment respectively;
after being awakened, the microcontroller sends an information reading command to the storage controller;
the storage controller receives the information reading command after being awakened, awakens a memory of the storage starting system according to the information reading command, reads starting information stored in the memory and sends the starting information to the microcontroller after the memory is awakened;
and the microcontroller completes self starting based on the starting information and starts the memory and the memory controller based on the starting information so as to enable the memory starting system to enter a working state.
5. The storage boot method of claim 4, wherein the non-awake state comprises a sleep state.
6. The memory booting method according to claim 5, wherein before the step of performing the memory controller and the microcontroller to be woken up by a wake-up command respectively input from an external device, the method further comprises:
when the microcontroller and the storage controller in the working state receive a sleep command sent by an external device, the microcontroller controls the storage controller to configure the memory according to the sleep command so as to enable the memory to enter the sleep state, and after the memory enters the sleep state, the storage controller and the microcontroller enter the sleep state, so that the storage starting system enters the sleep state.
7. The storage boot method of claim 5, wherein a power consumption of the storage boot system in the hibernation state is lower than a power consumption of the storage boot system in the active state.
8. The memory booting method of claim 5, wherein the memory controller waking up the memory according to the information read command comprises:
the memory controller executes the information reading command, reads the starting information stored in the memory in the dormant state, and changes the bus signal of the memory starting system from high level to low level when reading fails, so as to trigger a pre-awakening module in the memory controller, so that the pre-awakening module sends a level signal to the memory to awaken the memory, and the memory controller changes the bus signal of the memory starting system from low level to high level after the memory is awakened.
9. The memory boot method according to claim 8, wherein the memory is in a read/write operation disabled state when the memory controller changes a bus signal of the memory boot system from a high level to a low level.
10. The memory boot method according to claim 8, wherein the memory is in a read-write operation valid state when the memory controller changes a bus signal of the memory boot system from a low level to a high level.
11. The storage BOOT method according to claim 8, wherein the BOOT information in the memory includes a BOOT code, wherein the BOOT code is a code that is executed when the storage BOOT system enters the operating state from the sleep state.
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