CN106874161B - Method and device for processing cache exception - Google Patents
Method and device for processing cache exception Download PDFInfo
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- CN106874161B CN106874161B CN201710052784.6A CN201710052784A CN106874161B CN 106874161 B CN106874161 B CN 106874161B CN 201710052784 A CN201710052784 A CN 201710052784A CN 106874161 B CN106874161 B CN 106874161B
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
Abstract
The embodiment of the invention provides a method and a device for processing cache exception, wherein the method comprises the following steps: detecting cache abnormity, and reading a register of a first-level cache and a register of a second-level cache; identifying an abnormal cache line generating cache abnormity according to the read registers of the first-level cache and the second-level cache; determining that a cache way to which the abnormal cache line belongs is located in a first-level cache, and judging whether the first-level cache has an available cache way or not according to a register for recording the state of the cache way of the first-level cache; if so, in a register for recording the state of the cache way of the first-level cache, recording that the cache way to which the abnormal cache line belongs is unavailable, and closing the cache way to which the abnormal cache line belongs; if not, performing restart. By applying the embodiment of the invention, the stability of the communication equipment is improved, and the influence on the service is reduced.
Description
Technical Field
The invention relates to the technical field of computers, in particular to a method and a device for processing Cache abnormity.
Background
At present, the access speed of a Central Processing Unit (CPU) is higher and higher, and the access speed of a memory is slowly improved, which causes the bottleneck of the CPU access speed when the CPU obtains instructions from the memory or reads and writes data in the memory. Based on this situation, the Cache (Cache) comes up.
Cache is a special memory subsystem, located between the CPU and the memory. Generally, caches are divided into a primary (L1, level 1) Cache and a secondary (L2, level 2) Cache. The L1Cache is integrated inside the CPU, and includes multiple Cache ways, each of which includes multiple Cache lines. The L2Cache is integrated on the mainboard and comprises a plurality of banks (storage units); wherein each Bank comprises a plurality of Cache ways, and each Cache way comprises a plurality of Cache lines. The storage capacities of the L1Cache and the L2Cache are small, but the access speed is high, the CPU can quickly acquire instructions or read and write data from the L1Cache and the L2Cache, and the access speed of the CPU is greatly improved. However, the Cache cost is high, and the storage capacity is small, which makes the processing of Cache exception very important.
In the prior art, when a communication device detects that a Cache is abnormal, a register of an L1Cache and a register of an L2Cache are read, abnormal information of an L1Cache and/or Cache abnormal information of an L2Cache are recorded, and the communication device executes restart. However, the problem caused by the processing mode of the Cache exception is that the Cache exception of the communication device is an accidental exception, and it cannot be determined when the communication device is restarted due to the Cache exception, which causes unstable influence on communication running of the communication device, causes network data interruption, and affects service processing.
Disclosure of Invention
The embodiment of the invention aims to provide a method and a device for processing cache exception, so as to improve the stability of communication equipment and reduce the influence on business. The specific technical scheme is as follows:
in one aspect, an embodiment of the present invention discloses a method for processing a cache exception, where the method includes:
detecting cache abnormity, and reading a register of a first-level cache and a register of a second-level cache;
according to the read registers of the first-level cache and the second-level cache, identifying an abnormal cache line generating the cache abnormity;
determining that the cache way to which the abnormal cache line belongs is located in the first-level cache, and judging whether the first-level cache has an available cache way or not according to a register for recording the state of the cache way of the first-level cache;
if yes, in the register for recording the state of the cache way of the first-level cache, recording that the cache way to which the abnormal cache line belongs is unavailable, and closing the cache way to which the abnormal cache line belongs;
if not, performing restart.
In another aspect, an embodiment of the present invention discloses a device for handling a cache exception, where the device includes:
a detection module for detecting cache anomalies;
the reading module is used for reading a register of the first-level cache and a register of the second-level cache when the cache abnormity is detected;
the identification module is used for identifying an abnormal cache line generating the cache abnormity according to the read registers of the first-level cache and the second-level cache;
the control module is used for determining that the cache way to which the abnormal cache line belongs is positioned in the first-level cache, and judging whether the first-level cache has an available cache way or not according to a register for recording the state of the cache way of the first-level cache; if yes, in the register for recording the state of the cache way of the first-level cache, recording that the cache way to which the abnormal cache line belongs is unavailable, and closing the cache way to which the abnormal cache line belongs; if not, performing restart.
In the embodiment of the invention, when the communication equipment detects that the Cache is abnormal, when available Cache ways exist in the L1Cache or the Bank of the L2Cache, the Cache way with the Cache abnormality is recorded first, then the Cache way with the Cache abnormality is closed, and the available Cache ways in the Bank of the L1Cache or the L2Cache are continuously used, so that the times of restarting the communication equipment due to the Cache abnormality are reduced, the stability of the communication equipment is improved, and the influence on message forwarding service is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic flow diagram of a method for processing Cache exceptions according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating a register for recording a Cache way status of an L1Cache according to an embodiment of the present invention;
FIG. 3 is a diagram of the register in FIG. 2 recording the Cache way status of L1Cache to record an unavailable Cache way;
FIG. 4 is a schematic diagram of the registers in FIGS. 2 and 3 recording the Cache way status of the L1Cache to record the unavailable Cache way;
FIG. 5 is a diagram illustrating a register that records a Cache way state of an L1Cache shared by two threads according to an embodiment of the present invention;
FIG. 6 is a schematic diagram of the register recording the unavailable Cache way of the Cache way state of the L1Cache shared by the two threads in FIG. 5;
FIG. 7 is a diagram illustrating a register for recording a Cache way status of an L2Cache according to an embodiment of the present invention;
FIG. 8 is a diagram of FIG. 7 showing a register recording an unavailable Cache way for the Cache way state of the L2 Cache;
FIG. 9 is a schematic diagram of the registers in FIGS. 7 and 8 recording the Cache way status of the L2Cache to record the unavailable Cache way;
fig. 10 is a schematic structural diagram of a Cache exception handling device according to an embodiment of the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The present invention will be described in detail below with reference to specific examples.
Referring to fig. 1, fig. 1 is a schematic flowchart of a method for processing a Cache exception according to an embodiment of the present invention. Generally, caches are classified into L1Cache and L2 Cache. The LCache comprises a plurality of Cache ways, and each Cache way comprises a plurality of Cache lines; the L2Cache includes a plurality of banks, each Bank including a plurality of Cache ways, each Cache way including a plurality of Cache lines. Specifically, the method comprises the following steps:
step 101, detecting cache abnormity, reading a register of a first-level cache and a register of a second-level cache;
step 102, identifying an abnormal cache line generating cache abnormity according to the read registers of the first-level cache and the second-level cache;
step 103, determining that the cache way to which the abnormal cache line belongs is located in a first-level cache;
104, judging whether the first-level cache has an available cache way or not according to a register for recording the cache way state of the first-level cache; if yes, go to step 105; if not, go to step 107;
105, recording the unavailability of a cache way to which an abnormal cache line belongs in a register for recording the state of the cache way of the first-level cache;
step 106, closing the cache way to which the abnormal cache line belongs;
in step 107, a restart is performed.
Specifically, the CPU of the communication device may adopt a SECDED (Single Error Correction and Double Error Detection, Single Error Correction, multiple Error discovery) technique in an ECC (Error Correction Code) technique to detect whether there is an erroneous Bit in each Cache line included in each Cache way of the L1Cache and the L2Cache, and if there is an erroneous Bit, perform checking and Correcting; if a plurality of wrong bits exist, determining that Cache line is abnormal, reading a register of an L1Cache and a register of an L2Cache, and determining whether the Cache line with the Cache abnormality is located in the L1Cache or the L2Cache according to the read information;
if the Cache line with the Cache exception (namely the exception Cache line) is located in the L1Cache, determining the Cache way to which the Cache line with the Cache exception belongs, and setting the Cache way as unavailable.
For example: the size of the storage space of one Cache way is 4KB, the size of the storage space of one Cache line is 32 bytes, one Cache way can comprise 128 Cache lines of 0-Cache line127, and if any Cache line of 0-Cache line127 in one Cache way is detected to have Cache abnormity, the Cache way is set to be unavailable.
Before the Cache way to which the Cache line in the L1Cache with the Cache abnormality belongs is set to be unavailable, whether an available Cache way still exists in the L1Cache can be detected, if the available Cache way exists, the Cache way to which the Cache line in the L1Cache with the Cache abnormality belongs is set to be unavailable, the unavailable Cache way in the L1Cache is closed, and the communication equipment can continue to use the available Cache way in the L1Cache for communication, so that the service is processed, and the influence on the service is reduced; if no available Cache Way exists, the Cache Way which can process the service is not available in the L1Cache, then the Cache Way which belongs to the Cache line with the Cache exception in the L1Cache is set to be unavailable, the operation of closing the unavailable Way in the L1Cache does not have any meaning, and the communication equipment can be directly restarted at the moment.
In one embodiment of the invention, in order to facilitate determining whether a Way available in the current L1Cache exists, whether the Cache Way of the L1Cache is available may be recorded by a register.
FIG. 2 is a diagram illustrating a register for recording a Cache way status of the L1Cache according to an embodiment of the present invention. Assume that the L1Cache of the communication device has 8 Cache ways. In the register shown in FIG. 2, which records the Cache way state of the L1Cache, Bit0-Bit7 indicates whether the Cache way0-Cache way 7 of the L1Cache is available; and in the initial state, each Bit value of the Bit0-Bit7 of the register for recording the Cache way state of the L1Cache is set to be 0, and the register is used for indicating that the Cache way corresponding to each Bit is available.
FIG. 3 is a diagram of the register in FIG. 2 recording the Cache way status of L1Cache to record an unavailable Cache way; when the communication equipment detects that the Cache is abnormal, reading a register of an L1Cache and a register of an L2Cache, writing instructions and data stored by the L1Cache and the L2Cache into a memory, detecting that a Cache line with the Cache abnormality is located at a Cache way0 of an L1Cache according to the read register of the L1Cache and the read register of the L2Cache, determining that an available Cache way exists in the L1Cache, performing OR operation on Bit0 indicating the Cache way0 in the register recording the Cache way state of the L1Cache, modifying the initial value of the Bit0 from '0' to '1', and indicating that the Cache way0 of the L1Cache is unavailable; the communication device closes Cache way0 of L1 Cache.
In fig. 3, when a Cache exception occurs in the communication device, before the Cache way0 of the L1Cache is recorded to be unavailable, the instructions and data recorded in the L1Cache and the L2Cache are written back into the memory, so that the consistency of the data is ensured, and the loss of the stored data and instructions due to the fact that the Cache way0 is the last available Cache way in the L1Cache and needs to be restarted is avoided.
FIG. 4 is a schematic diagram of the registers in FIGS. 2 and 3 recording the Cache way status of the L1Cache to record the unavailable Cache way; the communication equipment detects the Cache abnormality again, reads a register of an L1Cache and a register of an L2Cache, writes instructions and data stored by the L1Cache and the L2Cache into a memory, detects that a Cache line with the Cache abnormality is located in a Cache way 3 of an L1Cache according to the read register of the L1Cache and the read register of the L2Cache, determines that an available Cache way exists in the L1Cache, performs 'OR' operation on Bit 3 indicating the Cache way 3 in the register recording the Cache way state of the L1Cache, modifies the initial value of the Bit 3 from '0' to '1', and indicates that the Cache way 3 of the L1Cache is unavailable; the communication device closes Cache way 3 of L1 Cache.
Supposing that the communication device has closed 7 Cache ways in the L1Cache, and detects that the Cache line in which the Cache exception occurs is located in one Cache way of the L1Cache again, after writing the instructions and data stored in the L1Cache and the L2Cache into the memory, it is determined that the L1Cache has no available Cache way, the communication device restarts the Cache, and the communication device does not need to set the Bit, which indicates the last unavailable Cache way, in the register recording the Cache way state of the L1Cache as unavailable.
In other embodiments of the present invention, the communication device may determine whether an available Cache way exists in the L1Cache according to the number of bits whose value is "0" in the register that records the Cache way state of the L1Cache, or the communication device may determine whether an available Cache way exists in the L1Cache according to the number of bits whose value is "1" in the register that records the Cache way state of the L1 Cache. For example, if the number of bits with a value of "0" read by the communication device from the register recording the Cache way status of the L1Cache is 1, it is determined that the Cache line in which the Cache exception occurs currently is located in the only available Cache way of the L1Cache, and the L1Cache does not have an available Cache way. Or, for example, if the number of bits having a value of "1" read by the communication device from the register recording the Cache way status of the L1Cache is 7 (the total number of Cache ways of the L1Cache is minus 1), it is determined that the Cache line in which the Cache exception currently occurs is located in the only available Cache way of the L1Cache, and the L1Cache does not have an available Cache way.
In an embodiment of the present invention, a CPU of a communication device includes multiple cores, that is, a multi-core CPU, each core of the multi-core CPU may have multiple threads, and the threads share a storage space of a Cache line of each Cache way of an L1 Cache. In this case, after determining the Cache way of the L1Cache to which the Cache line with the Cache exception belongs, it is necessary to record all the Cache ways to which the Cache line with the Cache exception occurs, which correspond to each thread in the L1Cache, as unusable in the register that records the Cache way state of the L1Cache shared by these threads, and to close all the unusable Cache ways to which the Cache line with the Cache exception occurs, which correspond to each thread in the L1 Cache.
FIG. 5 is a diagram illustrating a register that records a Cache way state of an L1Cache shared by two threads according to an embodiment of the present invention; suppose that one of the cores of the CPU runs 2 threads, sharing 8 Cache ways of the L1 Cache. In the register shown in fig. 5, which records the Cache way states of the L1Cache shared by the two threads, Bit0 to Bit7 indicate whether 8 Cache ways of the L1Cache shared by the thread 1 are available, and Bit8 to Bit 15 indicate whether 8 Cache ways of the L1Cache shared by the thread 2 are available.
FIG. 6 is a schematic diagram of the register recording the unavailable Cache way of the Cache way state of the L1Cache shared by the two threads in FIG. 5; when the communication equipment detects that the Cache is abnormal, reading a register of an L1Cache and a register of an L2Cache, writing instructions and data stored by the L1Cache and the L2Cache into a memory, detecting that a Cache line with the Cache abnormality is located in a Cache way0 of an L1Cache according to the read register of the L1Cache and the read register of the L2Cache, determining that an available Cache way exists in the L1Cache, performing OR operation on Bit0 of the Cache way0 used by an indication thread 1, modifying the initial value of the Bit0 from '0' to '1', performing OR operation on Bit8 of the Cache way0 used by the indication thread 2, modifying the initial value of the Bit8 from '0' to '1', and thus recording that the Cache way0 of the L1Cache shared by the thread 1 and the thread 2 is unavailable; the communication device closes Cache way0 of the L1Cache shared by thread 1 and thread 2.
In other embodiments of the present invention, when the communication device detects that a Cache is abnormal, a register of an L1Cache and a register of an L2Cache are read, and according to the read register of the L1Cache and the read register of the L2Cache, it is detected that a Cache way to which a Cache line in which the Cache is abnormal belongs is located in one Bank of the L2Cache, if it is detected that an available Cache way also exists in a Bank to which the Cache way to which the Cache line in which the Cache is abnormal belongs, the Cache way to which the Cache line in which the Cache is abnormal belongs is closed, and the communication device can continue to use other available Cache ways in the Bank, thereby reducing an influence on a service; if the Bank does not have available Cache way, the operation of closing the Cache way to which the Cache line with Cache exception belongs does not need to be executed any more, and the communication equipment can be directly restarted.
FIG. 7 is a diagram illustrating a register for recording a Cache way status of the L2Cache according to an embodiment of the present invention. Assume that the L2Cache of the communication device includes 2 banks: bank0 and Bank 1; bank0 and Bank 1 each include 8 Cache ways. In the register shown in FIG. 7, which records the Cache way status of the L2Cache, the initial value of Bit0-Bit7 may be set to "0" to indicate that Bank0 Cache way0-Cache way 7 is available, and the initial value of Bit8-Bit 15 may be set to "0" to indicate that Bank 1Cache way0-Cache way 7 is available.
FIG. 8 is a diagram of FIG. 7 showing a register recording an unavailable Cache way for the Cache way state of the L2 Cache; when the communication equipment detects that the Cache is abnormal, reading a register of an L1Cache and a register of an L2Cache, writing instructions and data stored by the L1Cache and the L2Cache into a memory, detecting that a Cache line with the Cache abnormality is located in a Cache way0 of a Bank0 of an L2Cache according to the read register of the L1Cache and the read register of the L2Cache, determining that an available Cache way exists in the Bank0 of the L2Cache, performing OR operation on a Bit0 of the Cache way0 indicating the Bank0 in a register recording the Cache way state of the L2Cache, modifying the initial value of the Bit0 from '0' to '1', and indicating that the Cache way0 of the Bank0 of the L2Cache is unavailable; the communication device closes Cache way0 of Bank0 of L2 Cache.
FIG. 9 is a schematic diagram of the registers in FIGS. 7 and 8 recording the Cache way status of the L2Cache to record the unavailable Cache way; when the communication equipment detects that the Cache is abnormal, reading a register of an L1Cache and a register of an L2Cache, writing instructions and data stored by the L1Cache and the L2Cache into a memory, detecting that a Cache line with the Cache abnormality is located in a Cache way 3 of a Bank 1 of an L2Cache according to the read register of the L1Cache and the read register of the L2Cache, determining that an available Cache way exists in the Bank 1 of the L2Cache, carrying out 'OR' operation on a Bit 11 in the register for recording the Cache way state of the L2Cache, modifying an initial value of the Bit 11 from '0' to '1', and indicating that the Cache way 3 of the Bank 1 of the L2Cache is unavailable; the communication device closes Bank 1Cache way 3 of L2 Cache.
Supposing that the communication device has closed 7 Cache ways of Bank0 of the L2Cache, detects that the Cache line with Cache abnormality is located in one Cache way of Bank0 of the L2Cache again, writes the instructions and data stored in the L1Cache and the L2Cache into the memory, determines that the Bank0 of the L2Cache has no available Cache way, and restarts the communication device without restarting the communication device after all the Cache ways of Bank0 recording the L2Cache are set to be unavailable.
In other embodiments of the present invention, the communication device may determine whether there is an available Cache way in each Bank of the L2Cache according to the number of bits with a value of "0" in the register that records the Cache way state of the L2Cache, or the communication device may determine whether there is an available Cache way in each Bank of the L2Cache according to the number of bits with a value of "1" in the register that records the Cache way state of the L2 Cache.
For example, if the number of bits with the value "0" read by the communication device from Bit-0-Bit7 of the register recording the Cache way status of the L2Cache is 1, it is determined that the Cache line currently having the Cache exception is located in the only available Cache way of Bank0 of the L2Cache, and the no available Cache way of Bank0 of the L2 Cache. Or the communication equipment reads 7 bits with the value of 1 from the Bit0-Bit7 of the register for recording the Cache way state of the L2Cache, and then the communication equipment determines that the Cache line with Cache exception currently is located in the only available Cache way of the Bank0 of the L2Cache, and the Bank0 of the L2Cache has no available Cache way.
Similarly, the communication equipment reads 1 Bit with the value of 0 from the Bit-8-Bit 15 of the register for recording the Cache way state of the L2Cache, and then determines that the Cache line with the Cache exception currently is located in the only available Cache way of the Bank 1 of the L2Cache, and the Bank 1 of the L2Cache has no available Cache way. Or the communication equipment reads 7 bits with the value of 1 from the Bit8-Bit 15 of the register for recording the Cache way state of the L2Cache, and then determines that the Cache line with Cache exception currently is located in the only available Cache way of the Bank 1 of the L2Cache, and the Bank 1 of the L2Cache has no available Cache way.
By applying the embodiment, when the communication equipment detects that the Cache is abnormal, when available Cache ways exist in the L1Cache or the Bank of the L2Cache, the Cache way with the Cache abnormality is recorded first, then the Cache way with the Cache abnormality is closed, and the available Cache ways in the Bank of the L1Cache or the L2Cache are continuously used, so that the times of restarting the communication equipment due to the Cache abnormality are reduced, the stability of the communication equipment is improved, and the influence on the message forwarding service is reduced.
Referring to fig. 10, fig. 10 is a schematic structural diagram of a Cache exception handling device according to an embodiment of the present invention, where the device includes:
a detection module 1001 for detecting cache exceptions;
a reading module 1002, configured to read a register of a first-level cache and a register of a second-level cache when a cache anomaly is detected;
an identifying module 1003, configured to identify an exception cache line in which a cache exception occurs according to the read register of the first-level cache and the read register of the second-level cache;
the control module 1004 is configured to determine that a cache way to which the abnormal cache line belongs is located in the primary cache, and determine whether the primary cache has an available cache way according to a register that records a cache way state of the primary cache; if so, in a register for recording the state of the cache way of the first-level cache, recording that the cache way to which the abnormal cache line belongs is unavailable, and closing the cache way to which the abnormal cache line belongs; if not, performing restart.
In other embodiments of the present invention, the control module 1004 may further be configured to:
determining that a cache way to which the abnormal cache line belongs is positioned in a first-level cache and shared by a plurality of threads, and judging whether the first-level cache has an available cache way or not according to a register for recording the cache way state of the first-level cache shared by the plurality of threads; if yes, in a register for recording the cache way state of a primary cache shared by a plurality of threads, recording the cache way to which the abnormal cache line used by each thread belongs as unavailable; closing a cache way to which an abnormal cache line shared by a plurality of threads belongs; if not, performing restart.
In other embodiments of the present invention, the control module 1004 may further be configured to:
determining that a cache way to which the abnormal cache line belongs is located in one storage unit of the second-level cache, and judging whether the storage unit to which the cache way to which the abnormal cache line belongs is located has an available cache way or not according to a register for recording the cache way state of each storage unit of the second-level cache; if so, recording that the cache way to which the abnormal cache line belongs is unavailable in a register for recording the cache way state of each storage unit of the second-level cache; closing the cache way to which the abnormal cache line belongs; if not, performing restart.
In other embodiments of the present invention, the control module 1004 may further be configured to:
and the storage module records the data and the instructions stored in the first-level cache and the second-level cache in the memory.
By applying the embodiment, when the communication equipment detects that the Cache is abnormal, when available Cache ways exist in the L1Cache or the Bank of the L2Cache, the Cache way with the Cache abnormality is recorded first, then the Cache way with the Cache abnormality is closed, and the available Cache ways in the Bank of the L1Cache or the L2Cache are continuously used, so that the times of restarting the communication equipment due to the Cache abnormality are reduced, the stability of the communication equipment is improved, and the influence on the message forwarding service is reduced.
It is noted that, herein, relational terms such as first and second, and the like may be used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Also, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising an … …" does not exclude the presence of other identical elements in a process, method, article, or apparatus that comprises the element.
All the embodiments in the present specification are described in a related manner, and the same and similar parts among the embodiments may be referred to each other, and each embodiment focuses on the differences from the other embodiments. In particular, for the system embodiment, since it is substantially similar to the method embodiment, the description is simple, and for the relevant points, reference may be made to the partial description of the method embodiment.
The above description is only for the preferred embodiment of the present invention, and is not intended to limit the scope of the present invention. Any modification, equivalent replacement, or improvement made within the spirit and principle of the present invention shall fall within the protection scope of the present invention.
Claims (6)
1. A method of handling cache exceptions, the method comprising:
detecting cache abnormity, and reading a register of a first-level cache and a register of a second-level cache;
according to the read registers of the first-level cache and the second-level cache, identifying an abnormal cache line generating the cache abnormity;
determining that a cache way to which the abnormal cache line belongs is located in the first-level cache and shared by a plurality of threads, and judging whether the first-level cache has an available cache way or not according to a register recording the cache way state of the first-level cache shared by the plurality of threads;
if yes, in the register for recording the cache way state of the primary cache shared by the threads, recording the cache way to which the abnormal cache line used by each thread belongs as unavailable; closing a cache way to which the exception cache line shared by the plurality of threads belongs;
if not, performing restart.
2. The method of claim 1, further comprising:
determining that the cache way to which the abnormal cache line belongs is located in one of the storage units of the secondary cache, and judging whether the storage unit to which the cache way to which the abnormal cache line belongs is located has an available cache way according to a register for recording the cache way state of each storage unit of the secondary cache;
if so, recording that the cache way to which the abnormal cache line belongs is unavailable in the register for recording the cache way state of each storage unit of the second-level cache; closing the cache way to which the abnormal cache line belongs;
if not, performing restart.
3. The method of claim 1, wherein after identifying the anomalous cache line that produced the cache exception, the method further comprises:
and recording the data and the instructions stored in the first-level cache and the second-level cache in a memory.
4. An apparatus for handling cache exceptions, the apparatus comprising:
a detection module for detecting cache anomalies;
the reading module is used for reading a register of the first-level cache and a register of the second-level cache when the cache abnormity is detected;
the identification module is used for identifying an abnormal cache line generating the cache abnormity according to the read registers of the first-level cache and the second-level cache;
the control module is used for determining that a cache way to which the abnormal cache line belongs is positioned in the first-level cache and shared by a plurality of threads, and judging whether the first-level cache has an available cache way or not according to a register for recording the cache way state of the first-level cache shared by the plurality of threads; if yes, in the register for recording the cache way state of the primary cache shared by the threads, recording the cache way to which the abnormal cache line used by each thread belongs as unavailable; closing a cache way to which the exception cache line shared by the plurality of threads belongs; if not, performing restart.
5. The apparatus of claim 4, wherein the control module is further configured to:
determining that the cache way to which the abnormal cache line belongs is located in one of the storage units of the secondary cache, and judging whether the storage unit to which the cache way to which the abnormal cache line belongs is located has an available cache way according to a register for recording the cache way state of each storage unit of the secondary cache; if so, recording that the cache way to which the abnormal cache line belongs is unavailable in the register for recording the cache way state of each storage unit of the second-level cache; closing the cache way to which the abnormal cache line belongs; if not, performing restart.
6. The apparatus of claim 4, further comprising:
and the storage module records the data and the instructions stored in the first-level cache and the second-level cache in a memory.
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| CN201710052784.6A CN106874161B (en) | 2017-01-24 | 2017-01-24 | Method and device for processing cache exception |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6038693A (en) * | 1998-09-23 | 2000-03-14 | Intel Corporation | Error correction scheme for an integrated L2 cache |
| CN1518700A (en) * | 2001-06-22 | 2004-08-04 | 皇家菲利浦电子有限公司 | Fast and acurate cache way selection |
| CN1979451A (en) * | 2005-12-08 | 2007-06-13 | 国际商业机器公司 | Methods and apparatus for handling a cache miss |
| CN102929796A (en) * | 2012-06-01 | 2013-02-13 | 杭州中天微系统有限公司 | Memory management module simultaneously supporting software backfilling and hardware backfilling |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6038693A (en) * | 1998-09-23 | 2000-03-14 | Intel Corporation | Error correction scheme for an integrated L2 cache |
| CN1518700A (en) * | 2001-06-22 | 2004-08-04 | 皇家菲利浦电子有限公司 | Fast and acurate cache way selection |
| CN1979451A (en) * | 2005-12-08 | 2007-06-13 | 国际商业机器公司 | Methods and apparatus for handling a cache miss |
| CN102929796A (en) * | 2012-06-01 | 2013-02-13 | 杭州中天微系统有限公司 | Memory management module simultaneously supporting software backfilling and hardware backfilling |
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