CN106874161A - A kind of abnormal processing method and processing device of cache - Google Patents
A kind of abnormal processing method and processing device of cache Download PDFInfo
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- CN106874161A CN106874161A CN201710052784.6A CN201710052784A CN106874161A CN 106874161 A CN106874161 A CN 106874161A CN 201710052784 A CN201710052784 A CN 201710052784A CN 106874161 A CN106874161 A CN 106874161A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3037—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a memory, e.g. virtual memory, cache
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
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- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
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Abstract
A kind of abnormal processing method and processing device of cache is the embodiment of the invention provides, the method includes：Cache exception is detected, the register of on-chip cache and the register of second level cache is read；According to the register and the register of second level cache of the on-chip cache for reading, identification produces the abnormal abnormal cache line of cache；It is determined that the cache way belonging to abnormal cache line is located at on-chip cache, the register of the cache line state according to record on-chip cache judges whether on-chip cache also has available cache way；If it is, in the register of the cache line state of record on-chip cache, the cache way belonging to recording exceptional cache line is unavailable, the cache way belonging to abnormal cache line is closed；If not, execution is restarted.Using the embodiment of the present invention, the stability of communication equipment is improve, reduce the influence to business.
Description
Technical field
The present invention relates to field of computer technology, more particularly to a kind of cache Cache abnormal processing method and
Device.
Background technology
At present, the access speed more and more higher of central processing unit (CPU, Central Processing Unit), and internal memory
Access speed improvement it is slow, this causes CPU to become CPU from the data that internal memory is obtained in instruction or read/write memory to access speed
The bottleneck of degree.Based on the situation, Cache (cache) arises at the historic moment.
Cache is a kind of special memory sub-system, and it is located between CPU and internal memory.Usually, Cache points is one
Level (L1, level 1) Cache and two grade of (L2, level 2) Cache.L1 Cache are integrated in inside CPU, including multiple
Cache way (cache way), each Cache way include multiple Cache line (cache line).L2 Cache collection
Into on mainboard, including multiple Bank (memory cell)；Wherein each Bank includes multiple Cache way, each Cache way
Including multiple Cache line.Memory capacity all very littles of L1 Cache and L2 Cache, but access speed is quickly, CPU can be with
Instruction or read-write data are rapidly obtained from L1 Cache and L2 Cache, the access speed of CPU is drastically increased.But
Cache's is relatively costly, and memory capacity very little, and this causes to be particularly important the abnormal treatment of Cache.
In the prior art, communication equipment detect Cache it is abnormal when, read the register and L2Cache of L1 Cache
Register, the abnormal information of record L1 Cache and/or the Cache abnormal informations of L2 Cache, communication equipment is performed restarts.But
Problem caused by this Cache abnormal processing mode is that the Cache of communication equipment is accidental sexual abnormality extremely, it is impossible to
Determine when communication equipment can produce unstable to the communication of communication equipment operation again because Cache abnormal restartings
Influence, causes network data to be interrupted, traffic affecting treatment.
The content of the invention
The purpose of the embodiment of the present invention is to provide a kind of cache abnormal processing method and processing device, to improve communication
The stability of equipment, reduces the influence to business.Concrete technical scheme is as follows：
On the one hand, the embodiment of the invention discloses the processing method that a kind of cache is abnormal, methods described includes：
Cache exception is detected, the register of on-chip cache and the register of second level cache is read；
According to the register and the register of the second level cache of the on-chip cache for reading, identification is produced
The abnormal abnormal cache line of the cache；
Determine that the cache way belonging to the abnormal cache line is located at the on-chip cache, according to record institute
The register of the cache line state of on-chip cache is stated, judges whether the on-chip cache also has available high speed
Cache way；
If it is, in the register of the cache line state of the record on-chip cache, recording the exception
Cache way belonging to cache line is unavailable, closes the cache way belonging to the abnormal cache line；
If not, execution is restarted.
On the other hand, the embodiment of the invention discloses the processing unit that a kind of cache is abnormal, described device includes：
Detection module, for detecting cache exception；
Read module, for when detecting cache and being abnormal, read on-chip cache register and two grades high
The register of speed caching；
Identification module, for according to the register of the on-chip cache and posting for the second level cache for reading
Storage, identification produces the abnormal abnormal cache line of the cache；
Control module, for determining that it is slow at a high speed that the cache way belonging to the abnormal cache line is located at the one-level
Deposit, according to the register of the cache line state for recording the on-chip cache, whether judge the on-chip cache
Also available cache way；If it is, in the register of the cache line state of the record on-chip cache,
The cache way recorded belonging to the abnormal cache line is unavailable, closes the high speed belonging to the abnormal cache line
Cache way；If not, execution is restarted.
In the embodiment of the present invention, communication equipment detects Cache exceptions, L1 Cache or L2 Cache Bank also
When having available Cache way, first there is the abnormal Cache way of Cache in record, turns off and the abnormal Cache of Cache occur
Way, is continuing with the available Cache way in the Bank of L1 Cache or L2 Cache, reduce communication equipment due to
The Cache abnormal number of times restarted, improves the stability of communication equipment, reduces the influence to message forwarding service.
Brief description of the drawings
In order to illustrate more clearly about the embodiment of the present invention or technical scheme of the prior art, below will be to embodiment or existing
The accompanying drawing to be used needed for having technology description is briefly described, it should be apparent that, drawings in the following description are only this
Some embodiments of invention, for those of ordinary skill in the art, on the premise of not paying creative work, can be with
Other accompanying drawings are obtained according to these accompanying drawings.
Fig. 1 is a kind of schematic flow sheet of the abnormal processing methods of Cache provided in an embodiment of the present invention；
Fig. 2 is the schematic diagram of the register of the Cache way states of record L1 Cache in the embodiment of the present invention；
Fig. 3 is that the register of the Cache way states of record L1 Cache in Fig. 2 records showing for unavailable Cache way
It is intended to；
Fig. 4 is that the register of the Cache way states of record L1 Cache in Fig. 2 and Fig. 3 records unavailable Cache way
Schematic diagram；
Fig. 5 is the register of the Cache way states of the shared L1 Cache of two threads of record in the embodiment of the present invention
Schematic diagram；
Fig. 6 records unavailable for the register of the Cache way states of the shared L1 Cache of two threads of record in Fig. 5
The schematic diagram of Cache way；
Fig. 7 is the schematic diagram of the register of the Cache way states of record L2 Cache in the embodiment of the present invention；
Fig. 8 is that the register of the Cache way states of record L2 Cache in Fig. 7 records showing for unavailable Cache way
It is intended to；
Fig. 9 is that the register of the Cache way states of record L2 Cache in Fig. 7 and Fig. 8 records unavailable Cache way
Schematic diagram；
Figure 10 is a kind of structural representation of the abnormal processing units of Cache provided in an embodiment of the present invention.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, it is every other that those of ordinary skill in the art are obtained under the premise of creative work is not made
Embodiment, belongs to the scope of protection of the invention.
Below by specific embodiment, the present invention is described in detail.
With reference to Fig. 1, Fig. 1 is a kind of schematic flow sheet of the abnormal processing methods of Cache provided in an embodiment of the present invention.One
As, Cache points is L1 Cache and L2 Cache.LCache includes that multiple Cache way, each Cache way include many
Individual Cache line；L2 Cache include that multiple Bank, each Bank include that multiple Cache way, each Cache way include
Multiple Cache line.Specifically, the method includes：
Step 101, detects cache exception, reads the register of on-chip cache and posting for second level cache
Storage；
Step 102, according to the register and the register of second level cache of the on-chip cache for reading, identification is produced
The abnormal abnormal cache line of cache；
Step 103, it is determined that the cache way belonging to abnormal cache line is located at on-chip cache；
Step 104, the register of the cache line state according to record on-chip cache, judges on-chip cache
Whether available cache way is also had；If it is, performing step 105；If not, performing step 107；
Step 105, in the register of the cache line state of record on-chip cache, recording exceptional cache
Cache way belonging to row is unavailable；
Step 106, closes the cache way belonging to abnormal cache line；
Step 107, execution is restarted.
Specifically, the CPU of communication equipment can be using ECC (Error Correcting Code, error checking and correction)
In technology SECDED (Single Error Correction and Double Error Detection, single error correction,
Many error detections) technology, be in each Cache line that each Cache way of detection L1 Cache and L2 Cache includes
The no Bit (bit) that there is mistake, if in the presence of a Bit for mistake, being checked and being corrected；If in the presence of multiple mistakes
Bit, it is determined that Cache line occur Cache exceptions, reads the register of L1 Cache and the register of L2 Cache, according to
The information for reading can determine that it is to be located at L1 Cache that the abnormal Cache line of Cache occur, or positioned at L2
Cache；
L1 Cache are located in the event of Cache abnormal Cache line (namely exception Cache line), then really
Surely there is the Cache way belonging to the abnormal Cache line of Cache, and this Cache way is set to unavailable.
For example：One storage size of Cache way is 4KB, and the storage size of a Cache line is
32byte, then a Cache way can be including this 128 Cache line of Cache line0-Cache line127, if inspection
Measure in a Cache way that any Cache line have Cache exceptions in Cache line0-Cache line127, then
This Cache way is set to unavailable.
By the Cache way occurred in L1 Cache belonging to the abnormal Cache line of Cache be set to it is unavailable it
Before, can first detect in L1 Cache whether also there is available Cache way, if there is available Cache way, then will
There is the Cache way belonging to the abnormal Cache line of Cache in L1 Cache and be set to unavailable, and then close L1
Disabled Cache way in Cache, available Cache way are led to during communication equipment can be continuing with L1 Cache
Letter, processing business reduces the influence to business；If there is no available Cache way, no longer having in L1 Cache can
With the Cache way of processing business, then perform the Cache belonging to the Cache line that Cache exceptions will occur in L1 Cache
Way is set to unavailable, and the operation for closing disabled Way in L1 Cache will be without in all senses, now can be direct
Restart communication equipment.
In one embodiment of the invention, for the ease of determining to whether there is available Way in current L1 Cache, can
Whether be can use with the Cache way that L1 Cache are recorded by register.
Fig. 2 is the schematic diagram of the register of the Cache way states of record L1 Cache in the embodiment of the present invention.It is assumed that
The L1 Cache of communication equipment have 8 Cache way.Posted in the Cache way states of record L1 Cache shown in Fig. 2
In storage, Bit 0-Bit 7 indicate whether the Cache way 0-Cache way 7 of L1 Cache can use；Record L1 Cache
Cache way states register Bit 0-Bit 7 in an initial condition, each Bit value both is set to " 0 ", is used for
The corresponding Cache way of each Bit are indicated to can use.
Fig. 3 is that the register of the Cache way states of record L1 Cache in Fig. 2 records showing for unavailable Cache way
It is intended to；When communication equipment detects Cache exceptions, the register of L1 Cache and the register of L2 Cache are read, by L1
The instruction and data of Cache and L2 Cache storages writes internal memory, the register and L2 Cache according to the L1Cache for reading
Register, detects and the Cache way 0 that the abnormal Cache line of Cache are located at L1 Cache occurs, and determination L1
There are available Cache way in Cache, to indicating Cache way in the register of the Cache way states for recording L1Cache
0 Bit 0 carries out OR operation, and the initial value of Bit 0 is revised as " 1 " from " 0 ", indicates the Cache way 0 of L1 Cache
For unavailable；Communication equipment closes the Cache way 0 of L1 Cache.
In Fig. 3, communication equipment occur Cache it is abnormal when, the Cache way 0 of record L1 Cache it is unavailable it
Before, first by L1 Cache and L2 Cache record instruction and data be written back in internal memory, it is ensured that the uniformity of data and
Avoid Cache way 0 be in L1 Cache last available Cache way and caused by needing to restart storage number
According to the loss with instruction.
Fig. 4 is that the register of the Cache way states of record L1 Cache in Fig. 2 and Fig. 3 records unavailable Cache way
Schematic diagram；Communication equipment detects Cache exceptions again, reads the register of L1 Cache and the register of L2 Cache,
The instruction and data that L1 Cache and L2 Cache are stored writes internal memory, according to the register and L2 of the L1 Cache for reading
The register of Cache, detects and the Cache way 3 that the abnormal Cache line of Cache are located at L1 Cache occurs, and determination
There are available Cache way in L1 Cache, to indicating Cache in the register of the Cache way states of record L1 Cache
The Bit 3 of way 3 carries out OR operation, and the initial value of Bit 3 is revised as " 1 " from " 0 ", indicates the Cache of L1 Cache
Way 3 is unavailable；Communication equipment closes the Cache way 3 of L1 Cache.
It is assumed that communication equipment has had been switched off 7 Cache way in L1 Cache, generation Cache is detected again different
Normal Cache line are located at a Cache way of L1 Cache, the instruction sum that L1 Cache and L2 Cache are stored
According to write-in internal memory after, determine that L1 Cache have not had available Cache way, then restarted, communication equipment need not again by
The Bit of last unavailable Cache way is indicated to be set to not in the register of the Cache way states of record L1 Cache
Can use.
In other embodiments of the invention, communication equipment can posting according to the Cache way states of record L1 Cache
Numerical value is the number of the Bit of " 0 " in storage, determines whether L1 Cache also have available Cache way, or, communication equipment
Can be the number of the Bit of " 1 " according to numerical value in the register of the Cache way states of record L1 Cache, determine L1 Cache
Whether available Cache way are also had.For example, communication equipment is from the register of the Cache way states of record L1 Cache
The numerical value of reading is 1 for the number of the Bit of " 0 ", it is determined that the current Cache line that Cache exceptions occur are located at L1
Cache unique available Cache way, L1Cache do not have available Cache way.Or, for example, communication equipment is from record
The numerical value that the register of the Cache way states of L1 Cache reads for the Bit of " 1 " number for 7 (L1 Cache's
The total number of Cache way subtracts 1), it is determined that the current Cache line that Cache exceptions occur uniquely can use positioned at L1 Cache
Cache way, L1 Cache there is no available Cache way.
In one embodiment of the invention, the CPU of communication equipment contains multiple cores, i.e. multi-core CPU, multi-core CPU
Each core can have multiple threads, and the storage of the Cache line of each Cache way of the shared L1 Cache of these threads is empty
Between.In this case, it is determined that after the Cache way that the L1 Cache belonging to the abnormal Cache line of Cache occur, it is necessary to
In the register of Cache way states of the shared L1 Cache of these threads is recorded, by each thread pair in L1 Cache
Cache way belonging to the generation Cache that answers abnormal Cache line be all recorded as it is unavailable, by each line in L1 Cache
The corresponding disabled Cache way of journey are closed.
Fig. 5 is the register of the Cache way states of the shared L1 Cache of two threads of record in the embodiment of the present invention
Schematic diagram；It is assumed that one of core of CPU runs 2 threads, 8 Cache way of L1 Cache are shared.Shown in Fig. 5
The shared L1 Cache of two threads of record Cache way states register in, Bit 0-Bit 7 indicate thread 1 to be total to
Whether 8 Cache way of the L1 Cache for enjoying can use, and Bit 8-Bit 15 indicate 8 of the shared L1 Cache of thread 2
Whether Cache way can use.
Fig. 6 records unavailable for the register of the Cache way states of the shared L1 Cache of two threads of record in Fig. 5
The schematic diagram of Cache way；Communication equipment detect Cache it is abnormal when, read the register and L2 Cache of L1 Cache
Register, the instruction and data that L1 Cache and L2 Cache are stored writes internal memory, according to the deposit of the L1 Cache for reading
The register of device and L2 Cache, detects and the Cache way that the abnormal Cache line of Cache are located at L1 Cache occurs
0, and determine there be available Cache way in L1 Cache, the Bit 0 of the Cache way 0 used instruction thread 1 is carried out
OR operation, " 1 " is revised as by the initial value of Bit 0 from " 0 ", and the Bit 8 of the Cache way 0 to indicating thread 2 to use enters
Row OR operation, " 1 " is revised as by the initial value of Bit 8 from " 0 ", so, the L1 Cache that record thread 1 and thread 2 are shared
Cache way 0 for unavailable；Communication equipment closes the Cache way 0 of thread 1 and the shared L1 Cache of thread 2.
In other embodiments of the invention, when communication equipment detects Cache exceptions, the register of L1 Cache is read
With the register of L2 Cache, according to the register and the register of L2 Cache of the L1 Cache for reading, generation is detected
Cache way belonging to Cache abnormal Cache line are located at one of Bank of L2 Cache, if detecting generation
Also there is available Cache way in the Bank where Cache way belonging to Cache abnormal Cache line, then close hair
Cache way belonging to raw Cache abnormal Cache line, others can during communication equipment can be continuing with this Bank
Cache way, reduce the influence to business；If this Bank does not have available Cache way, it is not necessary to perform pass again
This operation that Cache way belonging to abnormal Cache line of Cache occur is closed, communication equipment can be directly restarted.
Fig. 7 is the schematic diagram of the register of the Cache way states of record L2 Cache in the embodiment of the present invention.It is assumed that
The L2 Cache of communication equipment include 2 Bank：Bank 0 and Bank 1；Bank 0 and Bank 1 each includes 8 Cache
way.In the register of the Cache way states of the record L2 Cache shown in Fig. 7, the initial value of Bit 0-Bit 7 can quilt
" 0 " is set to, the Cache way 0-Cache way 7 for indicating Bank 0 can use, and the initial value of Bit 8-Bit 15 can
It is arranged to " 0 ", the Cache way0-Cache way 7 for indicating Bank 1 can use.
Fig. 8 is that the register of the Cache way states of record L2 Cache in Fig. 7 records showing for unavailable Cache way
It is intended to；When communication equipment detects Cache exceptions, the register of L1 Cache and the register of L2 Cache are read, by L1
The instruction and data of Cache and L2 Cache storages writes internal memory, the register and L2 Cache according to the L1Cache for reading
Register, detects the Cache way 0 that the Bank 0 that the abnormal Cache line of Cache are located at L2Cache occurs, and determine
There are available Cache way in the Bank 0 of L2 Cache, to the register middle finger of the Cache way states of record L2 Cache
Showing the Bit 0 of the Cache way 0 of Bank 0 carries out OR operation, and the initial value of Bit 0 is revised as " 1 " from " 0 ", indicates L2
The Cache way 0 of the Bank 0 of Cache are unavailable；Communication equipment closes the Cache way 0 of the Bank 0 of L2 Cache.
Fig. 9 is that the register of the Cache way states of record L2 Cache in Fig. 7 and Fig. 8 records unavailable Cache way
Schematic diagram；When communication equipment detects Cache exceptions, the register of L1 Cache and the register of L2 Cache are read, will
The instruction and data write-in internal memory of L1 Cache and L2 Cache storages, according to the register and L2 of the L1 Cache for reading
The register of Cache, detects the Cache way that the Bank 1 that the abnormal Cache line of Cache are located at L2 Cache occurs
3, and determine there be available Cache way in the Bank 1 of L2 Cache, to posting for the Cache way states of record L2 Cache
Bit 11 carries out OR operation in storage, and the initial value of Bit 11 is revised as " 1 " from " 0 ", indicates the Bank 1 of L2 Cache
Cache way 3 for unavailable；Communication equipment closes the Cache way 3 of the Bank 1 of L2 Cache.
It is assumed that communication equipment has had been switched off 7 Cache way of the Bank 0 of L2 Cache, generation is detected again
Cache abnormal Cache line are located at a Cache way of the Bank 0 of L2 Cache, by L1Cache and L2 Cache
After the instruction and data write-in internal memory of storage, determine that the Bank 0 of L2 Cache without available Cache way, then carries out weight
Open, communication equipment need not the whole Cache way that have recorded the Bank0 of L2 Cache all set it is unavailable after restart again.
In other embodiments of the invention, communication equipment can posting according to the Cache way states of record L2 Cache
Numerical value is the number of the Bit of " 0 " in storage, determines whether each Bank of L2 Cache also has available Cache way, or
Person, communication equipment can be the number of the Bit of " 1 " according to numerical value in the register of the Cache way states of record L2 Cache, really
Whether each Bank for determining L2 Cache also has available Cache way.
For example, communication equipment reads from the Bit-0-Bit7 of the register of the Cache way states of record L2 Cache
Numerical value is 1 for the number of the Bit of " 0 ", it is determined that the current Cache line that Cache exceptions occur are located at L2 Cache's
The unique available Cache way of Bank 0, the Bank 0 of L2 Cache is without available Cache way.Or, communication equipment from
The number that the Bit0-Bit7 of the register of the Cache way states of record L2 Cache reads the Bit that numerical value is " 1 " is 7
It is individual, it is determined that current that the unique available Cache that the abnormal Cache line of Cache are located at the Bank 0 of L2 Cache occurs
The Bank 0 of way, L2 Cache is without available Cache way.
Likewise, communication equipment is read from the Bit-8-Bit 15 of the register of the Cache way states of record L2 Cache
The number for getting the Bit that numerical value is " 0 " is 1, it is determined that the current Cache line that Cache exceptions occur are located at L2 Cache
Bank 1 unique available Cache way, L2 Cache Bank 1 without available Cache way.Or, communication equipment
The number of the Bit that numerical value is " 1 " is read from the Bit8-Bit 15 of the register of the Cache way states of record L2 Cache
It it is 7, it is determined that current that the unique available Cache of Bank 1 that the abnormal Cache line of Cache are located at L2 Cache occur
The Bank 1 of way, L2 Cache is without available Cache way.
Using above-described embodiment, communication equipment detects Cache exceptions, L1 Cache or L2 Cache Bank also
When having available Cache way, first there is the abnormal Cache way of Cache in record, turns off and the abnormal Cache of Cache occur
Way, is continuing with the available Cache way in the Bank of L1 Cache or L2 Cache, reduce communication equipment due to
The Cache abnormal number of times restarted, improves the stability of communication equipment, reduces the influence to message forwarding service.
With reference to Figure 10, Figure 10 is a kind of structural representation of the abnormal processing units of Cache provided in an embodiment of the present invention,
The device includes：
Detection module 1001, for detecting cache exception；
Read module 1002, for when detecting cache and being abnormal, reading the register and two of on-chip cache
The register of level cache；
Identification module 1003, for the deposit of register and second level cache according to the on-chip cache for reading
Device, identification produces the abnormal abnormal cache line of cache；
Control module 1004, for determining that the cache way belonging to abnormal cache line is located at on-chip cache,
The register of the cache line state according to record on-chip cache, judges whether on-chip cache also has available height
Fast cache way；If it is, in the register of the cache line state of record on-chip cache, recording exceptional cache
Cache way belonging to row is unavailable, closes the cache way belonging to abnormal cache line；If not, execution is restarted.
In other embodiments of the invention, control module 1004, can be also used for：
It is determined that the cache way belonging to abnormal cache line is located at on-chip cache and is shared by multiple threads, root
According to the register of the cache line state of the shared on-chip cache of the multiple threads of record, whether on-chip cache is judged
Also available cache way；If it is, in the cache line state of the shared on-chip cache of the multiple threads of record
Register in, the cache way belonging to abnormal cache line that each thread is used is recorded as unavailable；Close quilt
Cache way belonging to the shared abnormal cache line of multiple threads；If not, execution is restarted.
In other embodiments of the invention, control module 1004, can be also used for：
It is determined that the cache way belonging to abnormal cache line is located at one of memory cell of second level cache,
The register of the cache line state of each memory cell according to record second level cache, judges abnormal cache line
Whether the memory cell that affiliated cache way is located at also has available cache way；If it is, recording two grades of high speeds
In the register of the cache line state of each memory cell of caching, the cache belonging to recording exceptional cache line
Road is unavailable；Close the cache way belonging to abnormal cache line；If not, execution is restarted.
In other embodiments of the invention, control module 1004, can be also used for：
The data and instruction that are stored in on-chip cache and second level cache are recorded in internal memory by memory module.
Using above-described embodiment, communication equipment detects Cache exceptions, L1 Cache or L2 Cache Bank also
When having available Cache way, first there is the abnormal Cache way of Cache in record, turns off and the abnormal Cache of Cache occur
Way, is continuing with the available Cache way in the Bank of L1 Cache or L2 Cache, reduce communication equipment due to
The Cache abnormal number of times restarted, improves the stability of communication equipment, reduces the influence to message forwarding service.
It should be noted that herein, such as first and second or the like relational terms are used merely to a reality
Body or operation make a distinction with another entity or operation, and not necessarily require or imply these entities or deposited between operating
In any this actual relation or order.And, term " including ", "comprising" or its any other variant be intended to
Nonexcludability is included, so that process, method, article or equipment including a series of key elements not only will including those
Element, but also other key elements including being not expressly set out, or also include being this process, method, article or equipment
Intrinsic key element.In the absence of more restrictions, the key element limited by sentence "including a ...", it is not excluded that
Also there is other identical element in process, method, article or equipment including the key element.
Each embodiment in this specification is described by the way of correlation, identical similar portion between each embodiment
Divide mutually referring to what each embodiment was stressed is the difference with other embodiment.Especially for system reality
Apply for example, because it is substantially similar to embodiment of the method, so description is fairly simple, related part is referring to embodiment of the method
Part explanation.
Presently preferred embodiments of the present invention is the foregoing is only, is not intended to limit the scope of the present invention.It is all
Any modification, equivalent substitution and improvements made within the spirit and principles in the present invention etc., are all contained in protection scope of the present invention
It is interior.
Claims (8)
1. the abnormal processing method of a kind of cache, it is characterised in that methods described includes：
Cache exception is detected, the register of on-chip cache and the register of second level cache is read；
According to the register and the register of the second level cache of the on-chip cache for reading, identification produces described
The abnormal abnormal cache line of cache；
Determine that cache way belonging to the abnormal cache line is located at the on-chip cache, according to recording described one
The register of the cache line state of level cache, judges whether the on-chip cache also has available cache
Road；
If it is, in the register of the cache line state of the record on-chip cache, recording the abnormal high speed
Cache way belonging to cache lines is unavailable, closes the cache way belonging to the abnormal cache line；
If not, execution is restarted.
2. method according to claim 1, it is characterised in that methods described also includes：
Determine that the cache way belonging to the abnormal cache line is located at the on-chip cache and is total to by multiple threads
Enjoy, according to the register of the cache line state for recording the shared on-chip cache of the multiple thread, judge institute
State whether on-chip cache also has available cache way；
If it is, in the register of the cache line state of the shared on-chip cache of the multiple threads of the record, will
The cache way belonging to described abnormal cache line that each thread is used is recorded as unavailable；Close by the multiple line
Cache way belonging to the shared described abnormal cache line of journey；
If not, execution is restarted.
3. method according to claim 2, it is characterised in that methods described also includes：
Determine that the cache way belonging to the abnormal cache line is located at one of storage of the second level cache
Unit, the register of the cache line state according to each memory cell for recording the second level cache judges described
Whether the memory cell that the cache way belonging to abnormal cache line is located at also has available cache way；
If it is, in the register of the cache line state of each memory cell of the record second level cache, note
The cache way recorded belonging to the abnormal cache line is unavailable；The high speed belonging to the abnormal cache line is closed to delay
Deposit road；
If not, execution is restarted.
4. method according to claim 1, it is characterised in that identification produce the cache it is abnormal it is abnormal at a high speed
After cache lines, methods described also includes：
The data and instruction that are stored in the on-chip cache and the second level cache are recorded in internal memory.
5. the abnormal processing unit of a kind of cache, it is characterised in that described device includes：
Detection module, for detecting cache exception；
Read module, register and two grades of high speeds for when detecting cache and being abnormal, reading on-chip cache delay
The register deposited；
Identification module, for the deposit of register and the second level cache according to the on-chip cache for reading
Device, identification produces the abnormal abnormal cache line of the cache；
Control module, for determining that the cache way belonging to the abnormal cache line is located at the on-chip cache,
According to the register of the cache line state for recording the on-chip cache, judge whether the on-chip cache also has
Available cache way；If it is, in the register of the cache line state of the record on-chip cache, record
Cache way belonging to the abnormal cache line is unavailable, closes the cache belonging to the abnormal cache line
Road；If not, execution is restarted.
6. device according to claim 5, it is characterised in that the control module, is additionally operable to：
Determine that the cache way belonging to the abnormal cache line is located at the on-chip cache and is total to by multiple threads
Enjoy, according to the register of the cache line state for recording the shared on-chip cache of the multiple thread, judge institute
State whether on-chip cache also has available cache way；If it is, high in the shared one-level of the multiple threads of the record
In the register of the cache line state of speed caching, the high speed belonging to described abnormal cache line that each thread is used
Cache way is recorded as unavailable；The cache belonging to described abnormal cache line that closing is shared by the multiple thread
Road；If not, execution is restarted.
7. device according to claim 5, it is characterised in that the control module, is additionally operable to：
Determine that the cache way belonging to the abnormal cache line is located at one of storage of the second level cache
Unit, the register of the cache line state according to each memory cell for recording the second level cache judges described
Whether the memory cell that the cache way belonging to abnormal cache line is located at also has available cache way；If it is,
In the register of the cache line state of each memory cell of the record second level cache, the exception is recorded high
Cache way belonging to fast cache lines is unavailable；Close the cache way belonging to the abnormal cache line；If not,
Execution is restarted.
8. device according to claim 5, it is characterised in that described device also includes：
Memory module, the data and instruction that are stored in the on-chip cache and the second level cache is recorded in interior
Deposit.
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| CN1979451A (en) * | 2005-12-08 | 2007-06-13 | 国际商业机器公司 | Methods and apparatus for handling a cache miss |
| CN102929796A (en) * | 2012-06-01 | 2013-02-13 | 杭州中天微系统有限公司 | Memory management module simultaneously supporting software backfilling and hardware backfilling |
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| US6038693A (en) * | 1998-09-23 | 2000-03-14 | Intel Corporation | Error correction scheme for an integrated L2 cache |
| CN1518700A (en) * | 2001-06-22 | 2004-08-04 | 皇家菲利浦电子有限公司 | Fast and acurate cache way selection |
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