CN106847145B - Array substrate test circuit and array substrate - Google Patents
Array substrate test circuit and array substrate Download PDFInfo
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- CN106847145B CN106847145B CN201710241348.3A CN201710241348A CN106847145B CN 106847145 B CN106847145 B CN 106847145B CN 201710241348 A CN201710241348 A CN 201710241348A CN 106847145 B CN106847145 B CN 106847145B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/006—Electronic inspection or testing of displays and display drivers, e.g. of LED or LCD displays
Abstract
The embodiment of the invention provides an array substrate test circuit, which comprises a test unit and a plurality of switching control units, wherein the test unit comprises a source signal source, a plurality of first switch units and a plurality of sub-pixels which correspond to the first switch units one by one, each sub-pixel is connected to the source signal source through one first switch unit, the source signal source and the switching control units are arranged along a first direction, the switching control units correspond to the first switch units one by one, and the switching control units control the corresponding first switch units to be conducted so that the source signal is transmitted to the corresponding sub-pixels. The arrangement of the test circuit can fully utilize the space of the array substrate in the length direction, so that the test circuit can save the space, and the test circuit can adapt to the design requirement of the array substrate with narrow frames.
Description
Technical Field
The invention relates to the field of test equipment, in particular to an array substrate test circuit and an array substrate.
Background
With the continuous development of LCD (Liquid Crystal Display) Display technology, LTPS (low temperature polysilicon) process panels are considered to be one of the mainstream Display technologies with the most development prospects in the high-end application market in the world. However, the array process in the LTPS process panel is complex, which results in low product yield and large gap in the shipping requirements. The Array Tester (ATS) can monitor the LTPS process and feed back to the production line to achieve the purpose of increasing the yield. Most products will be subjected to ATS inspection.
In the prior art, ATS inspection is mainly performed by a Full-Pin Contact Probing (FULL-Pin Contact Probing) method. Referring to fig. 1, the testing circuit in the prior art mainly includes a sub-pixel 31, a source signal source 32, a switch control circuit 33 and a switch 34. The switch control circuit 33 controls the conduction of the switch 34 to control the source signal to reach the sub-pixel 31, thereby performing the test. The ATS test circuit has the disadvantage that the circuit occupies the frame space of the panel, which affects the design architecture of the product. Especially, the frame of a narrow-frame product is small, so that a test circuit required by a test cannot be placed, and the phenomenon that the manufacturing process cannot be monitored is caused.
Disclosure of Invention
The invention aims to provide an array substrate test circuit, which can make full use of the space of the array substrate in the length direction due to the arrangement of the test circuit, so that the test circuit can meet the design requirement of a narrow-frame array substrate.
Another object of the present invention is to provide an array substrate using the above test circuit.
In order to achieve the above object, the embodiments of the present invention provide the following technical solutions:
the invention provides an array substrate test circuit which comprises a test unit and a plurality of switching control units, wherein the test unit comprises a source electrode signal source, a plurality of first switch units and a plurality of sub-pixels corresponding to the first switch units one by one, each sub-pixel is connected to the source electrode signal source through one first switch unit, the source electrode signal source and the switching control units are arranged along a first direction, the switching control units and the first switch units correspond one by one, and the switching control units control the corresponding first switch units to be conducted so that the source electrode signals are transmitted to the corresponding sub-pixels.
The switching control unit controls the conduction of the corresponding first switch unit in each test unit, so that a source signal in each test unit is transmitted to the corresponding sub-pixel.
The source signal sources in the test units are sequentially arranged along the first direction.
The plurality of switching control units are uniformly distributed in the plurality of source signal sources.
The array substrate test circuit further comprises a switch circuit, the test unit further comprises a second switch unit, the second switch unit is connected between the source signal source and the first switch unit, and the switch circuit controls the conduction of the second switch unit so that the source signal is transmitted to the first switch unit.
The invention also provides an array substrate, which comprises a test circuit, wherein the test circuit comprises a test unit and a plurality of switching control units, the test unit comprises a source signal source, a plurality of first switch units and a plurality of sub-pixels, each sub-pixel is connected to the source signal source through one first switch unit, the source signal source and the plurality of switching control units are arranged along a first direction, the plurality of switching control units, the plurality of first switch units and the plurality of sub-pixel electrodes are in one-to-one correspondence, and the switching control units control the corresponding first switch units to be conducted so that the source signal is transmitted to the corresponding sub-pixels.
The switching control unit controls the conduction of the corresponding first switch unit in each test unit, so that a source signal in each test unit is transmitted to the corresponding sub-pixel.
The source signal sources in the test units are sequentially arranged along the first direction.
The plurality of switching control units are uniformly distributed in the plurality of source signal sources.
The array substrate test circuit further comprises a switch circuit, the test unit further comprises a second switch unit, the second switch unit is connected between the source signal source and the first switch unit, and the switch circuit controls the conduction of the second switch unit so that the source signal is transmitted to the first switch unit.
The embodiment of the invention has the following advantages or beneficial effects:
in the embodiment of the invention, a source signal source S, the first switch units (Q1-Qn) and the sub-pixels are sequentially connected, the source signal source S is arranged along a first direction with the plurality of switch control units (sw1-swn), the plurality of switch control units (sw1-swn), the plurality of first switch units (Q1-Qn) and the plurality of sub-pixel electrodes 21 are in one-to-one correspondence, so that the sub-pixels are tested, the arrangement of the Test circuit can fully utilize the space in the length direction of the Array Test area 11, the space in the width direction of the Array Test area 11 can be saved, and the Test circuit can meet the design requirement of the narrow-frame Array substrate.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments of the present invention, and for those skilled in the art, other drawings can be obtained according to the drawings without creative efforts.
Fig. 1 is a schematic diagram of a test circuit structure of a prior art array substrate.
Fig. 2 is a schematic view of the structure of the array substrate according to the present invention.
Fig. 3 is a schematic structural diagram of a test circuit in the array substrate shown in fig. 2.
Fig. 4 is another schematic structural diagram of a test circuit in the array substrate shown in fig. 2.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Furthermore, the following description of the various embodiments refers to the accompanying drawings, which illustrate specific embodiments in which the invention may be practiced. Directional phrases used in this disclosure, such as, for example, "upper," "lower," "front," "rear," "left," "right," "inner," "outer," "side," and the like, refer only to the orientation of the appended drawings and are, therefore, used herein for better and clearer illustration and understanding of the invention, and do not indicate or imply that the device or element so referred to must have a particular orientation, be constructed and operated in a particular orientation, and are therefore not to be considered limiting of the invention.
In the description of the present invention, it should be noted that, unless otherwise explicitly specified or limited, the terms "mounted," "connected," and "connected" are to be construed broadly, e.g., as being fixedly connected, detachably connected, or integrally connected; may be a mechanical connection; they may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meanings of the above terms in the present invention can be understood in specific cases to those skilled in the art.
In addition, in the description of the present invention, "a plurality" means two or more unless otherwise specified. In the present specification, the term "step" is used to mean not only an independent step but also an independent step unless clearly distinguished from other steps, as long as the intended function of the step is achieved. In the present specification, the numerical range represented by "to" means a range including numerical values before and after "to" as a minimum value and a maximum value, respectively. In the drawings, structures that are similar or identical are denoted by the same reference numerals.
Please refer to fig. 2. Fig. 2 is a schematic structural diagram of an array substrate according to the present invention. The array substrate of the present invention includes: a Test circuit area 11 (also called Array Test area), a display area 12(AA area), a goa (gate On Array) area 13, a multiplexer selector (Demux) area 14, a fan-out (Fanout) area 15, a woa (wire On Array) area 16, a driver chip (IC) area 17, and a flexible connector (FPC) area 18. The Array Test area 11 is used for testing the electrical property of an Array (Array) substrate after the Array substrate is manufactured, and the Array substrate Test circuit is positioned in the Array Test area 11 except for the sub-pixels; the AA area 12 includes a plurality of pixel units, each pixel unit includes a red sub-pixel, a blue sub-pixel, and a green sub-pixel, and the AA area is used for displaying the pixels; a GOA region 13 for generating gate driving signals of the TFTs in the display region; a Fanout area 15 for realizing the routing connection between the IC and the data line in the AA area; a Demux area 14 for splitting an output end led out from an IC side to realize driving of a plurality of datalines; a WOA area 16 for connection of traces around the panel; an IC area 17 for Bonding (Bonding) of an IC, the driving chip for providing a data signal of the AA area; an FPC area 18 for Bonding of FPC through which the circuit board is connected. The test circuit area 11 is connected to the IC area 17 through a connection line to provide a test control signal (ATEN) to the test circuit, and specifically, when the test circuit operates, the test control signal is at a high level, and after the test of the test circuit is completed, the test control signal is at a low level, that is, the test circuit is turned off, so that the test circuit is prevented from displaying an influence on the AA area.
Please refer to fig. 3. Fig. 3 is a schematic structural diagram of a test circuit in the array substrate shown in fig. 2. The array substrate test circuit of the present invention includes a test unit 20 and a plurality of switching control units (i.e., sw1-swn in fig. 3). Specifically, the test unit 20 includes a source signal source S, a plurality of first switching units (i.e., Q1-Qn in fig. 2), and a plurality of sub-pixels 21. Each of the sub-pixels 21 is connected to the source signal source S through one of the first switch units, and the source signal source S is used for providing a source signal required by a test. The source signal source S, the first switching unit (Q1-Qn) and the sub-pixel 21 are connected in sequence substantially along a trend of the second direction (i.e., the Y direction in fig. 1 and 2). It is understood that the second direction is substantially a width direction of the Array Test area 11. The source signal source S and the plurality of switching control units (Q1-Qn) are arranged in a first direction (i.e., X direction in fig. 1 and 2). It is understood that the first direction is substantially a length direction of the Array Test area 11. The plurality of switching control units (sw1-swn), the plurality of first switch units (Q1-Qn) and the plurality of sub-pixel electrodes 21 are in one-to-one correspondence, and each switching control unit controls the on or off of one first switch unit, so that whether a signal sent by the source signal source S reaches the corresponding sub-pixel is controlled, and the test process of the sub-pixel is completed.
It is understood that, in other embodiments, the first direction X may also be other directions that are not parallel to the second direction Y.
It is understood that n may be 1, 2, 3, 4, 5 … …, as described above
In the present embodiment, the source signal source S, the first switching unit (Q1-Qn) and the sub-pixel 21 are connected in this order substantially along the second direction trend; the source signal source S and the plurality of switching control units (sw1-swn) are arranged along a first direction (namely, the X direction in fig. 1 and 2), the plurality of switching control units (sw1-swn), the plurality of first switch units (Q1-Qn) and the plurality of sub-pixel electrodes 21 are in one-to-one correspondence, so that sub-pixel testing is realized, the arrangement of the Test circuit can fully utilize the space in the length direction of the Array Test region 11, the space occupying the width direction of the Array Test region 11 can be reduced, and the Test circuit can adapt to the design requirements of the narrow-frame Array substrate.
Please refer to fig. 4. Fig. 4 is another schematic structural diagram of a test circuit in the array substrate shown in fig. 2. In the present embodiment, the number of the test units 20 is plural. It is understood that the test unit 20 and the switching control unit in this embodiment have substantially the same structure as the test unit in the previous embodiment, and are not described herein again. In this embodiment, for convenience of representation, each test unit includes 6 first switch units (i.e., Q1-Q6) and 6 sub-pixels. Accordingly, in the present embodiment, the number of switching control units is also 6 (i.e., sw1-sw 6). In other embodiments, the number of the first switch units and the sub-pixels may also be 1, 2, 3, 4, 5, 7, 8, 9 … …, which is not limited herein.
In the present embodiment, the switch control unit sw1 controls the state (on/off) of the first switch unit Q1 in each test unit 20, that is, the control unit sw1 controls the states of the plurality of first switch units Q1 at the same time; the switching control unit sw2 controls the state (on/off) of the first switch unit Q2 in each test unit 20, that is, the switching control unit sw1 controls the states of the plurality of first switch units Q1 at the same time; by analogy, the switching control unit sw6 controls the state (on/off) of the first switch unit Q6 in each test unit 20. In other words, the plurality of switching control units correspond to the plurality of first switch units in each of the test units 20 one to one, and the switching control units control the corresponding first switch units in each of the test units 20 to be turned on, so that the source signals in each of the test units are transmitted to the corresponding sub-pixels.
In a possible implementation manner of the present invention, the plurality of Test units 20 are arranged along the first direction X, so as to reduce the space in the width direction (and the second direction Y) of the Array Test area 11 occupied by the Test circuit. Preferably, the plurality of source signal sources S are sequentially arranged along the first direction X.
It is understood that the plurality of test units 20 and the plurality of switching control units are arranged along the first direction X. Preferably, the plurality of switching control units are uniformly distributed in the plurality of source signal sources S. Generally, in the array substrate test circuit, the number of the test units 20 is much larger than that of the switching control units. Therefore, the plurality of switching control units may be uniformly distributed among the plurality of test units 20. Specifically, the plurality of test units 20 may be sequentially arranged in a straight line along the first direction X. In other words, the plurality of source signal sources S are arranged in a straight line along the first direction, the plurality of switching control units are inserted in the straight line formed by the plurality of source signal sources S, and the same number of test units 20 (source signal sources S) are spaced between two adjacent switching control units. The plurality of switching control units are arranged among the plurality of Test units 20 in a penetrating manner, so that connecting wires between the switching control units and the first switch units can be distributed in the routing of the source signal source in a penetrating manner, the wiring is more compact, and the occupation of the space of the Array Test area 11, especially the space in the width direction, is reduced. In addition, the plurality of switching control units are uniformly distributed in the plurality of source signal sources S, so that the average distances between the switching control units and the test unit 20 are substantially the same as much as possible, and the switching signal delay received by the test unit at a part of positions due to excessive concentration of the plurality of switching control units is avoided, thereby affecting the accuracy of the test result.
In a possible implementation manner of the present invention, the array substrate test circuit further includes a switch circuit (not shown in the figure), the test unit further includes a second switch unit 22, the second switch unit 22 is connected between the source signal source S and the first switch unit, and the switch circuit controls the conduction of the second switch unit 22, so that the source signal is transmitted to the first switch unit. Thereby controlling the on-off of the source signal.
In the description herein, references to the description of the term "one embodiment," "some embodiments," "an example," "a specific example" or "some examples" or the like are intended to mean that a particular feature, structure, material, or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the invention. In this specification, the schematic representations of the terms used above do not necessarily refer to the same embodiment or example. Furthermore, the particular features, structures, materials, or characteristics described may be combined in any suitable manner in any one or more embodiments or examples.
The above-described embodiments do not limit the scope of the present invention. Any modification, equivalent replacement, and improvement made within the spirit and principle of the above-described embodiments should be included in the protection scope of the technical solution.
Claims (10)
1. An array substrate test circuit is characterized by comprising a plurality of test units and a plurality of switching control units, wherein each test unit comprises a source electrode signal source, a plurality of first switch units and a plurality of sub-pixels which are in one-to-one correspondence with the first switch units, each sub-pixel is connected to the source electrode signal source through one corresponding first switch unit, the source electrode signal source is used for providing a source electrode signal required by a test, the source electrode signal sources and the switching control units are arranged along a first direction, the source electrode signal sources, the first switch units and the sub-pixels are sequentially connected along a second direction, the switching control units are uniformly distributed among the test units, the test units are sequentially arranged along the first direction to form a straight line, the source electrode signal sources are sequentially arranged along the first direction to form a straight line, the switching control units are inserted in a straight line formed by the source signal sources, and the testing units with the same number are arranged between every two adjacent switching control units; the switching control units control the conduction of the corresponding first switch units so that source signals sent by the source signal source are transmitted to the corresponding sub-pixels, wherein the first direction is the length direction of an array test area of the array substrate, and the second direction is the width direction of the array test area.
2. The array substrate test circuit of claim 1, wherein the plurality of switching control units are in one-to-one correspondence with the plurality of first switch units in each test unit, and the switching control unit controls the corresponding first switch unit in each test unit to be turned on, so that the source signal in each test unit is transmitted to the corresponding sub-pixel.
3. The array substrate test circuit of claim 2, wherein the plurality of source signal sources in the plurality of test units are sequentially arranged along the first direction.
4. The array substrate test circuit of claim 3, wherein the plurality of switching control units are evenly distributed among the plurality of source signal sources.
5. The array substrate test circuit of claim 3, wherein the array substrate test circuit further comprises a switch circuit, the test unit further comprises a second switch unit, the second switch unit is connected between the source signal source and the first switch unit, and the switch circuit controls the second switch unit to be turned on so that the source signal is transmitted to the first switch unit.
6. An array substrate is characterized by comprising a test circuit, wherein the test circuit comprises a plurality of test units and a plurality of switching control units, each test unit comprises a source signal source, a plurality of first switch units and a plurality of sub-pixels, each sub-pixel is connected to the source signal source through one corresponding first switch unit, the source signal sources are used for providing source signals required by testing, the source signal sources and the plurality of switching control units are arranged along a first direction, the source signal sources, the plurality of first switch units and the plurality of sub-pixels are sequentially connected along a second direction, the plurality of switching control units are uniformly distributed among the plurality of test units, the plurality of test units are sequentially arranged along the first direction to form a straight line, the plurality of source signal sources are sequentially arranged along the first direction to form a straight line, the switching control units are inserted in a straight line formed by the source signal sources, and the testing units with the same number are arranged between every two adjacent switching control units; the switching control units control the conduction of the corresponding first switch units so that source signals sent by the source signal source are transmitted to the corresponding sub-pixels, wherein the first direction is the length direction of an array test area of the array substrate, and the second direction is the width direction of the array test area.
7. The array substrate of claim 6, wherein the plurality of switching control units correspond to the plurality of first switch units in each of the test units one to one, and the switching control units control the corresponding first switch units in each of the test units to be turned on, so that the source signals in each of the test units are transmitted to the corresponding sub-pixels.
8. The array substrate of claim 7, wherein the plurality of source signal sources in the plurality of test units are sequentially arranged along the first direction.
9. The array substrate of claim 8, wherein the plurality of switching control units are uniformly distributed among the plurality of source signal sources.
10. The array substrate of claim 9, wherein the array substrate test circuit further comprises a switch circuit, the test unit further comprises a second switch unit connected between the source signal source and the first switch unit, and the switch circuit controls the second switch unit to be turned on so that the source signal is transmitted to the first switch unit.
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Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN107680521B (en) * | 2017-09-28 | 2020-11-27 | 武汉华星光电技术有限公司 | Detection circuit based on array substrate and display device |
| CN107578735A (en) * | 2017-10-31 | 2018-01-12 | 武汉华星光电技术有限公司 | A kind of array base palte, method of testing and display device |
| US10777107B2 (en) * | 2017-10-31 | 2020-09-15 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Array substrate, testing method and display apparatus |
| US10782335B2 (en) | 2017-11-06 | 2020-09-22 | Wuhan China Star Optoelectronics Technology Co., Ltd. | Backlight test circuit, backlight test method and backlight module using the same |
| CN107784968A (en) * | 2017-11-06 | 2018-03-09 | 武汉华星光电技术有限公司 | Carry on the back optical detection circuit and Related product |
| CN109491154A (en) * | 2018-12-29 | 2019-03-19 | 厦门天马微电子有限公司 | Display panel, display device and its manufacturing method |
| CN113763848A (en) * | 2020-06-04 | 2021-12-07 | 群创光电股份有限公司 | Display panel |
| CN113658540A (en) * | 2021-08-24 | 2021-11-16 | 武汉华星光电半导体显示技术有限公司 | Display panel and display device |
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