CN106844248A - The method and system of data transfer - Google Patents
The method and system of data transfer Download PDFInfo
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- CN106844248A CN106844248A CN201710082710.7A CN201710082710A CN106844248A CN 106844248 A CN106844248 A CN 106844248A CN 201710082710 A CN201710082710 A CN 201710082710A CN 106844248 A CN106844248 A CN 106844248A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/14—Handling requests for interconnection or transfer
- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
- G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/063—Address space extension for I/O modules, e.g. memory mapped I/O
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0646—Configuration or reconfiguration
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Abstract
The invention discloses a kind of data transmission method and system, it is applied to I/O equipment and main frame is sent data to by DMA.The method includes：Index quantity S/P is calculated according to preset buffer memory size S and average data packet length P, then the size U according to indexing units calculates the size I=of index memory block（S / P）× U, and index memory block according to this size application；Quantity N=S/the M of the datarams block for needing distribution is calculated according to the size of memory block M according to default cache size S and per block number, and applies N block numbers according to memory block according to preset data block size M；Start physical address, the start physical address of length and all of datarams block and the size of data memory block that memory block will be indexed are written to I/O equipment；Control I/O equipment passes through DMA transfer upstream data；Main frame reads index information and obtains upstream data bag content according to the record of indexing units.The present invention can improve the success rate of the memory source application of host computer system and can effectively utilize less contiguous memory block, to provide more host memory resources for I/O equipment.
Description
Technical field
The present invention relates to field of data transmission, and in particular to towards the Data Transmission Controlling of the I/O equipment such as PCIE, mainly
The method and system of memory source allocation manager and data transfer are provided for the DMA transfer of the I/O equipment such as PCIE.
Background technology
I/O equipment generally uses direct memory access (Direct Memory Access, letter when carrying out data transmission
Claim DMA) data in technical transmission I/O equipment, so as to be achieved independently of the backstage bulk data transfer of CPU.In dma operation
In, main frame is that dma operation distributes DMA memory address spaces, and I/O equipment is directly read in the enterprising row data of DMA memory address spaces
Write, so as to complete dma mode data transfer.Dma operation realizes that I/O equipment sends DMA messages to main frame by DMA messages,
DMA address is included in DMA messages, DMA address is located on the DMA memory address spaces that main frame is distributed by dma operation.Pass through
DMA address in DMA messages, I/O equipment directly can be written and read to the data on the DMA memory address spaces of main frame, tool
Body, for example, when main frame carries out write operation to I/O equipment, DMA messages are the text of reading the newspaper to internal memory, and data are by the reading
One or more completion order bags that message is responded are carried, from memory copying to I/O equipment；When main frame enters to I/O equipment
During row read operation, the size of data for copying as needed, the DMA messages of I/O equipment generation write message for one or more, report
Text carries the data of copy, writes the DMA memory address spaces that message reaches destination host, and the data load in message is copied to
In corresponding memory headroom.Because in dma operation, the process of data transfer is participated in without host CPU, it is achieved thereby that I/
High-speed read-write of the O device to host data independence.
With continuing to develop for computer technology, bandwidth needed for various computer PCI E equipment is also increasing, corresponding
PCIE device is also required to distribute bigger up-downgoing data buffer storage in main frame.And conventional main frame is distributing up DMA cachings
When be usually that one piece of application or two pieces of larger contiguous memorys carry out data buffer storage, but as required caching is increasing,
Conventional method the drawbacks of it is also more and more obvious：
Drawback 1：Larger contiguous memory application chance of success is low, once system cannot provide expected contiguous memory resource, that
Size continuation application can only be reduced until applying successfully, so cannot usually obtain being expected cache size；
Drawback 2：Host computer system memory source is underutilized, since it is desired that the relatively large contiguous memory of application, so being
Less contiguous memory block in system cannot be used, even if having enough memory sources in may so causing system, but
Also a portion can only be used by corresponding PCIE device.
The content of the invention
In view of above-mentioned the deficiencies in the prior art, the present invention proposes a kind of for being carried out between I/O equipment and host device
The method and data transmission system of DMA data transfer, to improve the success rate of the memory source application of host computer system and can have
Effect is using less contiguous memory block to provide more host memory resources for I/O equipment.
According to an aspect of the invention, there is provided a kind of data transmission method, methods described is applied to I/O equipment and passes through
DMA sends data to main frame, and methods described includes：
Index quantity S/P is calculated according to preset buffer memory size S and average data packet length P, then according to indexing units
Size U calculate index memory block size I=（S / P）× U, and index memory block according to this size application；
The number of the datarams block for needing distribution is calculated according to the size of memory block M according to default cache size S and per block number
Amount N=S/M, and apply N block numbers according to memory block according to preset data block size M；
The start physical address and datarams of the start physical address, length and all of datarams block of memory block will be indexed
The size of block is written to I/O equipment；
Control I/O equipment passes through DMA transfer upstream data；
Main frame reads index information and obtains upstream data bag content according to the record of indexing units.
The indexing units include datarams block sequence number, packet original position where data packet length, packet
Offset address, indexing units significant notation, indexing units finish the information such as mark, wherein,
Data packet length is used for recording the length information of the corresponding packet of current indexing units；
Which data are datarams block sequence number where packet, be located in for recording the corresponding packet of current indexing units
In counterfoil；
The offset address of packet original position, the original position for recording the corresponding packet of current indexing units is deposited at it
The byte number that the start address of the datarams block put offsets backward；
Indexing units significant notation, for representing whether current indexing units are effective；
Indexing units finish mark, and whether the indexing units for representing next packet will start anew retrieval
In a kind of possible design, after the main frame obtains current indexing units corresponding packet, will currently index
It is invalid that unit significant notation is set to, when the I/O equipment is stored in new packet in datarams block, by current indexing units
Significant notation is set to effectively.
In a kind of possible design, when the significant notation that main frame checks indexing units to be read is asserted
When, i.e., the offset address for packaging beginning position according to the packet place datarams block sequence number and data that are recorded in indexing units exists
The position of corresponding data bag is found in datarams block, the data packet length for then being recorded according to indexing units obtains upper line number
According to bag.
In a kind of possible design, after the main frame obtains packet, the mark that finishes of indexing units is also checked for, if
The mark that finishes is effective, then it is invalid that the mark that will finish is set to, while the indexing units position for checking of host record is changed
It is first indexing units；If finishing marked invalid, the indexing units position for checking of host record is then changed
It is next indexing units.
According to another aspect of the present invention, there is provided a kind of data transmission system, the system include main frame and with master
The I/O equipment of machine connection, the I/O equipment sends data to main frame by DMA, and the main frame includes：
Index internal memory application unit, for according to preset buffer memory size S and average data packet length P calculate index quantity S/
P, then the size U according to indexing units calculate index memory block size I=（S / P）× U, and according to this size Shen
Please index memory block；
Datarams application unit, for calculating needs according to the size of memory block M according to default cache size S and per block number
Quantity N=S/the M of the datarams block of distribution, and apply N block numbers according to memory block according to preset data block size M；
Memory Allocation information transmitting unit, start physical address, length and all of datarams for memory block will to be indexed
The start physical address of block and the size of data memory block are written to I/O equipment；
Upstream data reading unit, for reading index information and obtaining upstream data bag content according to the record of indexing units.
The present invention because without once applying for relatively large continuous physical memory, in so every piece of continuous physical of main frame application
The successful probability of counterfoil will be greatly increased, so that the drawbacks of prior art preferably being solved, improves the internal memory money of host computer system
The success rate of source application simultaneously can effectively utilize less contiguous memory block, so as to for including the various I/ including such as PCIE device
O device provides more host memory resources.
Brief description of the drawings
Fig. 1 shows host memory resource map of the invention.
Fig. 2 shows upstream data bag filling flow chart of the invention.
Fig. 3 shows that host data bag of the invention receives flow chart.
Specific embodiment
Below in conjunction with the accompanying drawing in the embodiment of the present invention, the technical scheme in the embodiment of the present invention is carried out clear, complete
Site preparation is described, it is clear that described embodiment is only a part of embodiment of the invention, rather than whole embodiments.It is based on
Embodiment in the present invention, the every other implementation that those skilled in the art are obtained under the premise of creative work is not made
Example, belongs to the scope of protection of the invention.
Because the present invention is applied to carry out up DMA data transfer between I/O equipment and host device, for convenience to this
The understanding of invention, the flow to DMA write operation in the prior art is briefly described.DMA write operation can be realized data
In the DMA memory address for copying destination host to from I/O equipment, DMA write operation comprises the following steps：
1st, request is started according to the dma operation for receiving, I/O device driver softwares generate an I/O command bag, comprising DMA copies
Data in I/O equipment to internal memory command information, source data address and target memory DMA address on I/O device；
2nd, I/O device receives the order bag, and the size of data for copying as needed generates one or more DMA write message,
The destination address of message is internal memory DMA address, and message carries the data of copy；
3rd, DMA write message is sent to corresponding passage (generally PCIE links)；
4th, DMA write message reaches the physical memory space of main frame, and the data load in message is copied into corresponding target memory
On DMA address.
By the I/O equipment up DMA transfer of control in the present invention, main frame needs to apply for two kinds of physical memory blocks：1）For depositing
Store up a fritter continuous physical memory of packet description information（Hereinafter will be simply referred to as indexing memory block）；2）Polylith is used for storing
The multiple isometric continuous physical memory block message of upstream data bag（Hereinafter will be simply referred to as datarams block）.
These memory blocks are all little per block size, and it is 1MB or 2MB to recommend size according to memory block per block number；Index internal memory
Block size can be calculated according to the average data packet length of setting and data memory block total size, under normal circumstances also will not be too
Greatly.Because without once applying for relatively large continuous physical memory, so every piece of continuous physical memory block of main frame application into
The probability of work(will be greatly increased, and be used for the total size of the data storage area of data storage in datarams number of blocks × data
Counterfoil size.
, it is necessary to the start physical address and length that memory block and all datarams blocks will be indexed after memory source application is finished
Degree informs I/O equipment.When I/O equipment needs to transmit up DMA data, can be suitable according to the transmission of location information of the record of itself
Sequence will need the packet DMA for uploading in certain datarams block, and be filled out in the index record of newest index memory block
Write relevant information.
Main frame is to know the packet information being newly written by reading significant notation in index memory block, and according to
The positional information and length information of each latest data bag recorded in index memory block obtain the packet content being newly written.It is main
The internal memory application situation of machine is as shown in Figure 1.
Embodiment 1：
The present embodiment describes the workflow of data transmission method of the invention in detail, by I/O equipment（As PCIE hardware sets
It is standby）Up DMA transfer is controlled, when main frame load driver, is started working in accordance with the following steps：
1st step, index quantity is calculated according to preset buffer memory size S and average data packet length P, then according to indexing units
Size U calculates the size I of index memory block（I =（S / P）× U）, and apply indexing memory block first according to this size.
Datarams block sequence number, packet start bit where data packet length, packet are needed in each indexing units
The offset address put, indexing units significant notation, indexing units finish the information such as mark, and the effect of these information is as follows：
Data packet length：Record the length information of the corresponding packet of current indexing units；
Datarams block sequence number where packet：The corresponding packet of current indexing units is recorded positioned at which data memory block
In；
The offset address of packet original position：Record what the original position of the corresponding packet of current indexing units was deposited at it
The byte number that the start address of datarams block offsets backward；
Indexing units significant notation：Whether effectively the mark is used for representing current indexing units, when main frame obtains the Index List
After the corresponding packet of unit, it is invalid that this mark is set to；When PCIE device is stored in new packet in datarams block, by this
Mark is set to effectively；
Indexing units finish mark：When the packet of transmission has all write last block end than being so large that datarams block
Cannot again write new packet, but the indexing units in index memory block are when also having vacant, last effective Index List
The mark that finishes of unit is set to and effectively represents that the indexing units of next packet will start anew to retrieve.
2nd step, the data for calculating needs distribution according to the size of memory block M according to default cache size S and per block number
The quantity N of memory block, and apply N block numbers according to memory block according to preset data block size M（N = S / M）.
3rd step, will index memory block start physical address, length and all of datarams block start physical address
Be written to PCIE hardware devices with the size of data memory block, allow hardware device know upstream data by DMA where.
4th step, control PCIE hardware devices start to transmit upstream data.
When needing to carry out transmitting uplink data, PCIE hardware devices can since index memory block initial address according to
Order using each indexing units and can record currently used which indexing units arrived backward one by one；It is same for internal memory
Data block be also from the first BOB(beginning of block) in sequence one by one backward using and record currently used datarams block sequence number and
The data length filled.It should be noted that every piece of internal storage data block can fill many packets, including each packet
Be also in deposit data block since the initial address of internal storage data block order fill backward, only when an internal storage data block without
When method writes new packet, next internal storage data block can be just enabled；
Whenever having a upstream data bag to need transmission, PCIE hardware devices are first according to the currently used data of self record
The data length that the sequence number of memory block and the datarams block had been filled with is write the data packet in datarams block, Ran Hougen
Packet information is filled into newest indexing units according to the indexing units service condition of self record, finally by the indexing units
Significant notation be set to effectively.
5th step, main frame read index information and read upstream data bag content according to the record of indexing units.
Main frame can equally record the position of the indexing units for checking, when main frame checks indexing units to be read
When significant notation is asserted, i.e., datarams block sequence number and data are packaged according to where the packet recorded in indexing units
The beginning offset address of position finds the position of corresponding data bag in datarams block, the data for then being recorded according to indexing units
Packet length, you can access whole packet.After treatment full number is according to bag, main frame is needed the significant notation of indexing units
It is invalid to be set to；Now, the mark that finishes of inspection indexing units is also needed, if the mark that finishes is effective, then also need the mark that will finish
It is invalid to be set to, and the indexing units position for checking of host record needs to be changed to first indexing units；If finishing mark
Note is invalid, then the indexing units position for checking of host record is then changed to next indexing units.
The upstream data bag for describing PCIE hardware devices in detail referring to Fig. 2 fills flow：
Electricity on S201, PCIE hardware device；
S202, the length records clearing that currently used datarams block sequence number and data block are had been filled with data；
S203, currently used indexing units sequence number is recorded reset；
S204, main frame（That is host computer）The letter such as write-in index block address memory, length and multiple datarams block address, length
Breath；
Whether S205, PCIE device are waited needs transmission upstream data bag to main frame, if necessary to transmit, then into step 206,
Otherwise continue waiting for；
S206, PCIE device have been filled with the length of data according to the currently used datarams block sequence number and the data block of record
By packet DMA to specified physical memory, the destination address of DMA is for " current data memory block initial address+current data block is
Filling data length ", the data length of DMA is to need the upstream data bag of transmission long；
S207, the offset address of data packet length, datarams block sequence number where packet, packet original position is filled into
It is set to effectively in interim indexing units buffer structure and by significant notation；
The currently used datarams block of S208, renewal has been filled with data length record, and having been filled with length increases upstream data bag
Bag length；
S209, judge datarams block size subtract currently used datarams block have been filled with data length record whether be less than
Maximum bag length, if it is, going to step S210, otherwise goes to step S215；
S210, the length records clearing that datarams block is had been filled with data；
S211, judge whether currently used datarams block is last block, if it is, going to step S212, otherwise go to
Step S213；
S212, currently used datarams block sequence number is reset；
S213, currently used datarams block sequence number is added 1；
S214, mark that the indexing units of interim indexing units buffer structure finish are set to effectively；
S215, the physical address by the content DMA of interim indexing units buffer structure to currently used indexing units；
S216, judge whether currently used indexing units LSN is last indexing units, if it is, going to step
S217, otherwise goes to step S218；
S217, currently used indexing units sequence number is recorded reset, go to step 205；
S218, currently used indexing units sequence number is added 1, go to step 205.
Describe the idiographic flow of main frame reading DMA data in detail referring to Fig. 3：
S301, main frame prepare to start to receive upstream data；
S302, the indexing units sequence number of the current check of software records are entered as obtaining newest write-in rope from PCIE hardware devices
Draw unit number；
S303, main frame check that whether effectively current indexing units significant notation, if performing step S305, otherwise performs step
Rapid S304；
S304,1 millisecond of current receiving thread dormancy, go to step S303；
S305, according in indexing units record datarams block sequence number and skew, data packet length acquisition of information packet in
Hold；
The current indexing units of S306, main frame inspection finish and mark whether effectively, if performing step S309, otherwise to perform step
Rapid S307；
Whether the current indexing units of S307, main frame inspection are last, if performing step S309, otherwise perform step
S308；
S308, the indexing units sequence number of the current check of software records add 1, go to step S303；
S309, the indexing units sequence number of the current check of software records reset, and go to step S303.
Embodiment 2：
The present embodiment describes data transmission system of the invention, that includes main frame and the I/O equipment being connected with main frame.Its
In, the main frame includes：
Index internal memory application unit, for according to preset buffer memory size S and average data packet length P calculate index quantity S/
P, then the size U according to indexing units calculate index memory block size I=（S / P）× U, and according to this size Shen
Please index memory block；
Datarams application unit, for calculating needs according to the size of memory block M according to default cache size S and per block number
Quantity N=S/the M of the datarams block of distribution, and apply N block numbers according to memory block according to preset data block size M；
Memory Allocation information transmitting unit, start physical address, length and all of datarams for memory block will to be indexed
The start physical address of block and the size of data memory block are written to I/O equipment；
Upstream data reading unit, for reading index information and obtaining upstream data bag content according to the record of indexing units.
Data transmission method of the invention and system are described in detail above, those skilled in the art Ying Ming
In vain, embodiments of the invention can be provided as method, system or computer program product.Therefore, the present invention can use complete hardware
The form of the embodiment in terms of embodiment, complete software embodiment or combination software and hardware.And, the present invention can be used
One or more wherein include the computer-usable storage medium of computer usable program code, and (including but not limited to disk is deposited
Reservoir and optical memory etc.) on implement computer program product form.
The present invention is the flow with reference to method according to embodiments of the present invention, equipment (system) and computer program product
Figure and/or block diagram are described.It should be understood that every first-class during flow chart and/or block diagram can be realized by computer program instructions
The combination of flow and/or square frame in journey and/or square frame and flow chart and/or block diagram.These computer programs can be provided
The processor of all-purpose computer, special-purpose computer, Embedded Processor or other programmable data processing devices is instructed to produce
A raw machine so that produced for reality by the instruction of computer or the computing device of other programmable data processing devices
The device of the function of being specified in present one flow of flow chart or multiple one square frame of flow and/or block diagram or multiple square frames.
These computer program instructions may be alternatively stored in can guide computer or other programmable data processing devices with spy
In determining the computer-readable memory that mode works so that instruction of the storage in the computer-readable memory is produced and include finger
Make the manufacture of device, the command device realize in one flow of flow chart or multiple one square frame of flow and/or block diagram or
The function of being specified in multiple square frames.
These computer program instructions can be also loaded into computer or other programmable data processing devices so that in meter
Series of operation steps is performed on calculation machine or other programmable devices to produce computer implemented treatment, so as in computer or
The instruction performed on other programmable devices is provided for realizing in one flow of flow chart or multiple flows and/or block diagram one
The step of function of being specified in individual square frame or multiple square frames.Obviously, those skilled in the art can carry out various to the present invention
Change with modification without departing from the spirit and scope of the present invention.So, if these modifications of the invention and modification belong to this hair
Within the scope of bright claim and its equivalent technologies, then the present invention is also intended to comprising these changes and modification.
Claims (10)
1. a kind of data transmission method, it is characterised in that methods described is applied to I/O equipment and sends data to master by DMA
Machine, methods described includes：
Index quantity S/P is calculated according to preset buffer memory size S and average data packet length P, then according to indexing units
Size U calculate index memory block size I=（S / P）× U, and index memory block according to this size application；
The number of the datarams block for needing distribution is calculated according to the size of memory block M according to default cache size S and per block number
Amount N=S/M, and apply N block numbers according to memory block according to preset data block size M；
The start physical address and datarams of the start physical address, length and all of datarams block of memory block will be indexed
The size of block is written to I/O equipment；
Control I/O equipment passes through DMA transfer upstream data；
Main frame reads index information and obtains upstream data bag content according to the record of indexing units.
2. data transmission method as claimed in claim 1, it is characterised in that the indexing units include data packet length,
Datarams block sequence number, the offset address of packet original position, indexing units significant notation, indexing units are complete where packet
The information such as junction mark, wherein,
Data packet length is used for recording the length information of the corresponding packet of current indexing units；
Which data are datarams block sequence number where packet, be located in for recording the corresponding packet of current indexing units
In counterfoil；
The offset address of packet original position, the original position for recording the corresponding packet of current indexing units is deposited at it
The byte number that the start address of the datarams block put offsets backward；
Indexing units significant notation, for representing whether current indexing units are effective；
Indexing units finish mark, and whether the indexing units for representing next packet will start anew retrieval.
3. data transmission method as claimed in claim 2, it is characterised in that when the main frame obtains current indexing units pair
After the packet answered, it is invalid that current indexing units significant notation is set to, when the I/O equipment is stored in new packet to data
In memory block, current indexing units significant notation is set to effectively.
4. data transmission method as claimed in claim 2, it is characterised in that the main frame reads index information and according to index
The record of unit read upstream data bag content specifically,
When the significant notation that main frame checks indexing units to be read is asserted, i.e., according to record in indexing units
The offset address that datarams block sequence number and data where packet package beginning position finds corresponding data in datarams block
The position of bag, the data packet length for then being recorded according to indexing units obtains upstream data bag.
5. data transmission method as claimed in claim 4, it is characterised in that
After the main frame obtains packet, the mark that finishes of indexing units is also checked for, if the mark that finishes is effective, will finish mark
It is invalid that note is set to, while the indexing units position for checking of host record is changed into first indexing units；If complete
Junction mark is invalid, then the indexing units position for checking of host record is then changed into next indexing units.
6. a kind of data transmission system, it is characterised in that the system includes main frame and the I/O equipment being connected with main frame, described
I/O equipment sends data to main frame by DMA, and the main frame includes：
Index internal memory application unit, for according to preset buffer memory size S and average data packet length P calculate index quantity S/
P, then the size U according to indexing units calculate index memory block size I=（S / P）× U, and according to this size Shen
Please index memory block；
Datarams application unit, for calculating needs according to the size of memory block M according to default cache size S and per block number
Quantity N=S/the M of the datarams block of distribution, and apply N block numbers according to memory block according to preset data block size M；
Memory Allocation information transmitting unit, start physical address, length and all of datarams for memory block will to be indexed
The start physical address of block and the size of data memory block are written to I/O equipment；
Upstream data reading unit, for reading index information and obtaining upstream data bag content according to the record of indexing units.
7. data transmission system as claimed in claim 6, it is characterised in that the indexing units include data packet length,
Datarams block sequence number, the offset address of packet original position, indexing units significant notation, indexing units are complete where packet
The information such as junction mark, wherein,
Data packet length is used for recording the length information of the corresponding packet of current indexing units；
Which data are datarams block sequence number where packet, be located in for recording the corresponding packet of current indexing units
In counterfoil；
The offset address of packet original position, the original position for recording the corresponding packet of current indexing units is deposited at it
The byte number that the start address of the datarams block put offsets backward；
Indexing units significant notation, for representing whether current indexing units are effective；
Indexing units finish mark, and whether the indexing units for representing next packet will start anew retrieval.
8. data transmission system as claimed in claim 7, it is characterised in that when the main frame obtains current indexing units pair
After the packet answered, it is invalid that current indexing units significant notation is set to, when the I/O equipment is stored in new packet to data
In memory block, current indexing units significant notation is set to effectively.
9. data transmission system as claimed in claim 7, it is characterised in that the main frame reads index information and according to index
The record of unit read upstream data bag content specifically,
When the significant notation that main frame checks indexing units to be read is asserted, i.e., according to record in indexing units
The offset address that datarams block sequence number and data where packet package beginning position finds corresponding data in datarams block
The position of bag, the data packet length for then being recorded according to indexing units obtains upstream data bag.
10. data transmission system as claimed in claim 9, it is characterised in that
After the main frame obtains packet, the mark that finishes of indexing units is also checked for, if the mark that finishes is effective, will finish mark
It is invalid that note is set to, while the indexing units position for checking of host record is changed into first indexing units；If complete
Junction mark is invalid, then the indexing units position for checking of host record is then changed into next indexing units.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710082710.7A CN106844248B (en) | 2017-02-16 | 2017-02-16 | The method and system of data transmission |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710082710.7A CN106844248B (en) | 2017-02-16 | 2017-02-16 | The method and system of data transmission |
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| CN115190089A (en) * | 2022-05-26 | 2022-10-14 | 中科驭数（北京）科技有限公司 | Message storage method, device, equipment and storage medium |
| CN116974977A (en) * | 2023-07-26 | 2023-10-31 | 中科驭数（北京）科技有限公司 | Data transmission method, device, equipment and storage medium |
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