CN106817584A - A kind of MJPEG compressions implementation method and FPGA based on FPGA - Google Patents
A kind of MJPEG compressions implementation method and FPGA based on FPGA Download PDFInfo
- Publication number
- CN106817584A CN106817584A CN201611207295.5A CN201611207295A CN106817584A CN 106817584 A CN106817584 A CN 106817584A CN 201611207295 A CN201611207295 A CN 201611207295A CN 106817584 A CN106817584 A CN 106817584A
- Authority
- CN
- China
- Prior art keywords
- video data
- data stream
- fpga
- transform
- discrete cosine
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/102—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or selection affected or controlled by the adaptive coding
- H04N19/124—Quantisation
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/10—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding
- H04N19/134—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using adaptive coding characterised by the element, parameter or criterion affecting or controlling the adaptive coding
- H04N19/157—Assigned coding mode, i.e. the coding mode being predefined or preselected to be further used for selection of another element or parameter
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/48—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using compressed domain processing techniques other than decoding, e.g. modification of transform coefficients, variable length coding [VLC] data or run-length data
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/70—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals characterised by syntax aspects related to video coding, e.g. related to compression standards
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/85—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using pre-processing or post-processing specially adapted for video compression
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/90—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using coding techniques not provided for in groups H04N19/10-H04N19/85, e.g. fractals
- H04N19/91—Entropy coding, e.g. variable length coding [VLC] or arithmetic coding
Abstract
The embodiment of the invention provides a kind of MJPEG compression methods and FPGA based on FPGA, video data stream to caching carries out discrete cosine transform, then video data stream is carried out into transform again, to be quantified by the video data stream of transform, then run length encoding, the size of compressed video data stream are carried out to video data stream.By implementation of the invention, the characteristics of there is abundant programmable resource using FPGA, realize that MJPEG compresses on FPGA, it is ensured that the real-time and scalability of compression.
Description
Technical field
The present invention relates to field of video image processing, more particularly to a kind of MJPEG compression implementation methods based on FPGA and
FPGA。
Background technology
In video image transmission system, the transmission of multitude of video image data stream is referred to as system bottleneck；Pressed by MJPEG
Compression algorithm, can greatly reduce memory space and the network bandwidth required when vedio data is transmitted.Due to MJPEG compressions
Method comparison is complicated, and existing MJPEG compression algorithms are usually to be realized using software；But the real-time of algorithm and expansible
Property be all very limited, especially to multichannel high-resolution, frame-rate video image data stream compression high process, such as
1080p60f、4k60f。
The content of the invention
Present invention seek to address that prior art MJPEG compression algorithms realize the problem of real-time and poor expandability.
In order to solve the above technical problems, the present invention provides a kind of MJPEG compression implementation methods based on FPGA, including：
Video data stream to caching carries out discrete cosine transform；
Transform will be carried out by the video data stream after discrete cosine transform；
To be quantified by the video data stream of transform, and to quantization after the video data stream enter every trade
Journey is encoded；
To being encoded according to the size of entropy by the video data stream after run-length encoding, the video data is compressed
The size of stream.
Optionally, described pair carries out coding and includes by the video data stream after run-length encoding according to the size of entropy：
To carrying out Huffman encoding by the video data stream after run-length encoding.
Optionally, it is described to carry out quantization by the video data stream of transform and include：
According to the inverse of the quantization parameter for prestoring, corresponding video data stream is quantified.
Optionally, before the video data stream in described pair of caching carries out discrete cosine transform, also include：
Whether the video data stream for judging the caching is YCbCr format, if it is not, then changing into the video data stream
YCbCr format.
Optionally, before the video data stream in described pair of caching carries out discrete cosine transform, also include：
YY components and CbCr components in the video data stream of the YCbCr format is cached respectively.
The present invention also provides a kind of FPGA, including：
Discrete cosine transform module, for carrying out discrete cosine transform to the video data stream for caching；
Transform module, for transform will to be carried out by the video data stream after discrete cosine transform；
Quantization modules, for will be quantified by the video data stream of transform；
First coding module, run-length encoding is carried out for the video data stream after to quantization；
Second coding module, for being compiled according to the size of entropy by the video data stream after run-length encoding
Code, compresses the size of the video data stream.
Optionally, second coding module is additionally operable to：To being breathed out by the video data stream after run-length encoding
Fu Man is encoded.
Optionally, the quantization modules are additionally operable to：
According to the inverse of the quantization parameter for prestoring, corresponding video data stream is quantified.
Optionally, also including modular converter, it is used for：
Before the video data stream of the caching is carried out discrete cosine transform by the discrete cosine transform module, judge
Whether the video data stream is YCbCr format, if it is not, the video data stream then is changed into YCbCr format.
Optionally, also including cache module, for by the YY components and CbCr in the video data stream of the YCbCr format
Component is cached respectively.
The beneficial effects of the invention are as follows：
A kind of MJPEG compression implementation method and FPGA based on FPGA are the embodiment of the invention provides, to the video for caching
Data flow carries out discrete cosine transform, and video data stream then is carried out into transform again, will be flowed into by the video data of transform
Row quantifies, and then carries out run-length encoding, and Huffman encoding to video data stream, further compressed video data stream it is big
It is small.By implementation of the invention, the characteristics of there is abundant programmable logic resource using FPGA, MJPEG is realized on FPGA
Compression, it is ensured that the real-time and scalability of compression.
Brief description of the drawings
Fig. 1 is the MJPEG compression method flow charts based on FPGA of the embodiment of the present invention one；
Fig. 2 is the FPGA composition schematic diagrams of the embodiment of the present invention two；
Fig. 3 is the MJPEG compressibility composition schematic diagrams based on FPGA of the embodiment of the present invention three.
Specific embodiment
The embodiment of the present invention is described in further detail below by specific embodiment combination accompanying drawing.
Embodiment one：
The present embodiment provides a kind of MJPEG compression methods based on FPGA, refers to Fig. 1, specifically includes：
S101, the video data stream to caching carry out discrete cosine transform；
S102, transform will be carried out by the video data stream of discrete cosine transform；
S103, will be quantified by the video data stream of transform, and to quantization after the video data stream enter every trade
Journey is encoded, the size of compressed video data stream.
From for the angle of information theory, compression is exactly the redundancy in information of removing, and retains uncertain information, with one kind more
Replace the description of original redundancy close to the description of Essence of Information.Compression is broadly divided into two classes：Lossy compression method and Lossless Compression, its
In, if losing an other data does not result in too much influence, it is a good attention at this moment to ignore them, here it is damaging pressure
Contracting.Lossy compression method is widely used in animation, sound and image file, it is typical represent be exactly video disc file format MPEG,
Music file formats mp3 and image file format jpg.MJPEG in the present embodiment is equally a kind of lossy compression method.At other
In situation, then may may require that compressed data must be accurate, there has been nondestructive compression type, such as common zip, rar
Etc..
In the present embodiment, carried out with macro block MB=8*8bits as elementary cell due to MJPEG compression methods,
Therefore the video data stream being input into is needed first to cache.The video data stream of input is carried out successively according to address incremental order
Caching, in the present embodiment, with input video stream format as 1080p60f, sample rate YCbCr is 4:2:As a example by 2, caching it is big
Small should be 1920*8=15360@24bits.When according to address incremental order, just video data stream is cached, when writing
Address more than 13455 after write full two MB, you can to start the reading of the video data stream of caching.Then, when write address is super
Cross after 15359, that is, write and expired 8 rows, then read address write-in data according to original MB.And should be protected between write address and reading address
Hold gap to a certain extent, it is to avoid caching is fully written and causes loss of data.Wherein, the scope of clearance G AP can be set as
More than or equal to 128.
Therefore, exceeded after 13455 when data cached, it is possible to proceed follow-up processing procedure, subsequently everywhere
Reason flow can be MB data that input has been processed in MB in the unit interval, to meet the requirement of real-time processing.
In the present embodiment, discrete cosine transform is carried out to the video data stream for caching.Vedio data is each other
With certain correlation, this correlation observes not directly perceived enough in time domain, by discrete cosine transform, can remove it
Correlation, vedio data is observed from frequency domain.Vedio data be by the output spectrum after dct transform it is two-dimentional,
Upper left corner area is low frequency range, and lower right field is high frequency region.
Afterwards, after by dct transform, then transform is carried out to video data stream, transform be by the output of dct transform by
Zigzag scan, low-frequency data is connected in series.Transform will be carried out by the video data stream of dct transform, be basic with a MB
Unit, by the way of Pingpang Memory, is first sequentially written in, then is read by particular address.
Then, the video data stream by transform is quantified.Remaining after quantization is all low frequency range data, high frequency
Area's data become 0 mostly, and further image compression process can be carried out based on this.Quantification gradation 0~255 256 altogether,
In the present embodiment, can include quantization is carried out by the video data stream of transform：According to the inverse of the quantization parameter for prestoring,
Corresponding video data stream is quantified.During quantization, by the reciprocal of quantization parameter and the video data stream phase by transform
Multiply.Wherein, the video data stream of different address, its corresponding quantization parameter is also different.
Occur that a large amount of is zero data by the video data stream after quantization, i.e., substantial amounts of company zero goes here and there, gone here and there for even zero
Information, it is only necessary to record the number that it is zero, so can significantly reduce data transfer bandwidth.In this implementation
In example, by run-length encoding (Run-Length Encoding, RLE), it is possible to realize for continuous complete zero information only recording it
Number, so as to reach the purpose of the size of compressed video data stream.
Additionally, in the present embodiment, the video data stream after to quantization is carried out after run-length encoding, can also be included：
To being encoded according to the size of entropy by the video data stream after run-length encoding.In order to further reduce data transfer bandwidth,
Size according to information content is inputting video data stream distribution codeword, and the transmission of streams of video data bandwidth obtained after so encoding can
It is lower to drop to.After being encoded by RLE, encoded according to the size of entropy, i.e., encoded the larger data of entropy with long code, used
Short code encodes the less data of entropy.In the present embodiment, entropy code can be carried out using Huffman encoding, needed for Huffman encoding
The code word wanted can be stored in advance in code table.Further, it is also possible to using the others compression coding mode such as arithmetic coding.
Additionally, bit padding and BYTE Stuffer are carried out to the code stream after Huffman encoding, while adding JFIF
GEN Header。
Additionally, in the present embodiment, before discrete cosine transform is carried out to the video data stream for caching, can also wrap
Include：Whether the video data stream for judging caching is YCbCr format, if it is not, video data stream then is changed into YCbCr format.
When the sample rate of output video data stream is 4:2:When 2, for the YY and Cb and Cr in parallel processing video stream point
Amount, can be before discrete cosine transform be carried out, by the YY in the video data stream of YCbCr format to the video data stream for caching
Component and CbCr components are cached respectively.After this, it is possible to be respectively processed YY components and CbCr components, so as to realize
The parallel processing of video data stream.
A kind of MJPEG compression implementation methods based on FPGA are present embodiments provided, the video data stream to caching is carried out
Discrete cosine transform, then carries out transform by video data stream again, will be quantified by the video data stream of transform, then
Run-length encoding, Huffman encoding, the size of further compressed video data stream are carried out to video data stream.By reality of the invention
Apply, the characteristics of there is abundant programmable resource using FPGA, realize that MJPEG compresses on FPGA, it is ensured that compression it is real-time
Property and scalability.
Second embodiment
The present embodiment provides a kind of FPGA, refers to Fig. 1, specifically includes：
Discrete cosine transform module 101, for carrying out discrete cosine transform to the video data stream for caching；
Transform module 102, for transform will to be carried out by the video data stream after discrete cosine transform；
Quantization modules 103, for will be quantified by the video data stream of transform；
First coding module 104, for carrying out run-length encoding to the video data stream after quantization, compressed video data stream
Size.
In the present embodiment, carried out with macro block MB=8*8bits as elementary cell due to MJPEG compression methods,
Therefore the video data stream being input into is needed first to cache.The video data stream of input is carried out successively according to address incremental order
Caching, in the present embodiment, with input video stream format as 1080p60f, sample rate YCbCr is 4:2:As a example by 2, caching it is big
Small should be 1920*8=15360@24bits.When according to address incremental order, just video data stream is cached, when writing
Address more than 13455 after write full two MB, you can to start the reading of the video data stream of caching.Then, when write address is super
Cross after 15359, that is, write and expired 8 rows, then read address write-in data according to original MB.And should be protected between write address and reading address
Hold gap to a certain extent, it is to avoid caching is fully written and causes loss of data.Wherein, the scope of clearance G AP can be set as
More than or equal to 128.
Therefore, exceeded after 13455 when data cached, it is possible to proceed follow-up processing procedure, subsequently everywhere
Reason flow can be MB data that input has been processed in MB in the unit interval, to meet the requirement of real-time processing.
In the present embodiment, discrete cosine transform is carried out to the video data stream for caching.Vedio data is each other
With certain correlation, this correlation observes not directly perceived enough in time domain, by discrete cosine transform, can remove it
Correlation, vedio data is observed from frequency domain.Vedio data be by the output spectrum after dct transform it is two-dimentional,
Upper left corner area is low frequency range, and lower right field is high frequency region.
Afterwards, after by dct transform, then transform is carried out to video data stream, transform be by the output of dct transform by
Zigzag scan, low-frequency data is connected in series.Transform will be carried out by the video data stream of dct transform, be basic with a MB
Unit, by the way of Pingpang Memory, is first sequentially written in, then is read by particular address.
Then, the video data stream by transform is quantified.Remaining after quantization is all low frequency range data, high frequency
Area's data become 0 mostly, and further image compression process can be carried out based on this.Quantification gradation 0~255 256 altogether,
In the present embodiment, quantization modules 103 can be also used for：According to the inverse of the quantization parameter for prestoring, to corresponding video data stream
Quantified.During quantization, the inverse of quantization parameter is multiplied with the video data stream by transform.Wherein, different address is regarded
Frequency data stream, its corresponding quantization parameter is also different.
Occur that a large amount of is zero data by the video data stream after quantization, i.e., substantial amounts of company zero goes here and there, gone here and there for even zero
Information, it is only necessary to record the number that it is zero, so can significantly reduce data transfer bandwidth.In this implementation
In example, by run-length encoding RLE, it is possible to realize for continuous complete zero information only recording its number, so as to reach compression video
The purpose of the size of data flow.
Additionally, in the present embodiment, the second coding module 105 can also be included, for by regarding after run-length encoding
Frequency data stream is encoded according to the size of entropy.It is defeated according to the size of information content to further reduce data transfer bandwidth
Enter video data stream distribution codeword, the transmission of streams of video data bandwidth obtained after so encoding can drop to lower.By RLE
After coding, encoded according to the size of entropy, i.e., encoded the larger data of entropy with long code, the less number of entropy is encoded with short code
According to.In the present embodiment, entropy code can be carried out using Huffman encoding, the code word required for Huffman encoding can be deposited in advance
Storage is in code table.
Additionally, adding JFIF GEN simultaneously to code stream bit padding and the BYTE Stuffer after Huffman encoding
Header, so that the MJPEG compressions of further perfect whole video data stream.
Additionally, in the present embodiment, modular converter 106 can also be included, for being carried out in the video data stream to caching
Before discrete cosine transform, whether the video data stream for judging caching is YCbCr format, if it is not, then changing into video data stream
YCbCr format.
When the sample rate of output video data stream is 4:2:When 2, for the YY and Cb and Cr in parallel processing video stream point
Amount, can also include cache module 107 in the present embodiment, for the YY components in the video data stream by YCbCr format and
CbCr components are cached respectively.After this, it is possible to be respectively processed YY components and CbCr components, it is achieved thereby that video
The parallel processing of data flow.
A kind of FPGA is present embodiments provided, the video data stream to caching carries out discrete cosine transform, then will regard again
Frequency data stream carries out transform, will be quantified by the video data stream of transform, then carries out stroke volume to video data stream
Code and Huffman encoding, the size of further compressed video data stream.By implementation of the invention, have what is enriched using FPGA
The characteristics of programmable resource, realize that MJPEG compresses on FPGA, it is ensured that the real-time and scalability of compression.
Embodiment three
The present embodiment provides a kind of MJPEG compressibilities based on FPGA, refer to Fig. 3, including：
1) cache module 107
Because MJPEG compression algorithms are processed by elementary cell of macro block MB=8*8bits, therefore input is regarded
Frequency stream needs first to be cached；Cache size is 1920*8@24bits=15360@24bits.
Input video stream is cached to cache module 107 successively by address incremental order first, when the write address of cache module 107
Full 2 MB are write after more than 13455, subsequent module starts to read data by MB；When the write address of cache module 107 exceedes
Full 8 rows are write after 15359, then reads sequence of addresses write-in data according to original MB, and write address must keep GAP with address is read>
=128 gaps, it is to avoid input buffer module 107 is filled and causes loss of data.
From the foregoing, after cache module 107 fills data more than 13455, MJPEG follow-up its main operational module etc.
Stream treatment can be started；Follow-up each submodule is the MB data that input has been processed in MB in the unit interval, to meet in real time
The requirement for the treatment of.
2) modular converter 106
The module mainly realizes being converted into the video data stream of rgb format the video data stream of YCbCr format, if defeated
It is YCbCr format to enter, then the module can be with bypass.
3) DCT modules 101
Because input video stream sample rate is 4:2:2, for YY the and CbCr components in parallel processing video stream, cache mould
Block 107 needs 2, and one is used to cache YY components, and another is used for CbCr components.After caching is more than 2 MB, with 1 MB
It is elementary cell, the value of Y-component is read by row scanning, carries out dct transform；Be elementary cell with 2 MB, by row scanning 2 times according to
Secondary reading Cb values and Cr values, carry out dct transform；It is that DCT modules 101 can be parallel in 128 clock cycle so in 2 MB
Treatment YCbCr4:2:2.
4) transform module 102
MB to the output of DCT modules 101 carries out transform, is elementary cell with 1 MB, by the way of Pingpang Memory, first
It is sequentially written in, is read by particular address.
5) quantization modules 103
Quantification gradation 0~255 totally 256, what Q values memory module was stored is the inverse of quantization parameter；Carrying out Q quantizations
When, it is first to read address according to predetermined quantification gradation, quantization parameter is read, then it is multiplied with input data.
6) the first coding module 104
Occur by the video flowing after quantization and largely connect zero string, even zero string information is only needed to record its number,
Data transfer bandwidth can so be reduced；RLE is encoded with MB as elementary cell, is output as elongated MB.
7) poller module 108
To meet the requirement of real-time processing, its main operational module uses full speed stream treatment, such first coding mould
Elongated MB totally 2 tunnels of the output of block 104：YY and CbCr；, it is necessary to parallel data stream is changed before the second coding module 105 is entered
It is serial data stream.
8) the second coding module 105
Further to reduce data transfer bandwidth, it is necessary to carry out entropy code to the serial elongated MB of poller module output, i.e.,
Huffman encoding, is inputting video data stream distribution codeword, the video data obtained after so encoding according to the size of information content
Streaming bandwidth is preferably minimized；Code word required for Huffman encoding is stored in advance in code table.
9) padding bytes module 109＆JFIF GEN modules 110
Bit padding and BYTE Stuffer are carried out to the code stream after Huffman encoding and adds JFIF GEN simultaneously
Header, that is, complete the MJPEG compressions of whole input video stream.
Above-mentioned summary is with video flowing 1080p60f sample rates 4:2:As a example by 2, if sample rate is 4:4:4, then only need into
The corresponding extension of row；If input video stream is rgb format, it is only necessary to open modular converter 106.
Obviously, those skilled in the art should be understood that each module or each step of the embodiments of the present invention can be used
General computing device realizes that they can be concentrated on single computing device, or be distributed in multiple computing device institutes
On the network of composition, alternatively, the program code that they can be can perform with computing device be realized, it is thus possible to by they
Storage is performed in computer-readable storage medium (ROM/RAM, magnetic disc, CD) by computing device, and in some cases, can
Shown or described step is performed with different from order herein, or they are fabricated to each integrated circuit die respectively
Block, or the multiple modules or step in them are fabricated to single integrated circuit module to realize.So, the present invention is not limited
Combined in any specific hardware and software.
Above content is to combine the further description that specific embodiment is made to the embodiment of the present invention, it is impossible to recognized
Fixed specific implementation of the invention is confined to these explanations.For general technical staff of the technical field of the invention,
Without departing from the inventive concept of the premise, some simple deduction or replace can also be made, the present invention should be all considered as belonging to
Protection domain.
Claims (10)
1. a kind of MJPEG based on FPGA compresses implementation method, including：
Video data stream to caching carries out discrete cosine transform；
Transform will be carried out by the video data stream after discrete cosine transform；
To be quantified by the video data stream of transform, and to quantization after the video data stream carry out stroke volume
Code；
To being encoded according to the size of entropy by the video data stream after run-length encoding, the video data stream is compressed
Size.
2. the MJPEG based on FPGA as claimed in claim 1 compresses implementation method, it is characterised in that described pair through overtravel
The video data stream after coding carries out coding according to the size of entropy to be included：Huffman volume is carried out to the video stream data
Code.
3. MJPEG compression implementation methods based on FPGA as claimed in claim 1, it is characterised in that it is described will be by transform
Video data stream carry out quantization and include：
According to the inverse of the quantization parameter for prestoring, corresponding video data stream is quantified.
4. the MJPEG based on FPGA as described in claim any one of 1-3 compresses implementation method, it is characterised in that described
Before video data stream to caching carries out discrete cosine transform, also include：
Whether the video data stream for judging the caching is YCbCr format, if it is not, the video data stream then is changed into YCbCr
Form.
5. the MJPEG based on FPGA as claimed in claim 4 compresses implementation method, it is characterised in that cache at described Dui
Before video data stream carries out discrete cosine transform, also include：
YY components and CbCr components in the video data stream of the YCbCr format is cached respectively.
6. a kind of FPGA, it is characterised in that including：
Discrete cosine transform module, for carrying out discrete cosine transform to the video data stream for caching；
Transform module, for transform will to be carried out by the video data stream after discrete cosine transform；
Quantization modules, for will be quantified by the video data stream of transform；
First coding module, run-length encoding is carried out for the video data stream after to quantization；
Second coding module, for being encoded according to the size of entropy by the video data stream after run-length encoding, pressing
The size of the video data stream that contracts.
7. FPGA as claimed in claim 6, it is characterised in that second coding module is additionally operable to：To by run-length encoding
The video data stream afterwards carries out Huffman encoding.
8. FPGA as claimed in claim 6, it is characterised in that the quantization modules are additionally operable to：
According to the inverse of the quantization parameter for prestoring, corresponding video data stream is quantified.
9. the FPGA as described in claim 6-8, it is characterised in that also including modular converter, be used for：
Before the video data stream of the caching is carried out discrete cosine transform by the discrete cosine transform module, judge described
Whether video data stream is YCbCr format, if it is not, the video data stream then is changed into YCbCr format.
10. FPGA as claimed in claim 9, it is characterised in that also including cache module, for by the YCbCr format
YY components and CbCr components in video data stream are cached respectively.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611207295.5A CN106817584A (en) | 2016-12-23 | 2016-12-23 | A kind of MJPEG compressions implementation method and FPGA based on FPGA |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611207295.5A CN106817584A (en) | 2016-12-23 | 2016-12-23 | A kind of MJPEG compressions implementation method and FPGA based on FPGA |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106817584A true CN106817584A (en) | 2017-06-09 |
Family
ID=59110640
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611207295.5A Pending CN106817584A (en) | 2016-12-23 | 2016-12-23 | A kind of MJPEG compressions implementation method and FPGA based on FPGA |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106817584A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108832935A (en) * | 2018-05-31 | 2018-11-16 | 郑州云海信息技术有限公司 | A kind of RLE algorithm implementation method, system, equipment and computer storage medium |
| CN110313178A (en) * | 2018-04-04 | 2019-10-08 | 深圳市大疆创新科技有限公司 | Code device and system |
| CN111726634A (en) * | 2020-07-01 | 2020-09-29 | 成都傅立叶电子科技有限公司 | High-resolution video image compression transmission method and system based on FPGA |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100746484B1 (en) * | 2006-11-02 | 2007-08-03 | 김응수 | A real time remote monitoring system for water flea activity status using ccd camera |
| CN101094401A (en) * | 2006-06-23 | 2007-12-26 | 深圳安凯微电子技术有限公司 | Image compression / decompression method and system |
| US20090003690A1 (en) * | 2007-06-28 | 2009-01-01 | Yueguang Jiao | Method and system for processing image at high speed |
| CN201893860U (en) * | 2010-11-30 | 2011-07-06 | 杭州荣耀科技有限公司 | High definition film camera |
| CN104883518A (en) * | 2015-05-11 | 2015-09-02 | 杭州奕霖传感科技有限公司 | Low-cost small-sized thermal infrared imager |
-
2016
- 2016-12-23 CN CN201611207295.5A patent/CN106817584A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101094401A (en) * | 2006-06-23 | 2007-12-26 | 深圳安凯微电子技术有限公司 | Image compression / decompression method and system |
| KR100746484B1 (en) * | 2006-11-02 | 2007-08-03 | 김응수 | A real time remote monitoring system for water flea activity status using ccd camera |
| US20090003690A1 (en) * | 2007-06-28 | 2009-01-01 | Yueguang Jiao | Method and system for processing image at high speed |
| CN201893860U (en) * | 2010-11-30 | 2011-07-06 | 杭州荣耀科技有限公司 | High definition film camera |
| CN104883518A (en) * | 2015-05-11 | 2015-09-02 | 杭州奕霖传感科技有限公司 | Low-cost small-sized thermal infrared imager |
Non-Patent Citations (1)
| Title |
|---|
| 包宋建等: "基于XC2S600E的MJPEG编码器研究与实现", 《重庆文理学院学报(自然科学版)》 * |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110313178A (en) * | 2018-04-04 | 2019-10-08 | 深圳市大疆创新科技有限公司 | Code device and system |
| CN108832935A (en) * | 2018-05-31 | 2018-11-16 | 郑州云海信息技术有限公司 | A kind of RLE algorithm implementation method, system, equipment and computer storage medium |
| CN111726634A (en) * | 2020-07-01 | 2020-09-29 | 成都傅立叶电子科技有限公司 | High-resolution video image compression transmission method and system based on FPGA |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8874531B2 (en) | Methods and systems for encoding/decoding files and transmissions thereof | |
| JP5399416B2 (en) | Video coding system with reference frame compression | |
| TWI496116B (en) | Improving decoder performance through quantization control | |
| JP2009506606A (en) | Image data processing method | |
| CN105472389B (en) | Compression method is cached outside a kind of piece for ultra high-definition processing system for video | |
| CN109842803A (en) | A kind of method and device of compression of images | |
| JP2014039257A (en) | Decoder and decoding method | |
| CN102378991A (en) | Compressed domain system and method for compression gains in encoded data | |
| CN106817584A (en) | A kind of MJPEG compressions implementation method and FPGA based on FPGA | |
| JP2011518527A (en) | Video decoding | |
| CN105472442A (en) | Out-chip buffer compression system for superhigh-definition frame rate up-conversion | |
| CN105791819B (en) | The decompression method and device of a kind of frame compression method of image, image | |
| KR102238091B1 (en) | System and method for 3d model compression and decompression | |
| JP2009171134A (en) | Video format converter | |
| Konstantinov et al. | The use of asymmetric numeral systems entropy encoding in video compression | |
| JP2004501531A (en) | Method and apparatus for run-length encoding video data | |
| EP3461009A1 (en) | High density archival | |
| KR20200107745A (en) | Sub-block based entropy coding for embedded image codec | |
| TWI565303B (en) | Image processing system and image processing method | |
| Reddy et al. | A novel approach of lossless image compression using hashing and Huffman coding | |
| Chandra et al. | LOSS LESS COMPRESSION OF IMAGES USING BINARY PLANE, DIFFERENCE AND HUFFMAN CODING (BDH TECHNIQUE). | |
| CN110087072A (en) | Image processing apparatus | |
| CN113905255B (en) | Media data editing method, media data packaging method and related equipment | |
| KR102154580B1 (en) | Image processing apparatus and method | |
| WO2021192784A1 (en) | Video encoding system and video encoding method |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| RJ01 | Rejection of invention patent application after publication |
Application publication date: 20170609 |
|
| RJ01 | Rejection of invention patent application after publication |