CN106817021B - Charge pump circuit - Google Patents
Charge pump circuit Download PDFInfo
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- CN106817021B CN106817021B CN201610072649.3A CN201610072649A CN106817021B CN 106817021 B CN106817021 B CN 106817021B CN 201610072649 A CN201610072649 A CN 201610072649A CN 106817021 B CN106817021 B CN 106817021B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/06—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider
- H02M3/07—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using resistors or capacitors, e.g. potential divider using capacitors charged and discharged alternately by semiconductor devices with control electrode, e.g. charge pumps
- H02M3/073—Charge pumps of the Schenkel-type
- H02M3/076—Charge pumps of the Schenkel-type the clock signals being boosted to a value being higher than the input voltage value
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Dc-Dc Converters (AREA)
Abstract
The embodiment provides a kind of charge pump circuit, which includes sub-circuit, which is pump stage circuit or output-stage circuit.Sub-circuit includes input, output end, transistor, first capacitor device, first diode device and the second diode component.Transistor has the first source/drain (S/D) coupled with input terminal end, the 2nd end S/D coupled with output end and gate terminal.First capacitor device has the first end coupled with the gate terminal of transistor and is configured to receive the second end of the first driving signal.First diode device has the cathode coupled with the 2nd end S/D of transistor and the anode coupled with the gate terminal of transistor.Second diode component has the cathode coupled with the gate terminal of transistor and the anode coupled with the 2nd end S/D of transistor.
Description
Technical field
This invention relates generally to technical field of semiconductors, more particularly, to charge pump circuit and its operating method.
Background technique
Charge pump circuit is direct current (DC)-(DC) converter, and the voltage of the voltage level generated is higher than input power electricity
The voltage level (positive charge pump) of pressure or voltage level (negative charge pump) lower than reference ground voltage.In some applications, electric
Lotus pump circuit includes the capacitor as energy storage elements and the transistor as memory transfer element.In some applications
In, transistor on or off in response to various control signals, and control signal and connect by input supply voltage and reference
The limitation of the voltage level of ground voltage.Moreover, charging and level by the voltage level on the capacitor to charge pump circuit
Shifting function, each drain/source terminal of transistor have the voltage for moving up or moving down.In some applications, each move up/under
The voltage level of the voltage of shifting has exceeded input supply voltage and with reference to the voltage range between ground voltage.
Summary of the invention
In order to solve the existing defects in the prior art, according to an aspect of the present invention, a kind of charge pump electricity is provided
Road, comprising: sub-circuit, the sub-circuit are pump stage circuit or output-stage circuit, and the sub-circuit includes: input terminal；Output end；
Transistor, the 2nd end S/D that there is the first source/drain (S/D) coupled with the input terminal end, coupled with the output end
And gate terminal；First capacitor device has the first end coupled with the gate terminal of the transistor and is configured to connect
Receive the second end of the first driving signal；First diode device has the cathode coupled with the 2nd end S/D of the transistor
And the anode coupled with the gate terminal of the transistor；And second diode component, there is the grid with the transistor
The anode holding the cathode of coupling and being coupled with the 2nd end S/D of the transistor.
In the charge pump circuit, the sub-circuit is the pump stage circuit, the sub-circuit further include: the second capacitive character
Device has the first end coupled with the output end and is configured to receive the second end of the second driving signal.
The charge pump circuit further include: control circuit is configured to generate first control signal and second control signal,
In, the sub-circuit further include: the first driver is configured to the first control signal to generate the first driving letter
Number；And second driver, the second control signal is configured to generate second driving signal.
In the charge pump circuit, first driver be configured to make first driving signal with logic-high value phase
Switch between corresponding first voltage level and reference voltage level corresponding with logic low value；And second driver
Be configured to make second driving signal second voltage level corresponding with the logic-high value and with the logic low value
Switch between corresponding reference voltage level, the first voltage level is different from the second voltage level.
In the charge pump circuit, the first diode device has forward voltage drop；The second diode component tool
There is forward voltage drop；And the forward voltage drop of the first diode device is greater than the forward voltage drop of second diode component.
In the charge pump circuit, the first diode device includes X transistor for being connected as diode, and X is big
In zero positive integer, and when X is greater than 1, the X transistor for being connected as diode is connected in series；And described second
Diode component includes Y transistor for being connected as diode, and Y is the positive integer greater than zero and less than X, and when Y is greater than 1
When, the Y transistor for being connected as diode is connected in series.
In the charge pump circuit, the first diode device has forward voltage drop；The transistor has threshold value electricity
Pressure；And the forward voltage drop of the first diode device is greater than the threshold voltage of the transistor.
In the charge pump circuit, the transistor is N-type transistor.
According to another aspect of the present invention, a kind of charge pump circuit is provided, comprising: input node；Output node；It is N number of
Pump stage circuit, N are the positive integer greater than zero, and each of described N number of pump stage circuit pump stage circuit all includes: input terminal；With
Output end；And output-stage circuit, including input terminal and output end；Wherein, the first pump stage circuit in N number of pump stage circuit
Input terminal coupled with the input node；The output end of n-th of pump stage circuit in N number of pump stage circuit with it is described N number of
The input terminal of (n+1) a pump stage circuit in pump stage circuit couples, and n is positive integer and 1≤n≤(N-1)；N number of pump
The output end of n-th pump stage circuit in grade circuit is coupled with the input terminal of the output-stage circuit；The output-stage circuit
Output end is coupled with the output node；With one in N number of pump stage circuit further include: transistor, the transistor tool
Have: the first source/drain (S/D) end is coupled with one input node in N number of pump stage circuit；2nd end S/D, with
One output node coupling in N number of pump stage circuit；And gate terminal；First capacitor device has and the crystalline substance
The first end of the gate terminal coupling of body pipe and the second end for being configured to the first driving signal of reception；Second capacitive character device
Part has the first end coupled with one output node in N number of pump stage circuit and is configured to receive the second drive
The second end of dynamic signal；First diode device, have the cathode that is coupled with the 2nd end S/D of the transistor and with institute
State the anode of the gate terminal coupling of transistor；And second diode component, have and to be coupled with the gate terminal of the transistor
Cathode and the anode coupled with the 2nd end S/D of the transistor.
Charge pump circuit further include: control circuit is configured to generate multiple control signal, wherein N number of pump stage electricity
One in road further include: the first driver is configured to the first control signal in the multiple control signal to generate
First driving signal；And second driver, the second control signal being configured in the multiple control signal are come
Generate second driving signal.
In the charge pump circuit, first driver includes the first phase inverter；And second driver includes
Second phase inverter.
In the charge pump circuit, first driver be configured to make first driving signal with logic-high value phase
Switch between corresponding first voltage level and reference voltage level corresponding with logic low value；And second driver
Be configured to make second driving signal second voltage level corresponding with the logic-high value and with the logic low value
Switch between corresponding reference voltage level, the first voltage level is different from the second voltage level.
In the charge pump circuit, the first diode device has forward voltage drop；The second diode component tool
There is forward voltage drop；And the forward voltage drop of the first diode device is greater than the forward voltage drop of second diode component.
In the charge pump circuit, the first diode device includes X transistor for being connected as diode, and X is big
In zero positive integer, and when X is greater than 1, the X transistor for being connected as diode is connected in series；And described second
Diode component includes Y transistor for being connected as diode, and Y is the positive integer greater than zero and less than X, and when Y is greater than 1
When, the Y transistor for being connected as diode is connected in series.
In the charge pump circuit, the first diode device has forward voltage drop；The transistor has threshold value electricity
Pressure；And the forward voltage drop of the first diode device is greater than the threshold voltage of the transistor.
In the charge pump circuit, the transistor is N-type transistor.
In the charge pump circuit, the input node is configured to receive reference voltage；And the output node configuration
To export pump voltage, the voltage level of the pump voltage is lower than the voltage level of the reference voltage.
According to another aspect of the invention, a kind of pump stage circuit or output-stage circuit for operating charge pump circuit is provided
Method, which comprises in response to controlling the first logical value of signal, make the voltage electricity at the first end of capacitive device
It puts down from first voltage level transitions to second voltage level；In response to the second voltage at the first end of the capacitive device
Level makes voltage level translation at the second end of the capacitive device to tertiary voltage level, the capacitive device
The second end and the gate terminal of transistor be electrically coupled；And work as the transistor turns and first diode device forward bias
When setting and being connected, the gate terminal of the transistor is adjusted by the first diode device and source/drain (S/D) holds it
Between first voltage it is poor, the first diode device have the anode that is coupled with the gate terminal of the transistor and with it is described
The cathode of the end the S/D coupling of transistor.
This method further include: when the transistor cutoff and the second diode component forward bias and when being connected, lead to
It is poor to cross the second voltage that second diode component is adjusted between the end S/D of the transistor and gate terminal, the described 2nd 2
Pole pipe device has the anode coupled with the end S/D of the transistor and the cathode coupled with the gate terminal of the transistor.
In the method, the first diode device has forward voltage drop；The transistor has threshold voltage；And
The forward voltage drop of the first diode device is greater than the threshold voltage of the transistor.
Detailed description of the invention
When reading in conjunction with the accompanying drawings, each side that the present invention may be better understood according to the following detailed description
Face.It is emphasized that according to the standard practices in industry, various parts are not drawn to scale.In fact, in order to clear
Discussion, the size of various parts can be arbitrarily increased or reduce.
Fig. 1 is the functional block diagram of charge pump circuit in accordance with some embodiments.
Fig. 2 is pump stage (pumping stage) circuit in accordance with some embodiments that can be used for the charge pump circuit in Fig. 1
Circuit diagram.
Fig. 3 is the circuit diagram of the output-stage circuit in accordance with some embodiments that can be used for the charge pump circuit in Fig. 1.
Fig. 4 is the circuit diagram of the control circuit in accordance with some embodiments that can be used for the charge pump circuit in Fig. 1.
Fig. 5 A and Fig. 5 B are the output-stage circuits in the pump stage circuit or Fig. 3 in accordance with some embodiments that can be used as in Fig. 2
In diode component two exemplary diode devices circuit diagram.
Fig. 6 is each of the charge pump circuit in Fig. 1 that combination Fig. 2 to Fig. 4 in accordance with some embodiments is further shown
The timing diagram of voltage level on node.
Fig. 7 is the flow chart of the method for the pump stage circuit in operation diagram 2 in accordance with some embodiments.
Fig. 8 is the circuit diagram of the signal generating circuit in the control circuit in accordance with some embodiments that can be used for Fig. 4.
Specific embodiment
Following disclosure provides many different embodiments or examples, for realizing different characteristic of the invention.Below
By the particular instance for describing component and arrangement to simplify the present invention.Certainly, these are only examples and are not intended to limit the present invention.
For example, in the following description, above second component or the upper formation first component may include the first component and second component shape
It also may include that the additional component being formed between the first component and second component makes first as the embodiment directly contacted
The embodiment that component and second component are not directly contacted with.In addition, the present invention can in multiple examples repeat reference numerals and/or
Character.This repetition is for purposes of simplicity and clarity, and itself not indicate each embodiment discussed and/or match
Relationship between setting.
In addition, for ease of description, can be used herein such as " in ... lower section ", " ... below ", " lower part ",
" ... above ", the spatial relation terms such as " top " to be to describe an element or component and another element or component as shown in the figure
Relationship.In addition to orientation shown in figure, spatial relation term be intended to include using or operating process in device difference
Orientation.Device can be positioned in other ways and (is rotated by 90 ° or in other orientation), and space phase used herein
Relationship description symbol can be similarly interpreted accordingly.
According to some embodiments, the pump stage circuit or output-stage circuit of charge pump circuit include transistor and transistor
Two diode devices between the capacitive device of gate terminal coupling and gate terminal and source/drain (S/D) end of transistor
Part.Two diode components are coupled in a manner of reverse parallel connection.Pass through road of discharging provided by one in two diode components
DC between the gate terminal of diameter and transistor and driving signal is isolated, and the voltage difference between gate terminal and the end S/D remains about
For one forward voltage drop in two diode components.
Fig. 1 is the functional block diagram of charge pump circuit 100 in accordance with some embodiments.Charge pump circuit 100 includes: input section
Point 102；Output node 104；Reference voltage end 106；N number of pump stage circuit 110 [1], 110 [2] and 110 [N]；Output-stage circuit
120；And control circuit 130.N is equal to or greater than 1 positive integer.As unrestricted example, Fig. 1 shows three pumps
Grade circuit 110 [1], 110 [2] and 110 [N] (that is, N=3).Pump stage circuit 110 [1], 110 [2] and 110 [N] and output stage
Circuit 120 is coupled between input node 102 and output node 104.Control circuit 130 and output node 104 and reference voltage
106 coupling of end, and be configurable to generate for controlling pump stage circuit 110 [1], 110 [2] and 110 [N] and output-stage circuit
The multiple control signal SW [1] of 120 operation, SW [2], SW [N], SWF, CP [1], CP [2] and CP [N].
Each of pump stage circuit 110 [1], 110 [2] and 110 [N] pump stage circuit all includes input terminal IN, output end
OUT and control signal end SW and CP.Output-stage circuit 120 includes input terminal IN, output end OUT and control signal end SW.The
The input terminal IN of one pump stage circuit 110 [1] is coupled with input node 102.The output end OUT of n-th of pump stage circuit 110 [n] with
The input terminal IN of (n+1) a pump stage circuit 110 [n+1] is coupled, and wherein n is positive integer and 1≤n≤(N-1).N-th pump
The output end OUT of grade circuit 110 [N] is coupled with the input terminal IN of output-stage circuit 120.The output end OUT of output-stage circuit 120
It is coupled with output node 104.
In some embodiments, pump stage circuit 110 [1], 110 [2] and 110 [N] are configured to have at input node 102
Voltage level VINVoltage be converted to the predetermined voltage level V at output node 104OUT.It is transported in the stable state of charge pump circuit 100
Between the departure date, and ignore transient overshoot or undershoot, the voltage level at the output end OUT of pump stage circuit 110 [1] is in VINWith V1It
Between switch；Voltage level at the output end OUT of pump stage circuit 110 [2] is in V1With V2Between switch；Pump stage circuit 110 [N]
Voltage level at input terminal IN is in VN-2With VN-1Between switch；And the voltage at the output end OUT of pump stage circuit 110 [N]
Level is in VN-1With VOUTBetween switch.In some embodiments, the voltage level root on the output end OUT of pump stage circuit 110 [n]
According to following equation in Vn-1With VnBetween switch:
Δ V=VOUT-VN； (1)
V0=VN； (2)
VN=VOUT；And (3)
Vn=VN+ n* (Δ V/N), n are positive integer and 1≤n≤(N-1) (4)
In some embodiments, voltage level VOUTGreater than voltage level VIN, charge pump circuit 100 be used as positive charge pump, because
This, Δ V has positive value.In some embodiments, voltage level VOUTLess than voltage level VIN, charge pump circuit 100 is as negative electricity
Lotus pump, therefore, Δ V has negative value.
In addition, the control signal end SW of pump stage circuit 110 [1] is configured to receive control signal SW [1]；And pump stage circuit
The control signal end CP of 110 [1] is configured to receive control signal CP [1].The control signal end SW of pump stage circuit 110 [2] is configured
Signal SW [2] are controlled to receive；And the control signal end CP of pump stage circuit 110 [2] is configured to receive control signal CP [2].
The control signal end SW of pump stage circuit 110 [N] is configured to receive control signal SW [N]；And the control of pump stage circuit 110 [N]
Signal end CP is configured to receive control signal CP [N].The control signal end SW of output-stage circuit 120 is configured to receive control signal
SWF.It is responded herein in connection with Fig. 2 and Fig. 6 detailed description pump stage circuit 110 [1], 110 [2] and 110 [N] and output-stage circuit 120
In the illustrative embodiments and operation of each control signal.
Control circuit 130 is coupled with output node 104 and reference voltage end 106, and is configured as: being based on output node
Voltage level V at 104OUTWith the reference voltage level V at reference voltage end 106REF, generate multiple control signal SW [1], SW
[2], SW [N], SWF, CP [1], CP [2] and CP [N].In some embodiments, signal SW [n] and corresponding signal CP [n] tool
There is identical waveform.In some embodiments, the voltage level pulse width (corresponding to logic-high value) that signal SW [n] has is no
It is same as the voltage level pulse width of corresponding signal CP [n].
In some embodiments, all odd signals SW [n] first waveforms all having the same, and all even signals
SW [n] the second waveform all having the same.In some embodiments, first waveform and the second waveform are not and logic-high value simultaneously
Corresponding voltage level, therefore, odd signals SW [n] and even signal SW [n] are referred to as non-overlap signal.In some implementations
In example, all odd signals CP [n] third waveforms all having the same, and all even signal CP [n] are having the same
4th waveform.In some embodiments, third waveform and the 4th waveform simultaneously for logically high corresponding voltage level, because
This, odd signals CP [n] and even signal CP [n] are referred to as non-overlap signal.
Herein in connection with the illustrative embodiments and operation of Fig. 4 detailed description control circuit 130.
Fig. 2 is that the circuit of the pump stage circuit 200 of the charge pump circuit 100 in accordance with some embodiments that can be used in Fig. 1 shows
It is intended to.In some embodiments, pump stage circuit 200 can be used as any one in pump stage circuit 110 [1], 110 [2] and 110 [N]
A or all pump stage circuit.
Pump stage circuit 200 includes input terminal IN, output end OUT and control signal end SW and CP, corresponds respectively to Fig. 1
In pump stage circuit 110 [1], 110 [2] or 110 [N] end IN, OUT, SW and CP.In order to illustrate input terminal IN has voltage
VS, and output end OUT has voltage VD.Control signal end SW is configured to receive control signal S1, which, which corresponds to, controls
Signal SW [1], SW [2] or SW [N] processed.Control signal end CP is configured to receive control signal S2, which, which corresponds to, controls
Signal CP [1], CP [2] or CP [N] processed.
Pump stage circuit 200 includes transistor 210, first capacitor device 222, the second capacitive device 224, the one or two pole
Tube device 232, the second diode component 234, the first driver 242 and the second driver 244.
Transistor 210 is N-type transistor and is used as switching device.In some embodiments, transistor 210 is implemented as
P-type transistor or other switching devices applicatory.Transistor 210 includes gate terminal 212, the first end S/D 214 and the 2nd S/
The end D 216.First end S/D 214 is coupled with input terminal IN.2nd end S/D 216 is coupled with output end OUT.Gate terminal 212 has electricity
Press VG。
First capacitor device 222 has the first end coupled with the gate terminal 212 of transistor 210 and is configured to connect
Receive driving signal S3The second end.Second capacitive device 224 has and the output end OUT first end coupled and configuration
To receive driving signal S4The second end.First diode device 232 has to be coupled with the 2nd end S/D 216 of transistor 210
Cathode and the anode that is coupled with the gate terminal 212 of transistor 210.Second diode component 234 has and transistor 210
The cathode that gate terminal 212 couples and the anode coupled with the 2nd end S/D 216 of transistor 210.
First driver 242 is configured that based on control signal S1Generate driving signal S3.Second driver 244 is configured that
Based on control signal S2Generate driving signal S4.First driver 242 is phase inverter, with what is coupled with control signal end SW
Input terminal and the output end coupled with the second end of capacitive device 222.Second driver 244 is phase inverter, is had
With the output end control signal end CP input terminal coupled and coupled with the second end of capacitive device 224.In some realities
It applies in example, the first driver 242 and the second driver 244 are implemented as one kind or following combination of devices of following device: reverse phase
Device, buffer, level converter or other suitable devices.In some embodiments, signal S1、S2、S3And S4Each of
Signal is all in first voltage level corresponding with logic-high value (hereinafter referred to as " the first logic high ") and and logic low value
Switch between corresponding reference ground voltage level (hereinafter referred to as " logic low ").In some embodiments, signal S3
And S4Each of signal all switch between the first logic high and logic low, and signal S1And S2In it is every
One signal is all in second voltage level corresponding with logic-high value (hereinafter referred to as " the second logic high ") and logic low
Switch between level.In some embodiments, the second logic high is greater than the first logic high.
In diode component forward bias and when being connected, diode component has the forward direction between its anode and cathode
Pressure drop.In some embodiments, first diode device 232 has forward voltage drop VFB1, the second diode component 234 is with just
To pressure drop VFB2, and forward voltage drop VFB1Greater than forward voltage drop VFB2.Moreover, transistor 210 has gate terminal 212 and the end S/D
Threshold voltage V between 216TH.In some embodiments, forward voltage drop VFB1Greater than the threshold voltage V of transistor 210TH。
In some embodiments, diode 232 is configured that when 232 forward bias of diode component and when being connected, and is provided
Discharge path between gate terminal 212 and the end S/D 216, so that voltage VGWith voltage VDBetween voltage difference be reduced to no more than two
The forward voltage drop V of pole pipe device 232FB1.In some embodiments, diode 234 is configured that when 234 forward bias of diode component
When setting and being connected, the discharge path between gate terminal 212 and the end S/D 216 is provided, by voltage VGWith voltage VDBetween electricity
Pressure difference is limited to the forward voltage drop V no more than diode component 234FB2.In some embodiments, as voltage VGWith voltage VDResponse
In signal S3And S4Transformation and when being switched over by the operation of capacitive device 222 and 224,232 He of diode component
234 provide conductive path also to reduce voltage VGWith voltage VDPeak voltage level.
In operation, diode component 232 and 234 is consequently for guaranteeing that the DC value on capacitor 222 is in correct model
So that 210 on or off of transistor in enclosing.
In some embodiments, diode component 232 includes concatenated one or more diodes, and diode component
232 forward voltage drop VFB1For the sum of the forward voltage drop of each of series diode diode.In some embodiments, two
Pole pipe device 234 includes concatenated one or more diodes, and the forward voltage drop V of diode component 234FB2For series connection two
The sum of the forward voltage drop of each of pole pipe diode.
In operation, capacitive device 222 is to driving signal S3Level conversion is carried out, there is big electricity without generating
Press the control signal of the amplitude of oscillation.The component simplifies circuit design and do not needing cost relevant to high-voltage capability
In the case of implement charge pump be possibly realized.The concrete operations of the various components of pump stage circuit 200 are shown in conjunction with Fig. 6.
Fig. 3 is the circuit of the output-stage circuit 300 of the charge pump circuit 100 in accordance with some embodiments that can be used in Fig. 1
Schematic diagram.In Fig. 3 with the same or similar component of the component reference label having the same in Fig. 2, therefore omit its in detail
Description.
Compared with pump stage circuit 200, output-stage circuit 300 does not have control signal end CP and driver 244.Capacitive character device
Part 224 is coupled between output end and power source reference end 310.In some embodiments, power source reference end 310 has connects with reference
Ground voltage level or the corresponding voltage level of 0V level.In some embodiments, power source reference end 310 has and logic low electricity
Put down identical voltage level.
In operation, output-stage circuit 300 stores at capacitive device 224 and keeps the electricity from previous pump stage circuit
Lotus and voltage of the output with scheduled pump voltage level (pumped voltage level) at output end OUT.Output
The capacitance of capacitive device 224 in grade circuit 300 is set as sufficiently large to allow scheduled electric current to export to external electrical
Substantially scheduled pump voltage level is kept while road.
Fig. 4 is that the circuit of the control circuit 400 of the charge pump circuit 100 in accordance with some embodiments that can be used in Fig. 1 shows
It is intended to.
Control circuit 400 includes feedback voltage end 402, reference voltage end 404, power voltage terminal 408, resistive device
412 and 414, comparator 420, signal generating circuit 430 and a plurality of control line 440.In some embodiments, control circuit
400 include clock end 406.
Feedback voltage end 402 is coupled with the output node 104 of charge pump circuit 100.Reference voltage end 404 is configured to receive
With reference voltage level VREFReference voltage.Power voltage terminal 408 is configured to the voltage that carrying has mains voltage level.
In some embodiments, mains voltage level is identical as the first logic high or the second logic high.Resistive device 412
And 414 be coupled in series between power voltage terminal 408 and feedback voltage end 402.Resistive device 412 and 414 is configured to divide
Voltage on output node 104 is converted to feedback voltage by device, which has can be with reference voltage level VREFPhase
The voltage level V comparedFB。
Comparator 420 includes first input end 422, the second input terminal 424 and output end 426.First input end 422 is matched
It is set to and receives reference voltage (with reference voltage level VREF).Second input terminal 424 is configured to receive feedback voltage (with anti-
Feed voltage level VFB).420 comparison reference voltage level V of comparatorREFWith feedback voltage level VFBValue and in output end
Comparison result is generated at 426.
Signal generating circuit 430 coupled with the output end 426 of comparator 420 and with 406 (if present) coupling of clock end
It closes.Signal generating circuit 430 also passes through a plurality of control line 440 and pump stage circuit 110 [1], 110 [2] and 110 [N] and output
Grade circuit 120 couples.Signal generating circuit 430 is configured to receive the comparison result at the output end 426 of comparator 420 and comes from
The clock signal clk of clock end 406, and on a plurality of control line 440 generate control signal SW [1], SW [2], SW [N],
SWF, CP [1], CP [2] and CP [N].In some embodiments, signal generating circuit 430 is additionally configured to receive from clock end
406 clock signal clk.
Control circuit 400 is non-limiting example.Can be used for generating control signal SW [1], SW [2], SW [N], SWF,
The other kinds of control circuit of CP [1], CP [2] and CP [N] are all in the range of each embodiment of the invention, to be based on
Pulse width, frequency or the amplitude information of these signals controls charge pump circuit 100.
Fig. 8 is the exemplary letter of the signal generating circuit 430 in the control circuit in accordance with some embodiments that can be used as Fig. 4
The circuit diagram of number generative circuit 800.
Signal generating circuit 800 includes d type flip flop (DFF) 802 and door 804 and two-phase non-overlapping clock generator 808.
DFF 802 includes input end of clock 806 and comparator input terminal 826.Two-phase non-overlapping clock generator 808 includes the first output
End 810 and second output terminal 812.
DFF 802 is configured to receive clock signal clk at input end of clock 806 and connect at logic input terminal 826
Comparator output is received, for example, the comparison result at output end 426.DFF 802 be based on clock signal clk to comparator export into
Row samples and exports the comparator output of sampling.
It is configured to receive the comparator output of the sampling from DFF 802 and clock signal clk, and Xiang Shuan with door 804
Phase non-overlapping clock generator 808 provides gate output.In response to the logic high of the comparator output of sampling, with door 804
It is configured as output to door controling clock signal.In response to the logic low of the comparator output of sampling, it is configured as output to patrol with door 804
Collect low level.
Two-phase non-overlapping clock generator 808 is configured to receive the door controling clock signal from door 804, and as sound
It answers, the first pulse signal A is created at the first output end 810, and create the second pulse signal B at second output terminal 812.
In some embodiments, the first pulse signal A and the second pulse signal B is used as charge pump control signal SW [i] and CP [i].?
In some embodiments, the first output end 810 and second output terminal 812 are coupled with a plurality of control line 440.
In some embodiments, the first pulse signal A is used as i for the charge pump control signal SW [i] of even number value, and the
Two pulse signal B are used as the charge pump control signal SW [i] that i is odd number value.
In some embodiments, the first pulse signal A is used as i for the charge pump control signal CP [i] of odd number value, and the
Two pulse signal B are used as the charge pump control signal CP [i] that i is even number value.
In operation, as feedback voltage level VFBHigher than reference voltage level VREFWhen, signal generating circuit 800 passes through life
To export in response to comparator at the first pulse signal A and the second pulse signal B, and works as feedback voltage level VFBLower than reference
Voltage level VREFWhen, the signal generating circuit 800 by do not generate the first pulse signal A and the second pulse signal B come in response to
Comparator output.
Signal generating circuit 800 is non-limiting example.Can be used for generating control signal SW [1], SW [2], SW [N],
SWF, CP [1], CP [2] and CP [N] (including do not have with the other kinds of signal generating circuit for controlling charge pump circuit 100
The signal generating circuit of clock signal input) all in the range of each embodiment of the invention.
Fig. 5 A is in the output-stage circuit 300 of the pump stage circuit 200 or Fig. 3 in accordance with some embodiments that can be used as Fig. 2
The circuit diagram of the exemplary diode device 500A of diode component 232 or 234.
Diode component 500A includes anode tap 502, cathode terminal 504 and between anode tap 502 and cathode terminal 504
The J P-type transistor 510 [1] of diode is connected as to 510 [J].J is greater than zero positive integer.When J is greater than 1, P-type crystal
Pipe 510 [1] is to 510 [J] series coupleds.In order to use the configuration based on diode component 500A to implement 232 He of diode component
Diode component 234, diode component 232 are configured to a (J=X) transistors 510 [1] of X for being connected as diode to 510
[X], and diode component 234 is configured to a (J=Y) transistors 510 [1] of Y for being connected as diode to 510 [Y],
Middle X and Y is positive integer.In some embodiments, the forward voltage drop V of diode component 232FB1Just greater than diode component 234
To pressure drop VFB2.Therefore, Y is set smaller than X.
Fig. 5 B is in the output-stage circuit 300 of the pump stage circuit 200 or Fig. 3 in accordance with some embodiments that can be used as Fig. 2
The circuit diagram of the another exemplary diode component 500B of diode component 232 or 234.In Fig. 5 B with the group in Fig. 5 A
The same or similar component of part reference label having the same, therefore omit the detailed description.
Diode component 500B includes that the connection between anode tap 502 and cathode terminal 504 is brilliant for K N-type of diode
Body pipe 520 [1] is to 520 [K].K is greater than zero positive integer.When K is greater than 1, N-type transistor 520 [1] to 520 [K] series connection coupling
It closes.In order to use the configuration based on diode component 500B to implement diode component 232 and diode component 234, diode device
Part 232 is configured to a (K=X) transistors 520 [1] of X for being connected as diode to 520 [X], and diode component 234
It is configured to a (K=Y) transistors 520 [1] of Y for being connected as diode to 520 [Y], wherein X and Y is positive integer.Some
In embodiment, forward voltage drop V that diode component 232 hasFB1Greater than the forward voltage drop V of diode component 234FB2.Therefore, will
Y is set smaller than X.
In some embodiments, implement diode component 232 and diode device based on the configuration of diode component 500A
One in part 234, and implement diode component 232 and diode component 234 based on the configuration of diode component 500B
In another.In some embodiments, with different from diode component 500A and diode component 500B other kinds of
Diode component implements diode component 232 or diode component 234.
Fig. 6 is each of the charge pump circuit 100 in Fig. 1 that combination Fig. 2 to Fig. 4 in accordance with some embodiments is further shown
The timing diagram of voltage level at a node.
In the example shown in Fig. 6, the quantity (that is, digital N in Fig. 1) of pump stage circuit is set as 2, and charge pump electricity
Road is configured to negative charge pump.Voltage level VINIt is set as 0V, and voltage level VOUTIt is set as -2.2V.Show in conjunction with Fig. 1 to Fig. 4
Charge pump circuit out also serves as positive charge pump.The different configuration of charge pump circuit 100 and setting are all of the invention each
In the range of embodiment.
Waveform 602 corresponds to the signal S of the first pump stage circuit 110 [1]1Voltage level.Waveform 604 corresponds to the first pump
The signal S of grade circuit 110 [1]2Voltage level.Waveform 612 corresponds to the voltage V of the first pump stage circuit 110 [1]DVoltage electricity
It is flat.Waveform 614 corresponds to the voltage V of the first pump stage circuit 110 [1]GVoltage level.Waveform 622 corresponds to the second pump stage electricity
The voltage V on road 110 [2]DVoltage level.Waveform 632 corresponds to the voltage V of output-stage circuit 120DVoltage level.
If specifically noted not otherwise, explanation is based primarily upon using the pump stage circuit in Fig. 2 below
The operation of first pump stage circuit 110 [1] of 200 reference label.The crystalline substance of second pump stage circuit 110 [2] and output-stage circuit 120
The transistor 210 and capacitive device 222 of the operation of body pipe 210 and capacitive device 222 and the first pump stage circuit 110 [1]
It operates similar.The capacitive character of the operation of the capacitive device 224 of second pump stage circuit 110 [2] and the first pump stage circuit 110 [1]
The operation of device 224 is similar.Therefore its specific descriptions is omitted.
In this embodiment, signal S1、S2、S3And S4Each of signal all there is 1.8 volts (V) of logically high electricity
The logic low of gentle 0.0V.In some embodiments, signal S1And S3Each of signal all have and signal S2And S4
The different logic high of logic high.In some embodiments, signal S1And S3Each of signal all there is 2.5V
Logic high, and signal S2And S4Each of signal all there is the logic high of 1.8V.
In time T1During the steady-state operation of charge pump circuit 100 before, the signal S of the first pump stage circuit 110 [1]1
(waveform 602) and signal S2(waveform 604) is logic low.Therefore, the signal S3 of the first pump stage circuit 110 [1] (does not show
Out) and signal S4 (not shown) is high level signal.In this example, the voltage V of the first pump stage circuit 110 [1]DIn coming from
0.0V at the input voltage level of power supply or previous pump stage circuit, such as the first pump stage circuit 110 [1].Moreover, at this
In example, the voltage V of the first pump stage circuit 110 [1]GVoltage level be equal to input voltage level add and diode component 232
Forward voltage drop VFB1(such as VFB1) sum.Because of forward voltage drop VFB1It is set greater than the threshold voltage of transistor 210
VTH, so the conducting of transistor 210 is (e.g., to be changed to voltage V in this example by input voltage level for 0.0V)D。
In time T1Place, signal S1(waveform 602) is converted to high logic level from low logic level.Signal S2(waveform 604)
Still in low logic level.Therefore, signal S3(not shown) is converted to low logic level from high logic level, and signal S4(do not show
It out) is still high level signal.By the operation of the capacitive device 222 of the first pump stage circuit 110 [1], in time T1Place, first
The voltage V of pump stage circuit 110 [1]G(waveform 614) is pulled low about 1.8V.Meanwhile first pump stage circuit 110 [1] diode
Device 234 provides discharge path also with by voltage VG(waveform 614) and voltage VD(waveform 612) is pulled to close to each other.As these
The pulling force of opposition as a result, in time T1Place, voltage VG(waveform 614) is from voltage level VFB1It is converted to than voltage level VFB1Subtract
The voltage level of the high several hundred millivolts (mV) of voltage level after 1.8V.The gate terminal of transistor 210 and the S/D of transistor 210
Voltage difference between end is insufficient to allow transistor 210 to be connected.Voltage VD(waveform 612) is still in 0.0V.Therefore, transistor 210
Cut-off.
In time T1Later but in time T2Before, by diode component 234 by voltage VG(waveform 614) and voltage
VD(waveform 612) is pulled to close to each other.Transistor 210 still ends.In some embodiments, time T1With time T2Between when
Between section be arranged to be not enough to voltage VGIt is pulled to sufficiently large so that transistor 210 is in time T2Place's conducting.In some embodiments
In, time T1With time T2Between period it is sufficiently small so that voltage VGThe voltage level or voltage V of (waveform 614)D(waveform
612) voltage level is less than 100mV.
In time T2Place, signal S2(waveform 604) is converted to high logic level from low logic level.Signal S1(waveform 602)
Still in high logic level.Therefore, signal S4(not shown) is converted to low logic level from high logic level, and signal S3(do not show
It out) is still low level signal.By the operation of capacitive device 224, in time T2Place, voltage VD(waveform 612) is pulled low about
1.8V.Meanwhile in this example, pass through another capacitive device (e.g., second of capacitive device 224 and next pump stage circuit
The capacitive device 224 of pump stage circuit 110 [2]) or corresponding output-stage circuit 120 another capacitive device (e.g., output stage
The capacitive device 224 of circuit 120) between share charge, voltage VDIt is also pulled to the steady state output voltage level of the pump stage,
Such as, -1.1V.In some embodiments, also by adjusting control signal SW [1], SW [2], SW [N], SWF, CP [1], CP [2]
With the frequency of CP [N] and/or pass through adjustment signal S4Voltage level control shared charge.Diode component 234 from
Conducting becomes time T when reverse bias2Place, voltage VG(waveform 614) is slightly pulled down.As a result, in time T2Place, voltage VD
The voltage level of the high several hundred mV of the voltage level that (waveform 612) is converted to ratio -1.8V from 0.0V.Transistor 210 still ends.
In time T2Later but in time T3Before, reach its charge after the cut-off of diode component 232 and 234 and put down
After weighing apparatus state, voltage VG(waveform 614) still in about the same voltage level at.Voltage VD(waveform 612) is pulled down,
It then (is in this example e.g., -1.1V) still in steady state output voltage level.In this example, VGVoltage level be greater than VD
Voltage level, but the voltage difference between them be insufficient to allow transistor 210 be connected.Transistor 210 still ends.
In time T3Place, signal S2(waveform 604) is converted to low logic level from high logic level.Signal S1(waveform 602)
Still in high logic level.Therefore, signal S4(not shown) is converted to high logic level from low logic level, and signal S3(do not show
It out) is still low level signal.By the operation of capacitive device 224, in time T3Place, voltage VD(waveform 612) is pulled up about
1.8V.Meanwhile diode component 234 provides discharge path also with by voltage VG(waveform 614) and voltage VD(waveform 612) is pulled to
It is close to each other.As a result, in time T3Place, voltage VD(waveform 612) from steady state output voltage level (e.g., in this example for-
1.1V) it is converted to the voltage level (that is, -1.1V adds 1.8V) of several hundred mV higher than the voltage level of 0.7V.The grid of transistor 210
Voltage difference between end and the end S/D of transistor 210 is insufficient to allow transistor 210 to be connected.Transistor 210 still ends.
In time T3Later but in time T4Before, by diode component 234 by voltage VG(waveform 614) and voltage
VD(waveform 612) is pulled to close to each other.Transistor 210 still ends.In some embodiments, time T3With time T4Between when
Between section it is sufficiently small so that voltage VGThe voltage level or voltage V of (waveform 314)DThe voltage level of (waveform 612) is less than 100mV.
In time T4Place, signal S1(waveform 602) is converted to low logic level from high logic level.Signal S2(waveform 604)
Still in low logic level.Therefore, signal S3(not shown) is converted to high logic level from low logic level, and signal S4(do not show
It out) is still high level signal.By the operation of capacitive device 222, in time T4Place, voltage VG(waveform 614) is pulled up about
1.8V.Meanwhile diode component 232 provides discharge path also with by voltage VG(waveform 614) is pulled to close to voltage VD.As a result,
Time T4Place, voltage VG(waveform 614) is converted to than voltage level VFB1The voltage level of high several hundred mV.The grid of transistor 210
Voltage difference between end and the end S/D 216 is enough that transistor 210 is connected.
In time T4Later but in time T5Before, voltage VD(waveform 612) is pulled down, and then inputs electricity still in stable state
Voltage level (is in this example e.g., 0V), and voltage VG(waveform 614) is pulled down, then still in diode component 232
Forward voltage drop VFB1At stable state input voltage level sum.Transistor 210 is still connected.
In time T5Place starts next operation circulation of pump stage circuit 200.Time T5Corresponding to next operation circulation when
Between T1。
In addition to the corresponding control signal of the second pump stage circuit be with the control signal of the first pump stage circuit 110 [1] not
Except the signal of overlapping, the second pump stage circuit 110 [2] is operated in the mode similar with the first pump stage circuit 110 [1].As a result, pump
The voltage V of grade circuit 110 [2]D(waveform 622) is in time T1To time T4Period is in -1.1V, and in time T4To time T5
Period is pumped (pump) to -2.2V.The transistor 210 of output-stage circuit 120 is with the transistor with the first input stage 110 [1]
210 similar modes work.The capacitive device 224 of output-stage circuit 120 is configured that the transistor when output-stage circuit 120
210 in time T1To time T4When period ends, by voltage VDVoltage level be maintained at -2.2V place.Output-stage circuit 120
Capacitive device 224 is additionally configured to: when the transistor 210 of output-stage circuit 120 is in time T4To time T5When period is connected, connect
Receive the charge of the capacitive device 224 from the second pump stage circuit 110 [2].As a result, the voltage V of output-stage circuit 120DStill protect
It holds at -2.2V.
As shown in Fig. 6 and Fig. 2, pass through the gate terminal of the discharge path and transistor 210 that are provided by diode component 232
212 with the output end of driver 242 (that is, signal S3) between DC isolation, when transistor 210 is connected, gate terminal 212 and S/
The voltage difference between voltage difference and gate terminal 212 and the end S/D 214 between the end D 216 remains approximately diode component 232
Forward voltage drop VFB1.In some embodiments, the forward voltage drop V of diode component 232FB1It is set smaller than logic high
(being such as in this example 1.8V).For the pump stage circuit or output-stage circuit 120 of the rear class of charge pump circuit 100, no matter
How corresponding input voltage level pumps voltage level, and therefore, transistor corresponding with transistor 210, which all has, to be passed through
The forward voltage drop V of diode component 232FB1The end the gate terminal-S/D voltage of adjusting is less than logic when transistor 210 is connected
High level.
Fig. 7 is the flow chart of the method 700 of the pump stage circuit in operation diagram 2 in accordance with some embodiments.As shown in connection with fig. 2
Example illustrate Fig. 7.It should be understood that being executed before, during and/or after the method 700 that can be shown in FIG. 7 additional
Operation, therefore some other processing is only briefly described herein.
Method 700 starts from operation 710, wherein making the of capacitive device in response to the first logical value for controlling signal
Voltage level (the signal S between such as driver 242 and capacitive device 222 of an end portion3) turn from first voltage level
Become second voltage level.In some embodiments, first voltage level corresponds to logic low, and second voltage level is corresponding
In logic high, controls signal and correspond to signal S1And first logical value correspond to logic low value.
Method 700 is carried out to operation 720, wherein in response to the second voltage level at the first end of capacitive device,
Make voltage level (such as voltage V at the second end of capacitive device 222G) it is converted to tertiary voltage level.Capacitive character device
The second end of part 222 and the gate terminal 212 of transistor 210 are electrically coupled.
In some embodiments, operation 710 and 720 is corresponding to the time T in the timing diagram of Fig. 64The signal at place changes.
Method 700 is carried out to operation 730, wherein when the conducting of transistor 210 and 232 forward bias of first diode device
When setting and being connected, the gate terminal 232 of transistor 210 is adjusted by first diode device (such as diode component 232)
First voltage between end source/drain (S/D) 216 is poor.First diode device 232 has the grid with transistor 210
The anode of 212 coupling of end and the cathode coupled with the end S/D 216 of transistor 210.In some embodiments, operation 730 is corresponding
In the timing diagram of Fig. 6 from time T4To time T5Signal transformation.
Method 700 is carried out to operation 740, wherein in response to controlling the second logical value of signal, makes capacitive device 222
First end at voltage level (such as signal S3) from second voltage level transitions be first voltage level.In some implementations
In example, the second logical value corresponds to logic-high value.As a result, making voltage VGIt is converted to be insufficient to allow transistor 210 to be connected the 4th
Voltage level.In some embodiments, operation 740 is corresponding to the time T in the timing diagram of Fig. 61The signal at place changes.
Method 700 is carried out to operation 750, wherein when the conducting of transistor 201 and 234 forward bias of the second diode component
When setting and being connected, adjusted by the second diode component (such as diode component 234) end S/D 216 of transistor 210 with
Second voltage between the gate terminal 212 of transistor 210 is poor.Second diode component 234 has the end S/D with transistor 210
The anode of 216 couplings and the cathode coupled with the gate terminal 212 of transistor 210.In some embodiments, operation 750 is corresponding
In the timing diagram of Fig. 6 from time T1To time T2And/or from time T3To time T4Signal transformation.
In some embodiments, first diode device 232 has forward voltage drop VFB1, the second diode component 234 has
Forward voltage drop VFB2, and forward voltage drop VFB1Greater than forward voltage drop VFB2.Moreover, transistor 210 has gate terminal 212 and the end S/D
Threshold voltage V between 216TH.In some embodiments, forward voltage drop VFB1Greater than the threshold voltage V of transistor 210TH。
In some embodiments, the method that operation 710 to 750 is applicable to the output-stage circuit 300 in operation diagram 3.
Method 700 is carried out to operation 760, wherein in response to another control signal (such as control signal S2), transistor
Voltage level at 210 end S/D 216 is pumped to scheduled pump voltage level.In some embodiments, operation 760 is corresponding
In the timing diagram of Fig. 6 from time T2To time T3Signal transformation.
According to one embodiment, charge pump circuit includes sub-circuit, which is pump stage circuit or output-stage circuit.Son
Circuit includes input, output end, transistor, first capacitor device, first diode device and the second diode component.It is brilliant
Body pipe has the first source/drain (S/D) coupled with input terminal end, the 2nd end S/D coupled with output end and gate terminal.
First capacitor device has the first end coupled with the gate terminal of transistor and is configured to receive the first driving signal
The second end.First diode device have the cathode that is coupled with the 2nd end S/D of transistor and with the gate terminal of transistor
The anode of coupling.Second diode component has the cathode coupled with the gate terminal of transistor and the 2nd S/D with transistor
Hold the anode of coupling.
According to another embodiment, charge pump circuit includes input node, output node, N number of pump stage circuit and output stage
Circuit.N is greater than zero positive integer.Each of N number of pump stage circuit pump stage circuit all includes input terminal and output end.Output
Grade circuit includes input terminal and output end.The input terminal of the first pump stage circuit in N number of pump stage circuit is coupled with input node.N
The input terminal of (n+1) a pump stage circuit in the output end of n-th of pump stage circuit in a pump stage circuit and N number of pump stage circuit
Coupling, wherein n is positive integer and 1≤n≤(N-1).The output end of n-th pump stage circuit in N number of pump stage circuit and output
The input terminal coupling of grade circuit.The output end of output-stage circuit is coupled with output node.One in N number of pump stage circuit further includes
Transistor, first capacitor device, the second capacitive device, first diode device and the second diode component.Transistor
The end the first source/drain (S/D) is included, is coupled with one input node in N number of pump stage circuit；2nd end S/D, and it is N number of
One output node coupling in pump stage circuit；And gate terminal.First capacitor device has the gate terminal with transistor
The first end of coupling and the second end for being configured to the first driving signal of reception.Second capacitive device has and N number of pump
The first end of one output node coupling in grade circuit and the second end for being configured to the second driving signal of reception.The
One diode component has the cathode coupled with the 2nd end S/D of transistor and the anode coupled with the gate terminal of transistor.
Second diode component has the cathode coupled with the gate terminal of transistor and the sun coupled with the 2nd end S/D of transistor
Pole.
According to another embodiment, a kind of method of pump stage circuit or output-stage circuit for operating charge pump circuit is disclosed.
Method includes: the first logical value in response to controlling signal, makes voltage level at the first end of capacitive device from first
Voltage level translation is to second voltage level.Method further include: in response to the second voltage on the first end of capacitive device
Level makes voltage level translation at the second end of capacitive device to tertiary voltage level, the second end of capacitive device
The gate terminal of portion and transistor is electrically coupled；With when transistor turns and first diode device forward bias and when being connected,
It is poor that the first voltage between the gate terminal of transistor and source/drain (S/D) end is adjusted by first diode device.One or two
Pole pipe device has the anode coupled with the gate terminal of transistor and the cathode coupled with the end S/D of transistor.
The component of several embodiments is discussed above, so that the present invention may be better understood in those of ordinary skill in the art
Various aspects.It will be understood by those skilled in the art that can easily using based on the present invention designing or
Other are changed for reaching purpose identical with embodiment described herein and/or realizing the processing and structure of same advantage.This
Field those of ordinary skill it should also be appreciated that this equivalent constructions without departing from the spirit and scope of the present invention, and not
In the case where the spirit and scope of the present invention, a variety of variations can be carried out, replaced and changed.
Claims (18)
1. a kind of charge pump circuit, comprising:
Sub-circuit, the sub-circuit are pump stage circuit or output-stage circuit, and the sub-circuit includes:
Input terminal；
Output end is configured to receive the second driving signal generated based on second control signal；
Transistor, second that there is the first source/drain (S/D) coupled with the input terminal end, coupled with the output end
Source/drain terminal and gate terminal；
First capacitor device, has the first end that couple with the gate terminal of the transistor and is configured to receive and be based on the
The second end for the first driving signal that one control signal generates；
First diode device, have the cathode that is coupled with the second source/drain terminal of the transistor and with the crystal
The anode of the gate terminal coupling of pipe；With
Second diode component has the cathode coupled with the gate terminal of the transistor and the second source with the transistor
Pole/drain electrode end coupling anode；
Control circuit is configured to generate the first control signal and the second control signal, and the control circuit includes:
Divider is configured to the voltage of the output of the charge pump circuit being converted to feedback voltage；
Comparator is configured to the numerical value of feedback voltage and reference voltage described in comparison；With
Signal generator is configured to receive the output and clock signal of the comparator, generates the first control signal and institute
Second control signal is stated,
Wherein, the first diode device has forward voltage drop, and second diode component has forward voltage drop, and institute
The forward voltage drop for stating first diode device is greater than the forward voltage drop of second diode component.
2. charge pump circuit according to claim 1, wherein the sub-circuit is the pump stage circuit, the sub-circuit
Further include:
Second capacitive device has the first end coupled with the output end of the sub-circuit and is configured to receive institute
State the second end of the second driving signal.
3. charge pump circuit according to claim 2,
Wherein, the sub-circuit further include:
First driver is configured to the first control signal to generate first driving signal；And
Second driver is configured to the second control signal to generate second driving signal.
4. charge pump circuit according to claim 3, in which:
First driver be configured to make first driving signal in first voltage level corresponding with logic-high value and
Switch between reference voltage level corresponding with logic low value；And
Second driver is configured to make second driving signal in second voltage electricity corresponding with the logic-high value
Switch between gentle reference voltage level corresponding with the logic low value, the first voltage level and the second voltage
Level is different.
5. charge pump circuit according to claim 1, in which:
The first diode device includes X transistor for being connected as diode, and X is the positive integer greater than zero, and when X is big
When 1, the X transistor for being connected as diode is connected in series；And
Second diode component includes Y transistor for being connected as diode, and Y is the positive integer greater than zero and less than X,
And when Y is greater than 1, the Y transistor for being connected as diode is connected in series.
6. charge pump circuit according to claim 1, in which:
The first diode device has forward voltage drop；
The transistor has threshold voltage；And
The forward voltage drop of the first diode device is greater than the threshold voltage of the transistor.
7. charge pump circuit according to claim 1, wherein the transistor is N-type transistor.
8. a kind of charge pump circuit, comprising:
Input node；
Output node；
N number of pump stage circuit, N are the positive integer greater than zero, and each of described N number of pump stage circuit pump stage circuit all includes:
Input terminal；With
Output end；And
Output-stage circuit, including input terminal and output end；
Control circuit is configured to generate multiple control signal, and the control circuit includes:
Divider is configured to the voltage at the output node being converted to feedback voltage；
Comparator is configured to the numerical value of feedback voltage and reference voltage described in comparison；With
Signal generator is configured to receive the output and clock signal of the comparator, generates the multiple control signal,
Wherein,
The input terminal of the first pump stage circuit in N number of pump stage circuit is coupled with the input node；
(n+1) a pump in the output end of n-th of pump stage circuit in N number of pump stage circuit and N number of pump stage circuit
The input terminal coupling of grade circuit, n is positive integer and 1≤n≤(N-1)；
The output end of n-th pump stage circuit in N number of pump stage circuit is coupled with the input terminal of the output-stage circuit；
The output end of the output-stage circuit is coupled with the output node；With
One in N number of pump stage circuit further include:
Transistor, the transistor includes the end the first source/drain (S/D), defeated with one in N number of pump stage circuit
Enter end coupling；Second source/drain terminal is coupled with one output end in N number of pump stage circuit；And gate terminal；
First capacitor device has the first end coupled with the gate terminal of the transistor and is configured to receive based on institute
State the second end for the first driving signal that the first control signal in multiple control signal generates；
Second capacitive device has the first end coupled with one output end in N number of pump stage circuit and matches
It is set to the second end for receiving the second driving signal generated based on the second control signal in the multiple control signal；
First diode device, have the cathode that is coupled with the second source/drain terminal of the transistor and with the crystal
The anode of the gate terminal coupling of pipe；And
Second diode component has the cathode coupled with the gate terminal of the transistor and the second source with the transistor
Pole/drain electrode end coupling anode,
Wherein, the first diode device has forward voltage drop, and second diode component has forward voltage drop, and institute
The forward voltage drop for stating first diode device is greater than the forward voltage drop of second diode component.
9. charge pump circuit according to claim 8, further includes:
Wherein, one in N number of pump stage circuit further include:
First driver, the first control signal being configured in the multiple control signal are driven to generate described first
Dynamic signal；And
Second driver, the second control signal being configured in the multiple control signal are driven to generate described second
Dynamic signal.
10. charge pump circuit according to claim 9, in which:
First driver includes the first phase inverter；And
Second driver includes the second phase inverter.
11. charge pump circuit according to claim 9, in which:
First driver be configured to make first driving signal in first voltage level corresponding with logic-high value and
Switch between reference voltage level corresponding with logic low value；And
Second driver is configured to make second driving signal in second voltage electricity corresponding with the logic-high value
Switch between gentle reference voltage level corresponding with the logic low value, the first voltage level and the second voltage
Level is different.
12. charge pump circuit according to claim 8, in which:
The first diode device includes X transistor for being connected as diode, and X is the positive integer greater than zero, and when X is big
When 1, the X transistor for being connected as diode is connected in series；And
Second diode component includes Y transistor for being connected as diode, and Y is the positive integer greater than zero and less than X,
And when Y is greater than 1, the Y transistor for being connected as diode is connected in series.
13. charge pump circuit according to claim 8, in which:
The first diode device has forward voltage drop；
The transistor has threshold voltage；And
The forward voltage drop of the first diode device is greater than the threshold voltage of the transistor.
14. charge pump circuit according to claim 8, wherein the transistor is N-type transistor.
15. charge pump circuit according to claim 8, in which:
The input node is configured to receive reference voltage；And
The output node is configured as output to pump voltage, and the voltage level of the pump voltage is electric lower than the voltage of the reference voltage
It is flat.
16. a kind of method for the pump stage circuit or output-stage circuit for operating charge pump circuit, which comprises
In response to controlling the first logical value of signal, keep the voltage level at the first end of capacitive device electric from first voltage
Flat turn fades to second voltage level；
In response to the second voltage level at the first end of the capacitive device, make the second end of the capacitive device
The voltage level translation at place is to tertiary voltage level, the second end of the capacitive device and the gate terminal thermocouple of transistor
It closes；And
When the transistor turns and first diode device forward bias and when being connected, pass through the first diode device
The first voltage that part is adjusted between the gate terminal of the transistor and the first source/drain (S/D) end is poor, the first diode
Device has the anode that couples with the gate terminal of the transistor and couples with the first source/drain terminal of the transistor
Cathode, wherein the first source/drain terminal of the transistor is coupled at the output node of the charge pump circuit,
Wherein, forward voltage drop of the first voltage difference based on the first diode device, the first diode device are adjusted
The forward voltage drop of part is greater than the forward voltage drop of the second diode component, and second diode component has and the transistor
The cathode of gate terminal coupling and the anode coupled with the first source/drain terminal of the transistor,
Wherein, generating the method for controlling signal includes:
Voltage at the output node of the charge pump circuit is converted into feedback voltage；
Compare the numerical value of the feedback voltage and reference voltage to generate comparison result；With
The comparison result and clock signal are received, the control signal is generated.
17. according to the method for claim 16, further includes:
When the transistor cutoff and the second diode component forward bias and when being connected, pass through the two or two pole
The second voltage that tube device is adjusted between the first source/drain terminal of the transistor and gate terminal is poor.
18. according to the method for claim 17, in which:
The first diode device has forward voltage drop；
The transistor has threshold voltage；And
The forward voltage drop of the first diode device is greater than the threshold voltage of the transistor.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US14/956,061 US11611276B2 (en) | 2014-12-04 | 2015-12-01 | Charge pump circuit |
| US14/956,061 | 2015-12-01 |
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| Publication Number | Publication Date |
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| CN106817021A CN106817021A (en) | 2017-06-09 |
| CN106817021B true CN106817021B (en) | 2019-09-13 |
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| CN111752329B (en) * | 2019-03-29 | 2022-11-18 | 恩智浦美国有限公司 | Reverse bias adjustment system and method for integrated circuits |
| CN114844348B (en) * | 2021-02-02 | 2024-05-10 | 圣邦微电子（北京）股份有限公司 | Power supply circuit, display panel and display device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6023188A (en) * | 1996-11-05 | 2000-02-08 | Aplus Flash Technology, Inc. | Positive/negative high voltage charge pump system |
| CN1187884C (en) * | 1999-09-27 | 2005-02-02 | 英特尔公司 | Method and apparatus for reducing stress across capacitors used in integrated circuits |
| US6864739B2 (en) * | 2001-04-05 | 2005-03-08 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
| CN102468747A (en) * | 2010-11-19 | 2012-05-23 | 无锡芯朋微电子有限公司 | Charge pump control circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104811034B (en) * | 2015-05-29 | 2017-07-11 | 聚辰半导体(上海)有限公司 | It is adapted to the simple charge pump circuit of low voltage operating |
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Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6023188A (en) * | 1996-11-05 | 2000-02-08 | Aplus Flash Technology, Inc. | Positive/negative high voltage charge pump system |
| CN1187884C (en) * | 1999-09-27 | 2005-02-02 | 英特尔公司 | Method and apparatus for reducing stress across capacitors used in integrated circuits |
| US6864739B2 (en) * | 2001-04-05 | 2005-03-08 | Saifun Semiconductors Ltd. | Charge pump stage with body effect minimization |
| CN102468747A (en) * | 2010-11-19 | 2012-05-23 | 无锡芯朋微电子有限公司 | Charge pump control circuit |
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