CN106815411B - Modeling method for layout proximity effect of multi-interdigital MOS device - Google Patents
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Abstract
The invention provides a modeling method for layout proximity effect of a multi-interdigital MOS device, which comprises the following steps: designing a test structure, wherein the test structure comprises a reference device group and a comparison device group used for establishing a grid spacing layout proximity effect model; establishing an initial model of the multi-interdigital device without the layout proximity effect based on the test data of the reference device, and modeling by adopting the parallel connection of a plurality of single-gate MOS devices, wherein the number of the single-gate devices is equal to the fork index; constructing a characteristic dimension based on layout factors related to grid spacing layout proximity effects of each multi-interdigital MOS device, taking the characteristic dimension as a layout factor of a single-gate device in an initial model, and equivalently representing the sum of the grid spacing layout proximity effects introduced by all interdigital devices by using the sum of the layout proximity effects introduced by all the parallel single-gate devices based on the layout factor; and constructing a threshold voltage and mobility correction model according to the characteristic size, the width and the length of a single finger and the number of fingers to correct the initial model.
Description
Technical Field
The invention relates to the technical field of semiconductor device modeling, in particular to a modeling method of an adjacent effect model of a multi-interdigital MOS device layout.
Background
With the continuous development of the CMOS technology, new materials and new technologies are continuously developed and applied, and the process nodes are continuously advanced. As the process dimensions are further scaled down, the influence of device fluctuation caused by process fluctuation on the circuit performance and reliability is more and more serious. How to suppress device fluctuations and accurately characterize the device fluctuations to provide a reference for integrated circuit design and optimization is an important issue that needs to be addressed urgently.
There are many factors that affect the process fluctuation, and the Layout Proximity Effect (LPE) is one of the more prominent problems in the advanced process. In order to improve or match the carrier mobility of the MOS device and improve the switching speed of the device, various stress engineering technologies such as an embedded germanium-silicon technology, a stress memory technology and the like are introduced into the deep nano MOSFET. Meanwhile, Shallow Trench Isolation (STI) also brings compressive stress to the device channel, which affects carrier mobility. With the difference of the layout size and the surrounding environment of the device, the stress in the channel can change, so that the performance of the device has layout correlation. Layout factors introducing layout proximity effect are many, wherein the gate proximity effect pse (poly space effect) caused by adjacent gate spacing and adjacent gate number is an important factor causing the threshold voltage and drain current of the device to change.
In view of the above problems, the industry has developed a more sophisticated process for the gate proximity effect of single gate devices. However, in the integrated circuit design, a multi-interdigital device is inevitably used, dummy poly introduced outside the device and the distance between gates inside the device all affect the device performance, the environment around each gate may be different, and a challenge is provided for accurately representing the change of the device performance caused by the layout factor change.
Disclosure of Invention
In order to overcome the problems, the invention aims to provide a modeling method for the grid proximity effect of a multi-interdigital MOS device, which accurately reflects the influence of the grid proximity effect introduced by related layout factors on the performance of the device by equivalently representing the proximity effect of all grids of the multi-interdigital device and provides reference for the optimal design of a layout.
In order to achieve the above object, the present invention provides a modeling method for layout proximity effect of a multi-finger MOS device, which includes:
step 01: designing a series of test structures, wherein the test structures comprise a reference device group and a comparison device group used for establishing a grid spacing layout proximity effect model;
step 02: establishing an initial model of the multi-interdigital device without the layout proximity effect based on the test data of the reference device, and modeling by adopting the parallel connection of a plurality of single-gate MOS devices, wherein the number of the single-gate devices is equal to the fork index;
step 03: constructing a feature size based on layout factors related to grid spacing layout proximity effects of each multi-interdigital MOS device, taking the constructed feature size as a layout factor of a single-gate device in an initial model, and equivalently representing the sum of the grid spacing layout proximity effects introduced by all interdigital devices of the multi-interdigital device by using the sum of the layout proximity effects introduced by all the parallel single-gate devices based on the layout factor;
step 04: and constructing a threshold voltage and mobility correction model according to the characteristic size, the width and the length of a single finger and the number of fingers to correct the initial model.
Preferably, in step 01, the designing a series of test structures specifically includes: firstly, determining the ranges of the width and the length of a grid of an MOS device under corresponding process conditions; then, designing a group of reference devices with different interdigital numbers for MOS devices with different sizes; and then transforming the characteristic size of each reference device to generate a group of contrast devices.
Preferably, the number of contrast device structures in a set generated is no less than three.
Preferably, in step 03, the layout factors related to the gate pitch layout proximity effect of the adopted multi-finger MOS device include: in the layout of the multi-interdigital MOS device, two grids at the leftmost side and two grids at the rightmost side are pseudo grids, and the characteristic dimension comprises the following steps: the distance between the two grids at the leftmost side of one interdigital is the second grid distance at the left side, the distance between the two grids at the leftmost side is the first grid distance at the left side, the distance between the two grids at the rightmost side is the second grid distance at the right side, and the distance between the two grids at the rightmost side is the first grid distance at the right side.
Preferably, in step 03, after equivalently representing the sum of layout proximity effects of gate pitches introduced by all the fingers of the multi-finger device by using the sum of layout proximity effects introduced by all the parallel single-gate devices, the obtained equivalent feature size includes: a left first equivalent pitch, a right first equivalent pitch, a left second equivalent pitch, and a right second equivalent pitch; the construction method of the left first equivalent spacing is that the number of the fingers is divided by the sum of reciprocal left first grid spacings of all the fingers, the construction method of the right first equivalent spacing is that the number of the fingers is divided by the sum of reciprocal right first grid spacings of all the fingers, the construction method of the left second equivalent spacing is that the number of the fingers is divided by the sum of reciprocal left second grid spacings of all the fingers, and the construction method of the right second equivalent spacing is that the number of the fingers is divided by the sum of reciprocal right second grid spacings of all the fingers.
Preferably, the step 04 specifically includes: constructing a correction model of threshold voltage variation and carrier mobility variation caused by grid spacing layout proximity effect according to the extracted feature size, the width and length of a single interdigital and the number of the interdigital; and then, extracting parameters of the corrected model to correct the initial model.
Preferably, extracting the modified model parameters comprises: based on the designed test structures, test values of threshold voltages and saturation currents of the test structures are obtained.
Preferably, the modifying the initial model specifically includes: the threshold voltage of the reference devices with different numbers of interdigital is compared with the variation value of the threshold voltage of the comparison device, the saturation current of the reference devices with different numbers of interdigital is compared with the variation value of the saturation current of the comparison device, the extracted correction model parameters are fitted, and therefore the test value of the threshold voltage is matched with the simulated value of the threshold voltage in the corrected model, and the test value of the saturation current is matched with the simulated value of the saturation current in the corrected model.
Preferably, the process of modifying the initial model is iterated cyclically such that the test values of the threshold voltages of the devices of the respective sizes match the simulated values of the threshold voltages in the modified model and the test values of the saturation currents match the simulated values of the saturation currents in the modified model.
Preferably, the MOS devices employed include large-size devices, narrow-channel devices, short-channel devices, and small-size devices.
According to the modeling method for the gate proximity effect of the multi-interdigital MOS device, the constructed device characteristic size comprehensively considers the surrounding environment of all gates, and the method can adapt to the change of device performance caused by the change of all layout factors. The constructed threshold voltage and mobility correction model introduces a function changing along with the number of the interdigital to model parameters of devices with different sizes based on the width and the length of a grid electrode of a single-grid device and the number of the interdigital, and further improves the model accuracy.
Drawings
FIG. 1 is a flow chart of a modeling method according to a preferred embodiment of the present invention
FIG. 2 is a schematic diagram of a layout of a multi-interdigital MOS device
Detailed Description
In order to make the contents of the present invention more comprehensible, the present invention is further described below with reference to the accompanying drawings. The invention is of course not limited to this particular embodiment, and general alternatives known to those skilled in the art are also covered by the scope of the invention.
The present invention will be described in further detail with reference to the accompanying drawings 1-2 and specific embodiments. It should be noted that the drawings are in a simplified form and are not to precise scale, and are only used for conveniently and clearly achieving the purpose of assisting in describing the embodiment.
As mentioned above, the nanoscale manufacturing process may bring influence of layout dependency to the MOS device, and for influence of gate layout proximity effect on device performance of the multi-finger device, MOS device modeling needs to comprehensively consider the peripheral condition of the MOSFET, and implement modeling on the adjacent layout factors. Wherein the device performance is significantly affected by variations in device stress due to variations in the spacing between adjacent gates. For a single interdigital device, the influence caused by the adjacent first and second polysilicon gates is generally considered. For a multi-interdigital device, the situation is more complicated, and the surrounding environment, namely layout factors, of each gate may be different. For modeling of a multi-finger device, the parallel connection of single-gate MOS devices with the same number of fingers is generally adopted, so that the influence of layout proximity effect brought by different gates is also required to be averaged and substituted into each equivalent single-gate device model to represent the total device performance.
Therefore, in order to adapt to layout proximity effect of a multi-finger MOS device, the present embodiment provides a modeling method for layout proximity effect of a multi-finger MOS device, please refer to fig. 1, where the modeling method includes:
step 01: designing a series of test structures, wherein the test structures comprise a reference device group and a comparison device group used for establishing a grid spacing layout proximity effect model;
specifically, designing a series of test structures specifically includes: firstly, determining the ranges of the width and the length of a grid of an MOS device under corresponding process conditions; then, designing a group of reference devices with different interdigital numbers for MOS devices with different sizes; and then transforming the characteristic size of each reference device to generate a group of contrast devices. The layout factor dimension of the reference device related to the layout proximity effect is a typical dimension determined under the process condition to enable the device to have the best performance, and is generally the minimum dimension defined by the layout design rule. The comparison device group is obtained by converting layout factors related to the layout proximity effect by the reference device group. The number of contrast device structures generated for each reference device here is not less than three.
Step 02: establishing an initial model of the multi-interdigital device without the layout proximity effect based on the test data of the reference device, and modeling by adopting the parallel connection of a plurality of single-gate MOS devices, wherein the number of the single-gate devices is equal to the fork index;
step 03: constructing a feature size based on layout factors related to grid spacing layout proximity effects of each multi-interdigital MOS device, taking the constructed feature size as a layout factor of a single-gate device in an initial model, and equivalently representing the sum of the grid spacing layout proximity effects introduced by all interdigital devices of the multi-interdigital device by using the sum of the layout proximity effects introduced by all the parallel single-gate devices based on the layout factor;
specifically, referring to fig. 2, in the layout of the multi-finger MOS device in this embodiment, the number of fingers is four, the width of each gate is wf, the length is l, the gate pitch of the device is sd, two gates at the leftmost side and two gates at the rightmost side of the device are dummy gates (dummy poly), and layout factors related to the gate pitch layout proximity effect include: the gate-to-gate distance between one interdigital and the leftmost gate is the second left gate pitch pcl2, the gate-to-gate distance between the interdigital and the leftmost gate is the first left gate pitch pcl1, the gate-to-gate distance between the interdigital and the rightmost gate is the second right gate pitch pcr2, and the gate-to-gate distance between the interdigital and the rightmost gate is the first right gate pitch pcr 1. The adopted MOS devices comprise large-size devices, narrow-channel devices, short-channel devices and small-size devices, specifically, in the characteristic size of the structure, the construction method of a first equivalent spacing pcl1eff on the left side is the sum of the number of the interdigital fingers divided by the reciprocal of the first grid spacing on the left side of all the interdigital, the construction method of a first equivalent spacing pcr1eff on the right side is the sum of the number of the interdigital fingers divided by the reciprocal of the first grid spacing on the right side of all the interdigital, the construction method of a second equivalent spacing pcl2eff on the left side is the sum of the number of the interdigital fingers divided by the reciprocal of the second grid spacing on the left side of all the interdigital, and the construction method of a second equivalent spacing pcr2eff on the right side is the sum of the number of the interdigital fingers divided by the reciprocal of the second grid spacing on the right; the new feature size is established using the following formula:
pcl1 in the above formulamiDistance to the left of the mi poly from the first gate, pcr1miDistance to the right of mi poly from the first gate, pcl2miDistance to the left of mi poly from the second gate, pcr2miThe distance to the right of the mi-th poly from the second gate. For the devices with the example fork index nr 4 shown in fig. 2, pci 1_ m1 pcl1, pcl2_ m1 pcl2, pcr1_ m1 sd, pcr2_ m1 2 sd + l; pci 1_ m2 ═ sd, pci 2_ m2 ═ sd + l + pci 1, pcr1_ m2 ═ sd, and pcr2_ m2 ═ 2 ═ sd + l; pci 1_ m3 ═ sd, pci 2_ m3 ═ 2 × sd + l, pcr1_ m3 ═ sd, and pcr2_ m1 ═ sd + l + pcr 1; pci 1_ m4 ═ sd, pci 2_ m4 ═ 2 × sd + l, pcr1_ m4 ═ pcr1, and pcr2_ m4 ═ pcr 2.
Step 04: and constructing a threshold voltage and mobility correction model according to the characteristic size, the width and the length of a single finger and the number of fingers to correct the initial model.
Specifically, a formula correction threshold voltage and mobility model is constructed based on the characteristic dimensions, so that the influence of the grid spacing layout proximity effect on the device performance is represented.
vth＝vth0+Δvthpse
u＝u0*ueffpse，
Wherein vth0, u0The threshold voltage and mobility of the reference device are determined according to the process conditions, and the reference device refers to a typical device with the best performance, and the sd, pci 1, pci 2, pcr1 and pcr2 of the reference device are designed according to the minimum rule allowed by the process design. pcl1effrefThe pcr1effref, the pcr2effref and the pcr2effref are the corresponding feature sizes of the reference device, and the feature size of the reference device is related to the number nr of the fingers. Δ vthpseUsed for correcting the variation, ueff, of the threshold voltage of the device after the layout factor is changedpseFor correcting the variation ratio of the device mobility, we use wf, l, nr, and feature size as input in the above formula, and kpsvth01 dnv1kpsvth02 dnv2 kpsu01 dnu1 kpsu02 dnu2 and its different size-related bin parameters are model parameters. Such as: for the model parameter a, the width-related bin parameter is wa, the length-related bin parameter is la, and the width-length simultaneous-related bin parameter is pa.
In step 04 of this embodiment, the method specifically includes: constructing a correction model of threshold voltage variation and saturation mobility variation caused by grid spacing layout proximity effect according to the extracted feature size, the width and length of a single interdigital and the number of the interdigital; and then, extracting parameters of the corrected model to correct the initial model. Specifically, the extracting of the corrected model parameter includes: extracting the modified model parameters includes: based on the designed test structures, test values of threshold voltages and saturation currents of the test structures are obtained.
The step of modifying the initial model specifically includes: the threshold voltage of the reference devices with different numbers of interdigital is compared with the variation value of the threshold voltage of the comparison device, the saturation current of the reference devices with different numbers of interdigital is compared with the variation value of the saturation current of the comparison device, the extracted correction model parameters are fitted, and therefore the test value of the threshold voltage is matched with the simulated value of the threshold voltage in the corrected model, and the test value of the saturation current is matched with the simulated value of the saturation current in the corrected model.
And circularly iterating the correction process of the initial model, so that the test value of the threshold voltage of each size of device is matched with the simulated value of the threshold voltage in the corrected model, and the test value of the saturation current is matched with the simulated value of the saturation current in the corrected model.
For example, to extract the model parameters, a corresponding test structure is designed and tested for threshold voltage and saturation current. The test structure is designed by first determining the maximum and minimum range of variation of devices wf, l within the model coverage, determining the size of large devices wfmax, lmax, and designing a set of reference devices of different finger numbers for large devices, such as nr 2, 4, 8. And generating a group of contrast device structures by converting the layout factor sizes (sd, pcl1, pcl2, pcr1 and pcr2) of each reference device, wherein the number of the generated contrast device structures is not less than 3. For other size devices such as short channel devices (wfmax, lmin), narrow channel devices (wfmin, lmax), and small devices (wfmin, lmin), reference devices and comparison devices are also generated according to the above method.
The threshold voltage and the saturation current value of all the reference devices are tested, the threshold voltage and the saturation current change value of the reference devices with different numbers of fingers and the comparison devices are compared for large-size devices, the threshold voltage test value is matched with the model simulation value by fitting kpsvth01 dnv1kpsvth02 dnv2 parameters, and the saturation current test value is matched with the model simulation value by fitting kpsu01, dnu1, kpsu02 and dnu2 parameters. Fitting the l-related bin parameter corresponding to the parameter for the short-channel device, fitting the w-related bin parameter corresponding to the parameter for the narrow-channel device, and fitting the l-and w-related bin parameters corresponding to the parameter for the small-size device according to the method, so that the voltage and saturation current test values of the threshold are matched with the simulated value. And the process is iterated circularly, so that the threshold voltage and drain current test values and simulation values of the devices with different sizes are optimally matched.
Although the present invention has been described with reference to preferred embodiments, it is to be understood that the present invention is not limited to the disclosed embodiments, but rather, may be embodied in many different forms and modifications without departing from the spirit and scope of the present invention as defined by the appended claims.
Claims (7)
1. A modeling method for layout proximity effect of a multi-interdigital MOS device is characterized by comprising the following steps:
step 01: designing a series of test structures, wherein the test structures comprise a reference device group and a comparison device group used for establishing a grid spacing layout proximity effect model; the reference device group comprises a plurality of reference devices, the comparison device group comprises a plurality of comparison devices, and the reference devices and the comparison devices are MOS devices;
step 02: establishing an initial model of the multi-interdigital device without the layout proximity effect based on the test data of the reference device, and modeling by adopting the parallel connection of a plurality of single-gate MOS devices, wherein the number of the single-gate devices is equal to the fork index;
step 03: constructing an equivalent feature size based on layout factors related to grid spacing layout proximity effects of each multi-interdigital MOS device, taking the constructed equivalent feature size as a layout factor of a single-gate device in an initial model, and equivalently representing the sum of the grid spacing layout proximity effects introduced by all the interdigital devices of the multi-interdigital device by using the sum of the layout proximity effects introduced by all the parallel single-gate devices based on the equivalent feature size;
step 04: constructing a threshold voltage and mobility correction model according to the equivalent characteristic size, the width and the length of a single interdigital and the number of the interdigital to correct the initial model; the method specifically comprises the following steps: constructing a correction model of threshold voltage variation and carrier mobility variation caused by grid spacing layout proximity effect according to the extracted feature size, the width and length of a single interdigital and the number of the interdigital; then, extracting parameters of a correction model to correct the initial model; wherein, extracting the modified model parameters comprises: acquiring a test value of threshold voltage and a test value of saturation current of the test structures based on the designed test structures; the step of modifying the initial model specifically includes: the threshold voltage of the reference devices with different numbers of interdigital is compared with the variation value of the threshold voltage of the comparison device, the saturation current of the reference devices with different numbers of interdigital is compared with the variation value of the saturation current of the comparison device, the extracted correction model parameters are fitted, and therefore the test value of the threshold voltage is matched with the simulated value of the threshold voltage in the corrected model, and the test value of the saturation current is matched with the simulated value of the saturation current in the corrected model.
2. The modeling method of claim 1, wherein in step 01, designing a series of test structures specifically comprises: firstly, determining the ranges of the width and the length of a grid of an MOS device under corresponding process conditions; then, designing a group of reference devices with different interdigital numbers for MOS devices with different sizes; and then, the layout factor of each reference device is transformed to generate a group of comparison devices.
3. A modeling method in accordance with claim 2, wherein the number of contrast device structures generated is not less than three.
4. The modeling method according to claim 1, wherein in step 03, the layout factors related to the gate pitch layout proximity effect of the adopted multi-finger MOS device include: in the layout of the multi-interdigital MOS device, two grids at the leftmost side and two grids at the rightmost side are pseudo grids, and the characteristic dimension comprises the following steps: the distance between the two grids at the leftmost side of one interdigital is the second grid distance at the left side, the distance between the two grids at the leftmost side is the first grid distance at the left side, the distance between the two grids at the rightmost side is the second grid distance at the right side, and the distance between the two grids at the rightmost side is the first grid distance at the right side.
5. The modeling method according to claim 1, wherein in the step 03, after equivalently representing the sum of the layout proximity effects of the gate pitches introduced by all the fingers of the multi-finger device by using the sum of the layout proximity effects introduced by all the parallel single-gate devices, the obtained equivalent feature sizes include: a left first equivalent pitch, a right first equivalent pitch, a left second equivalent pitch, and a right second equivalent pitch; wherein,
the construction method of the left first equivalent spacing is that the number of the fingers is divided by the sum of the left first reciprocal grid spacings of all the fingers, the construction method of the right first equivalent spacing is that the number of the fingers is divided by the sum of the right first reciprocal grid of all the fingers, the construction method of the left second equivalent spacing is that the number of the fingers is divided by the sum of the left second reciprocal grid of all the fingers, and the construction method of the right second equivalent spacing is that the number of the fingers is divided by the sum of the right second reciprocal grid of all the fingers.
6. A method as claimed in claim 1, wherein the process of modifying the initial model is iterated cyclically such that the test values of the threshold voltages of the devices of respective sizes match the simulated values of the threshold voltages in the modified model and the test values of the saturation currents match the simulated values of the saturation currents in the modified model.
7. The modeling method of claim 1, wherein the MOS devices employed include large-size devices, narrow-channel devices, short-channel devices, and small-size devices.
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101685478A (en) * | 2008-09-26 | 2010-03-31 | 恩益禧电子股份有限公司 | Circuit simulation based on gate spacing from adjacent mos transistors |
| CN101788760A (en) * | 2009-01-23 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Optimization method of optical proximity correction rule |
| CN105760604A (en) * | 2016-02-19 | 2016-07-13 | 上海集成电路研发中心有限公司 | Modeling method for statistic model based on territory proximity effect |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007093861A (en) * | 2005-09-28 | 2007-04-12 | Renesas Technology Corp | Method for designing mask pattern, and method for manufacturing semiconductor device |
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2016
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Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101685478A (en) * | 2008-09-26 | 2010-03-31 | 恩益禧电子股份有限公司 | Circuit simulation based on gate spacing from adjacent mos transistors |
| CN101788760A (en) * | 2009-01-23 | 2010-07-28 | 中芯国际集成电路制造(上海)有限公司 | Optimization method of optical proximity correction rule |
| CN105760604A (en) * | 2016-02-19 | 2016-07-13 | 上海集成电路研发中心有限公司 | Modeling method for statistic model based on territory proximity effect |
Non-Patent Citations (2)
| Title |
|---|
| 40nm_MOSFET版图邻近效应模型的研究和建立;朱诗倩;《中国优秀硕士学位论文全文数据库信息科技辑》;20151015;第2015年卷(第10期);第I135-58页 * |
| A systematic study of layout proximity effects for 28nm Poly/SiON logic technology;Ruoyuan Li 等;《2015 China Semiconductor Technology International Conference》;20150316;第1-4页 * |
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