CN106815411B - Modeling method for layout proximity effect of multi-interdigital MOS device - Google Patents

Abstract

The invention provides a modeling method for layout proximity effect of a multi-interdigital MOS device, which comprises the following steps: designing a test structure, wherein the test structure comprises a reference device group and a comparison device group used for establishing a grid spacing layout proximity effect model; establishing an initial model of the multi-interdigital device without the layout proximity effect based on the test data of the reference device, and modeling by adopting the parallel connection of a plurality of single-gate MOS devices, wherein the number of the single-gate devices is equal to the fork index; constructing a characteristic dimension based on layout factors related to grid spacing layout proximity effects of each multi-interdigital MOS device, taking the characteristic dimension as a layout factor of a single-gate device in an initial model, and equivalently representing the sum of the grid spacing layout proximity effects introduced by all interdigital devices by using the sum of the layout proximity effects introduced by all the parallel single-gate devices based on the layout factor; and constructing a threshold voltage and mobility correction model according to the characteristic size, the width and the length of a single finger and the number of fingers to correct the initial model.

Description

A Modeling Method for Layout Proximity Effect of Multi-finger MOS Devices

technical field

The invention relates to the technical field of semiconductor device modeling, in particular to a modeling method for a proximity effect model of a layout of a multi-finger MOS device.

Background technique

With the continuous development of CMOS technology, new materials and new technologies are constantly being developed and applied, which promotes the continuous advancement of process nodes. As process dimensions are further scaled down, device fluctuations caused by process fluctuations have an increasingly serious impact on circuit performance and reliability. How to suppress device fluctuation and accurately characterize device fluctuation to provide reference for integrated circuit design and optimization are important issues that need to be solved urgently.

There are many factors that affect process fluctuation, among which the layout proximity effect (LPE) is one of the more prominent problems in advanced processes. In order to improve or match the carrier mobility of MOS devices and improve the switching speed of the device, various stress engineering technologies have been introduced into deep nano MOSFETs, such as embedded germanium silicon technology, stress memory technology, etc. At the same time, Shallow Trench Isolation (STI: Shallow Trench Isolation) also brings compressive stress to the device channel, which affects the carrier mobility. The stress in the channel varies with device layout size and surrounding environment, making device performance layout dependent. There are many layout factors that introduce layout proximity effect. Among them, the gate proximity effect (PSE) caused by the distance between adjacent gates and the number of adjacent gates is an important factor that leads to the variation of device threshold voltage and drain current.

In view of the above problems, the industry already has a relatively mature solution for the gate proximity effect of single-gate devices. However, it is inevitable to use multi-fingered devices in integrated circuit design. The dummy poly introduced outside the device and the distance between the gate and the gate of the device will affect the performance of the device. The environment around each gate will affect the performance of the device. may vary, posing a challenge to accurately characterize the changes in device performance caused by the aforementioned layout factor changes.

SUMMARY OF THE INVENTION

In order to overcome the above problems, the present invention aims to provide a method for modeling the gate proximity effect of a multi-finger MOS device, which can accurately reflect the gate proximity introduced by the relevant layout factors by equivalently characterizing the proximity effect of all gates of the multi-finger MOS device. The effect of the effect on the performance of the device is also provided as a reference for the optimal design of the layout.

In order to achieve the above object, the present invention provides a method for modeling the proximity effect of a multi-finger MOS device layout, which includes:

Step 01: Design a series of test structures, including a reference device set and a comparative device set for establishing a proximity effect model of gate pitch layout;

Step 02: establish an initial model of the multi-interdigital device without layout proximity effect based on the reference device test data, and use the parallel connection of multiple single-gate MOS devices for modeling, and the number of single-gate devices is equal to the fork index;

Step 03: Construct the feature size based on the layout factor related to the proximity effect of the gate pitch layout of each multi-interdigitated MOS device, and take the constructed feature size as the layout factor of the single-gate device in the initial model. Based on the layout factor, use all The sum of the layout proximity effect introduced by the parallel single-gate device is equivalent to the sum of the layout proximity effect of the gate pitch introduced by all the fingers of the multi-finger device;

Step 04: Construct threshold voltage and mobility correction models according to the feature size, the width, length and number of fingers of a single finger to correct the initial model.

Preferably, in step 01, it is characterized in that designing a series of test structures specifically includes: first, determining the range of gate width and length of the MOS device under corresponding process conditions; then, designing a set of different MOS devices for different sizes Interdigitated reference devices; the feature size of each reference device is then transformed to generate a set of comparison devices.

Preferably, the number of the generated set of comparative device structures is not less than three.

Preferably, in step 03, the adopted layout factors related to the proximity effect of the gate pitch layout of the multi-digit MOS device include: in the layout of the multi-digit MOS device, the two gates on the far left and the two gates on the far right include: The root gate is a dummy gate, and the feature size includes: the distance between the gates of one interdigital distance from the leftmost gate is the distance between the second gates on the left, and the distance between the gates from the second to last gate on the leftmost is the first grid spacing on the left, the grid spacing from the rightmost grid is the second grid spacing on the right, and the grid spacing from the penultimate grid from the rightmost grid is the first grid spacing on the right .

Preferably, in the step 03, the equivalent feature obtained after the sum of the layout proximity effects introduced by all the single-gate devices in parallel is used to represent equivalently the sum of the grid spacing layout proximity effects introduced by all the interdigitated devices of the multi-digit device The dimensions include: the first equivalent distance on the left, the first equivalent distance on the right, the second equivalent distance on the left, and the second equivalent distance on the right; wherein, the construction method of the first equivalent distance on the left is fork index The quantity is divided by the sum of the reciprocals of the left first grid spacing of all the fingers, and the construction method of the right first equivalent spacing is the number of fingers divided by the sum of the inverses of the right first grid spacing of all the fingers, and the second grid spacing on the left. The construction method of equivalent spacing is the number of fingers divided by the sum of the reciprocals of the left second grid spacing of all fingers, and the construction method of the second equivalent spacing on the right is the number of fingers divided by the reciprocal of the second grid spacing on the right of all fingers Sum.

Preferably, the step 04 specifically includes: constructing the threshold voltage variation and carrier migration due to the proximity effect of the gate spacing layout according to the extracted feature size, the width, length and number of fingers of a single finger The modified model of the rate change; then, the modified model parameters are extracted to modify the initial model.

Preferably, the extracting and correcting model parameters includes: based on the designed test structures, acquiring test values of threshold voltages and test values of saturation currents of these test structures.

Preferably, revising the initial model specifically includes: by comparing the threshold voltages of the reference devices with different numbers of fingers and the change values of the threshold voltages of the comparison devices, and comparing the saturation currents of the reference devices with different numbers of fingers with the comparison device's saturation currents The change value of the saturation current is compared to fit the extracted modified model parameters, so that the test value of the threshold voltage matches the simulated value of the threshold voltage in the modified model, so that the test value of the saturation current is the same as that in the modified model. to match the simulated value of the saturation current.

Preferably, the process of revising the initial model is cyclically iterated, so that the test value of the threshold voltage of the devices of each size matches the simulated value of the threshold voltage in the revised model, and the test value of the saturation current matches the revised model. to match the simulated value of the saturation current.

Preferably, the MOS devices employed include large-scale devices, narrow-channel devices, short-channel devices and small-scale devices.

In the method for modeling the gate proximity effect of a multi-finger MOS device of the present invention, the constructed device feature size comprehensively considers the surrounding environment of all gates, and can adapt to changes in device performance brought about by changes in all layout factors. The constructed threshold voltage and mobility correction model is based on the gate width and length of the single-gate device and the number of fingers. The model parameters of different sizes of devices are introduced with a function of the number of fingers, which further improves the accuracy of the model.

Description of drawings

1 is a schematic flowchart of a modeling method according to a preferred embodiment of the present invention

Figure 2 is a schematic diagram of the layout of a multi-finger MOS device

Detailed ways

In order to make the content of the present invention clearer and easier to understand, the content of the present invention will be further described below with reference to the accompanying drawings. Of course, the present invention is not limited to this specific embodiment, and general substitutions known to those skilled in the art are also covered within the protection scope of the present invention.

The present invention will be further described in detail below with reference to the accompanying drawings 1-2 and specific embodiments. It should be noted that, the accompanying drawings are in a very simplified form and use inaccurate scales, and are only used to facilitate and clearly achieve the purpose of assisting the description of the present embodiment.

As mentioned above, the nano-scale manufacturing process will bring the influence of layout correlation to MOS devices. For the influence of the gate layout proximity effect on the device performance of multi-interdigitated devices, MOS device modeling requires a comprehensive analysis of MOSFETs. The surrounding situation is considered, and the adjacent layout factors are modeled. Among them, the change of device stress caused by the change of adjacent gate spacing has a significant impact on the device performance. For a single interdigitated device, it is usually necessary to consider the influence of the adjacent first and second polysilicon gates. For multi-interdigital devices, the situation is more complicated, and the surrounding environment that each gate faces, ie, the layout factor, may be different. For the modeling of multi-fingered devices, we usually use the parallel connection of single-gate MOS devices with the same number of fingers, so the influence of the layout proximity effect caused by different gates should also be averaged and substituted into each equivalent single-gate device. model, which characterizes the overall device performance.

Therefore, in order to adapt to the layout proximity effect of the multi-fingered device, this embodiment provides a modeling method for the layout proximity effect of the multi-interdigitated MOS device, please refer to FIG. 1 , and the modeling method includes:

Step 01: Design a series of test structures, including a reference device set and a comparative device set for establishing a proximity effect model of gate pitch layout;

Specifically, designing a series of test structures specifically includes: first, determining the range of gate width and length of the MOS device under corresponding process conditions; then, designing a set of reference devices with different numbers of fingers for MOS devices of different sizes; The feature size of each reference device is transformed to generate a set of comparison devices. The size of the layout factor of the reference device related to the layout proximity effect is the typical size determined under the process conditions to make the device have the best performance, which is generally the minimum size defined by the layout design rules. The comparison device group is obtained by transforming the layout factor related to the layout proximity effect by the reference device group. Here, the number of comparative device structures generated for each reference device is not less than three.

Step 02: establish an initial model of the multi-interdigital device without layout proximity effect based on the reference device test data, and use the parallel connection of multiple single-gate MOS devices for modeling, and the number of single-gate devices is equal to the fork index;

Step 03: Construct the feature size based on the layout factor related to the proximity effect of the gate pitch layout of each multi-interdigitated MOS device, and take the constructed feature size as the layout factor of the single-gate device in the initial model. Based on the layout factor, use all The sum of the layout proximity effect introduced by the parallel single-gate device is equivalent to the sum of the layout proximity effect of the gate pitch introduced by all the fingers of the multi-finger device;

Specifically, please refer to FIG. 2. In the layout of the multi-fingered MOS device in this embodiment, the number of fingers is four, the width of each gate is wf, the length is l, the gate spacing of the device is sd, and the most The two gates on the left and the two gates on the far right are dummy poly gates. The layout factors related to the proximity effect of the gate pitch layout include: one interdigit distance between the gates of the leftmost gate The distance is the second grid spacing pcl2 on the left, the grid-to-grid distance from the penultimate grid on the left is the first grid spacing on the left pcl1, and the grid-to-grid distance from the grid on the right is the grid spacing on the right. The second grid spacing pcr2, the grid spacing from the second to last grid on the far right is the first grid spacing pcr1 on the right. The MOS devices used include large-sized devices, narrow-channel devices, short-channel devices and small-sized devices. Specifically, in the feature size of the structure, the construction method of the first equivalent distance pcl1eff on the left is the number of fingers divided by all the The sum of the reciprocals of the first grid spacing on the left side of the fingers, the first equivalent spacing on the right side pcr1eff The construction method is the number of fingers divided by the sum of the reciprocals of the first grid spacing on the right side of all fingers, and the second equivalent spacing on the left side The construction method of pcl2eff is the number of fingers divided by the reciprocal sum of the left second grid spacing of all fingers, and the construction method of the right second equivalent spacing pcr2eff is the number of fingers divided by the reciprocal of the second grid spacing on the right side of all fingers and; the formula used to establish the new feature size is as follows:

In the above formula, pcl1 _mi is the distance from the left side of the mi-th poly to the first gate, pcr1 _mi is the distance from the right side of the mi-th poly to the first gate, and pcl2 _mi is the distance from the left side of the mi-th poly to the second gate. The distance of the grid, pcr2 _mi is the distance from the right side of the mi-th poly to the second grid. For the device with the sample cross index nr=4 shown in Figure 2, pcl1_m1=pcl1, pcl2_m1=pcl2, pcr1_m1=sd, pcl2_m1=2*sd+l; pcl1_m2=sd, pcl2_m2=sd+l+pcl1, pcr1_m2=sd , pcl2_m2=2*sd+l; pcl1_m3=sd, pcl2_m3=2*sd+l, pcr1_m3=sd, pcr2_m1=sd+l+pcr1; pcl1_m4=sd, pcl2_m4=2*sd+l, pcr1_m4=pcr1, pcr2_m4 =pcr2.

Step 04: Construct threshold voltage and mobility correction models according to the feature size, the width, length and number of fingers of a single finger to correct the initial model.

Specifically, threshold voltage and mobility models are modified based on the above feature size construction formula, so as to characterize the influence of the proximity effect of gate spacing layout on device performance.

vth=vth0+Δvth _pse

u=u ₀ *ueff _pse ,

Where vth0, u ₀ are the threshold voltage and mobility of the reference device, respectively, the reference device refers to the typical device with the best performance determined under the process conditions, usually the sd, pcl1, pcl2, pcr1, pcr2 of the reference device are designed according to the process Minimum rule design allowed. pcl1effref, pcr1effref, pcl2effref, and pcr2effref are the feature sizes corresponding to the reference device, and the feature size of the above-mentioned reference device is related to the fork index nr. Δvth _pse is used to correct the change in the threshold voltage of the device after the layout factor changes, and ueff _pse is used to correct the change ratio of the device mobility. In the above formula, wf, l, nr, and feature size are used as inputs, kpsvth01 dnv1 kpsvth02 dnv2, kpsu01 , dnu1, kpsu02, dnu2 and their bin parameters related to different sizes are model parameters. For example, for the model parameter a, the width-related bin parameter is wa, the length-related bin parameter is la, and the width-length related bin parameter is pa.

Step 04 of this embodiment specifically includes: constructing the threshold voltage variation and saturation mobility due to the proximity effect of the gate pitch layout according to the extracted feature size, the width, length and number of fingers of a single finger The modified model of the variation; then, the modified model parameters are extracted to modify the initial model. Specifically, extracting and correcting model parameters includes: extracting and correcting model parameters includes: obtaining test values of threshold voltages and test values of saturation currents of these test structures based on the designed test structures.

The correction of the initial model specifically includes: by comparing the threshold voltage of the reference device with different numbers of fingers and the change value of the threshold voltage of the comparison device, and comparing the saturation current of the reference device with different numbers of fingers and the saturation current of the comparison device. The change values are compared to fit the extracted modified model parameters, so that the test value of the threshold voltage matches the simulated value of the threshold voltage in the modified model, so that the test value of the saturation current matches the saturation current in the modified model. match the simulated values.

The above process of revising the initial model is looped and iterated, so that the test value of the threshold voltage of the device of each size matches the simulation value of the threshold voltage in the revised model, and the test value of the saturation current matches the saturation current in the revised model. match the simulated values.

For example, in order to extract the above model parameters, a corresponding test structure is designed and the test values of its threshold voltage and saturation current are tested. The design method of the test structure is to first determine the maximum and minimum range of the changes of the devices wf and l within the coverage of the model, determine the size of the large device wfmax, lmax, and design a set of reference devices with different numbers of fingers for the large device, such as nr=2 , 4, 8. For each reference device, a set of comparison device structures is generated by transforming the above layout factor size (sd, pcl1, pcl2, pcr1, pcr2), and the number of generated comparison device structures should be no less than 3. For other size devices such as short-channel devices (wfmax, lmin), narrow-channel devices (wfmin, lmax), and small devices (wfmin, lmin), reference devices and comparison devices are also generated according to the above method.

Test the threshold voltage and saturation current values of all the above reference devices. First, compare the threshold voltage and saturation current changes of reference devices with different number of fingers and comparison devices for large-size devices. By fitting the parameters of kpsvth01 dnv1 kpsvth02 dnv2 To match the model simulation value, fit the kpsu01, dnu1, kpsu02, dnu2 parameters to make the saturation current test value match the model simulation value. According to the above method, the l-related bin parameters corresponding to the above parameters are fitted for short-channel devices, the w-related bin parameters corresponding to the above parameters are fitted for narrow-channel devices, and the l and w-related bin parameters corresponding to the above parameters are fitted for small-sized devices. Match the threshold voltage and saturation current test values to the simulated values. And iterate this process in a loop, so that the threshold voltage and drain current test values and simulation values of devices of various sizes can be optimally matched.

Although the present invention has been disclosed above with preferred embodiments, the embodiments are merely examples for the convenience of description, and are not intended to limit the present invention. Those skilled in the art can make several modifications without departing from the spirit and scope of the present invention. Changes and modifications, the scope of protection claimed by the present invention shall be subject to the claims.

Claims (7)

1. A modeling method for layout proximity effect of a multi-interdigital MOS device is characterized by comprising the following steps:

step 01: designing a series of test structures, wherein the test structures comprise a reference device group and a comparison device group used for establishing a grid spacing layout proximity effect model; the reference device group comprises a plurality of reference devices, the comparison device group comprises a plurality of comparison devices, and the reference devices and the comparison devices are MOS devices;

step 02: establishing an initial model of the multi-interdigital device without the layout proximity effect based on the test data of the reference device, and modeling by adopting the parallel connection of a plurality of single-gate MOS devices, wherein the number of the single-gate devices is equal to the fork index;

step 03: constructing an equivalent feature size based on layout factors related to grid spacing layout proximity effects of each multi-interdigital MOS device, taking the constructed equivalent feature size as a layout factor of a single-gate device in an initial model, and equivalently representing the sum of the grid spacing layout proximity effects introduced by all the interdigital devices of the multi-interdigital device by using the sum of the layout proximity effects introduced by all the parallel single-gate devices based on the equivalent feature size;

step 04: constructing a threshold voltage and mobility correction model according to the equivalent characteristic size, the width and the length of a single interdigital and the number of the interdigital to correct the initial model; the method specifically comprises the following steps: constructing a correction model of threshold voltage variation and carrier mobility variation caused by grid spacing layout proximity effect according to the extracted feature size, the width and length of a single interdigital and the number of the interdigital; then, extracting parameters of a correction model to correct the initial model; wherein, extracting the modified model parameters comprises: acquiring a test value of threshold voltage and a test value of saturation current of the test structures based on the designed test structures; the step of modifying the initial model specifically includes: the threshold voltage of the reference devices with different numbers of interdigital is compared with the variation value of the threshold voltage of the comparison device, the saturation current of the reference devices with different numbers of interdigital is compared with the variation value of the saturation current of the comparison device, the extracted correction model parameters are fitted, and therefore the test value of the threshold voltage is matched with the simulated value of the threshold voltage in the corrected model, and the test value of the saturation current is matched with the simulated value of the saturation current in the corrected model.

2. The modeling method of claim 1, wherein in step 01, designing a series of test structures specifically comprises: firstly, determining the ranges of the width and the length of a grid of an MOS device under corresponding process conditions; then, designing a group of reference devices with different interdigital numbers for MOS devices with different sizes; and then, the layout factor of each reference device is transformed to generate a group of comparison devices.

3. A modeling method in accordance with claim 2, wherein the number of contrast device structures generated is not less than three.

4. The modeling method according to claim 1, wherein in step 03, the layout factors related to the gate pitch layout proximity effect of the adopted multi-finger MOS device include: in the layout of the multi-interdigital MOS device, two grids at the leftmost side and two grids at the rightmost side are pseudo grids, and the characteristic dimension comprises the following steps: the distance between the two grids at the leftmost side of one interdigital is the second grid distance at the left side, the distance between the two grids at the leftmost side is the first grid distance at the left side, the distance between the two grids at the rightmost side is the second grid distance at the right side, and the distance between the two grids at the rightmost side is the first grid distance at the right side.

5. The modeling method according to claim 1, wherein in the step 03, after equivalently representing the sum of the layout proximity effects of the gate pitches introduced by all the fingers of the multi-finger device by using the sum of the layout proximity effects introduced by all the parallel single-gate devices, the obtained equivalent feature sizes include: a left first equivalent pitch, a right first equivalent pitch, a left second equivalent pitch, and a right second equivalent pitch; wherein,

the construction method of the left first equivalent spacing is that the number of the fingers is divided by the sum of the left first reciprocal grid spacings of all the fingers, the construction method of the right first equivalent spacing is that the number of the fingers is divided by the sum of the right first reciprocal grid of all the fingers, the construction method of the left second equivalent spacing is that the number of the fingers is divided by the sum of the left second reciprocal grid of all the fingers, and the construction method of the right second equivalent spacing is that the number of the fingers is divided by the sum of the right second reciprocal grid of all the fingers.

6. A method as claimed in claim 1, wherein the process of modifying the initial model is iterated cyclically such that the test values of the threshold voltages of the devices of respective sizes match the simulated values of the threshold voltages in the modified model and the test values of the saturation currents match the simulated values of the saturation currents in the modified model.

7. The modeling method of claim 1, wherein the MOS devices employed include large-size devices, narrow-channel devices, short-channel devices, and small-size devices.

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