Background technology
Mobile wireless interface satellite mobile communication agreement based on geostationary orbit is from third generation affiliate
Mesh (3GPP, the 3rd Generation Partnership Project) ground digital cellular standards, can be with seamless access
Global mobile communication system/general GSM (GSM, Global System for Mobile Communication/
UMTS, Universal Mobile Telecommunications System) core net.GMR satellite communication protocols extensively should
In ACeS, ICO, Inmarsat, SkyTerra, TerreStar and Thuraya satellite mobile communication system.
Check that the information for receiving has inerrancy for ease of recipient, can typically use CRC.If circulation is superfluous
Remaining check code (CRC, Cyclic Redundancy Check) code word size is N, and information field is K, and check field is R
(N=K+R), as shown in figure 1, any code word then concentrated for CRC code, has and only exist R order polynomial g (D), make
:
T (D)=A (D) g (D)=DRm(D)+r(D)
Wherein:M (D) is K message polynomial, and r (D) is R check polynomial, and g (D) is referred to as generator polynomial:
G (D)=gRDR+g(R-1)D(R-1)+...+g2D2+g1D+g0
In GMR satellite mobile communication systems, using following 5 kinds of CRCs, its generator polynomial is respectively:
g3(D)=D3+D+1
g5(D)=D5+D3+D2+D+1
g8(D)=D8+D7+D4+D3+D+1
g12(D)=D12+D11+D3+D2+D+1
g16(D)=D16+D12+D5+1。
In conventional recycle redundancy check Calculative Process, typically using polynomial division operation, now above-mentioned 5 kinds of circulations
Redundancy check code generator polynomial is respectively necessary for being represented using 4,6,9,13 and 17 bits.
Current GMR satellite mobile communications mainly process (DSP, Digital Signal using 16 position digital signals
Processing) calculating cyclic redundancy check code is calculated, to realize the miniaturization of terminal system.For generator polynomial g16Come
Say, if still using polynomial division calculating cyclic redundancy check code, need the register ability that two length is 16 bits
Preserve, now register effective rate of utilization is only 53% (i.e. 17/32 × 100%=53%), causes the pole of register resources
It is big to waste.If by generator polynomial g16Storage in both registers, is using 16 bit DSP calculating cyclic redundancy check codes
When, it is necessary to be 32 bit informations by the transmission Data expansion that length is 17 bits and with this be respectively 16 bits with two length
Check polynomial carries out xor operation, so that xor operation increased by about one time.
The content of the invention
To solve the problems, such as that prior art register resources utilization rate is low or xor operation is computationally intensive, the present invention is provided
CRC computational methods and device based on GMR satellite communication protocols.
Mobile wireless interface GMR satellite mobile communication system CRC of the present invention based on geostationary orbit
CRC computational methods, including:
S1, initialization length are the register B of R;
S2, the kth bit information calculating status indicator value C using first bit information of register B and information field;
S3, to register B carry out move 1 bit manipulation, the room produced by displacement with 0 fill;
S4, register B is updated according to status indicator value C;
S5, the kth+1 for reading information field, repeat S2-S5, until all bit informations of information field are disposed,
The value of register B is final CRC output valves.
Register B's is initialized as value for full 0 in step S1;
Preferably, using the kth position bit information meter of first bit information of register B and information field described in step S2
Status indicator value C is calculated, including:XOR is carried out using the kth position bit information of first bit information of register B and information field
Computing obtains status indicator value C.
Preferably, it is described to be included according to status indicator value C renewals register B:
If status indicator value C is 1, by register B and remaining bits g1Deposited after carrying out XOR same bits position
Return the bit of register B;The remaining bits g1It is that CRC generator polynomials are divided into the first bit g0Length is the surplus of R afterwards
Remaining bit.
Preferably, using the kth position bit information meter of first bit information of register B and information field described in step S2
Status indicator value C is calculated, including:XOR is carried out using the kth position bit information of first bit information of register B and information field
Computing obtains state median C ', and state median C ' and CRC generator polynomials are divided into the first bit g0, then carry out XOR fortune
Calculation obtains status indicator value C.
Preferably, it is described to be included according to status indicator value C renewals register B:
If status indicator value C is 0, by register B and remaining bits g1Deposited after carrying out XOR same bits position
Return the bit of register B;The remaining bits g1It is that CRC generator polynomials are divided into the first bit g0Length is the surplus of R afterwards
Remaining bit.
Preferably, move 1 bit manipulation including carrying out moving to left 1 bit manipulation to register B to register B described in step S3.
Mobile wireless interface GMR satellite mobile communication system CRC of the present invention based on geostationary orbit
CRC computing devices, including:
Register, length is R, for storing check field;
Information field reading unit, the bit information for reading information field by bit, readout register B first
Bit information;
Status indicator value computing unit, for the kth position bit using first bit information of register B and information field
Information calculates status indicator value C;
Register shift control unit, for carrying out moving to left 1 bit manipulation to register B, the room produced by displacement uses 0
Filling;
Register updates control unit, and register B is updated according to status indicator value C.
Preferably, the status indicator value computing unit, for using first bit information of register B and information field
Kth position bit information calculate status indicator value C, including using the kth position of first bit information of register B and information field
Bit information carries out XOR and obtains status indicator value C;
The register updates control unit, and register B, including if status indicator value C are updated according to status indicator value C
It is 1, then by register B and remaining bits g1Same bits position be stored back to after XOR the bit of register B;It is described
Remaining bits g1It is that CRC generator polynomials are divided into the first bit g0Length is the remaining bits of R afterwards;
Alternatively, the status indicator value computing unit, for using first bit information of register B and information field
Kth position bit information calculate status indicator value C, including using the kth position of first bit information of register B and information field
Bit information carries out XOR and obtains state median C ', by state median C ' and the first bit of CRC generator polynomials
g0XOR is carried out again obtains status indicator value C;
The register updates control unit, and register B, including if status indicator value C are updated according to status indicator value C
It is 0, then by register B and remaining bits g1Same bits position be stored back to after XOR the bit of register B;It is described
Remaining bits g1It is that CRC generator polynomials are divided into the first bit g0Length is the remaining bits of R afterwards.
The present invention makes full use of 16 fixed DSP digital signal processing State variable informations, by GMR satellite communications system
System CRC generator polynomials are divided into first bit information and remaining bits information, using manipulation in situ mode, first using register B
First bit value calculates status indicator value with the individual bit sequentially input from a high position, and then register B is carried out to move to left 1 behaviour
Make, deposit is updated with the XOR value condition of CRC generator polynomial remaining bits using register B further according to the status indicator value
Device B, when all input bits are all by after above-mentioned calculating, bit is final CRC output valves in register B.
Compared with prior art, the present invention uses register bit In situ FTIRS mode, reduces to greatest extent to deposit
Device number demand, is particularly suitable for that, in 16 bit DSP systematic differences, in the case, register resources utilization rate from 53% can be made
Bring up to 100%.
Specific embodiment
In order to make the purpose , technical scheme and advantage of the present invention be clearer, below in conjunction with accompanying drawing to of the invention real
Apply example further description.
CRC computational methods of the present invention based on GMR satellite communication protocols, enter only with the left and right order corresponding with definition
Row description, specifically includes following steps, as shown in Figure 2:
GMR satellite communication system CRC generator polynomials g points is the first bit g by the embodiment of the present invention0It is R's with length
Remaining bits g1.I other words, CRC generator polynomials g is expressed as two sequences, i.e. g=[g0g1], wherein g0=1, g1It is remainder
Length for R bit sequence.
S1, initialization length are the register B of R;
Alternatively, the initialization value of register B can be random number, but used as more excellent mode, length be R (R=3,5,
8,12,16) register B, initialization bit value is full 0.
Initialization input information field subscript k=1, that is, postpone most input bits, and k-th of the information field of reading is defeated
Enter bit and be expressed as I (k), k=1,2 ..., K, K are information field length.
S2, the kth bit information calculating status indicator value C using first bit information of register B and information field;
The length of the status indicator value C is 1 bit.In 16 bit DSP systems, status indicator value C can be marked with overflowing
Sensible correspondence.
As a kind of preferred embodiment (be labeled as mode S2A), described first bit information of use register B and information word
The kth position bit information of section calculates status indicator value C to be included, the kth position ratio of first bit information of register B and information field
Special information carries out XOR and obtains status indicator value C, i.e.,:
C=xor (I (k), B (1)) (formula 1)
Wherein I (k) represents k-th input bit of information field, and B (1) represents the first bit value of register B, and xor is represented
Xor operation.
Alternatively (be labeled as mode S2B), described first bit information of use register B and information word
The kth position bit information of section calculates status indicator value C, including:Using the of first bit information of register B and information field
K bit information carries out XOR and obtains state median C ', by state median C ' and the bit of CRC generator polynomials first
g0Carry out XOR and obtain status indicator value C;I.e.:
C=xor (xor (I (k), B (1)), g0) (formula 2)
Wherein, g0=1.
S3, to register B carry out move 1 bit manipulation, the room produced by displacement with 0 fill;
It is described to register B move 1 bit manipulation including carrying out moving to left 1 bit manipulation to register B;
Register moves to left 1, can be expressed as:
B=[B (2:R) 0] (formula 3)
Wherein 2:R represents the 2,3rd of reading register B ..., R bit is stored in the 1,2nd of register B ..., R-1 ratios
Special position, produces the R bit to be filled using 0 because of displacement.
S4, register B is updated according to status indicator value C;
It is corresponding to aforesaid way S2A, if status indicator value C is 1, by register B and remaining bits g1Mutually on year-on-year basis
Special position be stored back to after XOR the bit of register B;The remaining bits g1It is that CRC generator polynomials are divided into
One bit g0Length is the remaining bits of R afterwards;
It is corresponding to aforesaid way S2B, if status indicator value C is 0, by register B and remaining bits g1Mutually on year-on-year basis
Special position be stored back to after XOR the bit of register B;The remaining bits g1It is that CRC generator polynomials are divided into
One bit g0Length is the remaining bits of R afterwards.
Register updates can be expressed as:
B=xor (B, g1) (formula 4)
Wherein, g1It is that the length not comprising CRC generator polynomials head bits is R bit sequences, that is, using register B
And g1XOR value be assigned to register B again.
S5, the kth+1 for reading information field, repeat S2-S5, until all bit informations of information field are disposed,
The value of register B is final CRC output valves.
It will be the information I and generator polynomial g of K by length that the final purpose of CRC is, calculate residual polynomial r, this hair
It is bright by K iteration, what is finally retained in B is exactly CRC output valves, and original information I need not be exported.
CRC calculating process register bit information change of the present invention is described in detail below, as shown in Figure 3.Work as life
G is taken into multinomial16(D) when, g1(when taking other production multinomials, CRC calculating process is complete for=[0,001 0,000 0,010 0001]
It is exactly the same), the length of register B is 16, is initialized as B=[B (1), B (2) ..., B (16)]=[0,0 ..., 0];Read kth
Individual information bit I (k), with the 1st bit B (1) of register and the first bit of CRC generator polynomials g0, using preferred embodiment
Formula 1 calculates status indicator value C using optional mode formula 2;Register B is carried out to move 1 bit manipulation, is exactly by register B
The 2,3rd ..., 16 and 0 totally 16 bits constitute new register value B;Register B is updated using the condition of formula 4, it is also possible to represent
g1The 4,11,16th bit carry out XOR with the corresponding delay position of register B and shift.View of the above, it will be seen that
The original position that the calculating of whole CRC check bit is all based on register B is calculated, so as to save the resource of register.
In 16 bit DSP instruction systems, status indicator value C generally as register hidden shadow bit (Shadow bit), with operation
Instruction automatically updates status indicator value C.In 16 bit DSP systems, many instruction direct basis status indicator value C are used as execution bar
Part, the correlation functions such as register renewal are performed in order to condition.
CRC computing device of the present invention based on GMR satellite communication protocols is described below, as shown in figure 4, including:
Register B, length is R, for storing check field;
Information field reading unit, bit information I (k) for reading information field by bit;
Status indicator value computing unit, for the kth position bit using first bit information of register B and information field
Information calculates status indicator value C;
Register shift control unit, for carrying out moving to left 1 bit manipulation to register B, the room produced by displacement uses 0
Filling;
Register updates control unit, and register B is updated according to status indicator value C.
As a kind of achievable mode, the status indicator value computing unit, for using first bit letter of register B
The kth position bit information of breath and information field calculates status indicator value C, including using first bit information of register B and letter
The kth position bit information of breath field carries out XOR and obtains status indicator value C;
The register updates control unit, and register B, including if status indicator value C are updated according to status indicator value C
It is 1, then by register B and remaining bits g1Same bits position be stored back to after XOR the bit of register B;It is described
Remaining bits g1It is that CRC generator polynomials are divided into the first bit g0Length is the remaining bits of R afterwards.
As the achievable mode of another kind, the status indicator value computing unit, for using register first bit of B
Information and information field kth position bit information calculate status indicator value C, including using first bit information of register B with
The kth position bit information of information field carries out XOR and obtains state median C ', state median C ' and CRC is generated many
First bit g of item formula0XOR is carried out again obtains status indicator value C;
The register updates control unit, and register B, including if status indicator value C are updated according to status indicator value C
It is 0, then by register B and remaining bits g1Same bits position be stored back to after XOR the bit of register B;It is described
Remaining bits g1It is that CRC generator polynomials are divided into the first bit g0Length is the remaining bits of R afterwards.
The implementation of each part can be quoted mutually with method implementation in apparatus of the present invention, be repeated no more.
The present invention uses register bit In situ FTIRS mode, reduces to greatest extent to register number demand.This hair
It is bright 3, the dsp system of 5,8,12,16 can be applicable, and be particularly suitable in 16 bit DSP systematic differences, in this situation
Under, register resources utilization rate can be made to bring up to 100% (i.e. 16/16* from 53% (i.e. 17/32 × 100%=53%)
100%).
The object, technical solutions and advantages of the present invention have been carried out further detailed description, institute by embodiment provided above
It should be understood that embodiment provided above is only the preferred embodiment of the present invention, be not intended to limit the invention, it is all
Any modification, equivalent substitution and improvements made for the present invention etc., should be included in the present invention within the spirit and principles in the present invention
Protection domain within.