CN106783888B - Display screen, control method thereof and display device - Google Patents
Display screen, control method thereof and display device Download PDFInfo
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
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Abstract
The invention discloses a display screen, a control method thereof and a display device, and belongs to the technical field of display. The display screen includes: display panel and control circuit, the thin-film transistor in the array substrate among the display panel includes: the control circuit is respectively connected with a target grid and an auxiliary grid in the n grids, and is used for inputting a first off-state voltage to the target grid in an off-state time period and inputting a second off-state voltage to the auxiliary grid in the off-state time period, so that a target PN junction is formed in the active layer under the action of the voltages on the n grids, and the forward conduction direction of the target PN junction is opposite to the current flowing direction in a region except the region where the target PN junction is located in the active layer. The invention solves the problem that the TFT can not be normally used, realizes the effect that the TFT can be normally used, and is used for the display screen.
Description
Technical Field
The invention relates to the technical field of display, in particular to a display screen, a control method thereof and a display device.
Background
The display screen comprises a display panel and an Array substrate line driver (GOA) circuit, wherein the display panel comprises an Array substrate and a color film substrate which are formed in a box-to-box mode, and liquid crystal located between the Array substrate and the color film substrate. The array substrate comprises a substrate and a plurality of Thin Film Transistors (TFTs) formed on the substrate and arranged in an array.
In the related art, the thin film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer, wherein the gate electrode, the electrode and the drain electrode are made of metal, and the active layer is made of a semiconductor type carbon nanotube. When the voltage applied to the gate electrode reaches an on-state voltage (generally greater than a threshold voltage), the active layer conducts the source electrode and the drain electrode, at the moment, the TFT is in an on state, the current in the TFT is large, and a data signal on the source electrode can be transmitted to the drain electrode; when the voltage applied to the gate electrode is an off-state voltage (generally less than a threshold voltage), the active layer cannot turn on the source electrode and the drain electrode, the TFT is in an off-state, the current in the TFT is small, and a data signal on the source electrode cannot be transmitted to the drain electrode.
However, when the TFT using the semiconductor type carbon nanotube as the active layer covers the inorganic passivation layer, bipolar conduction of carriers in the active layer is more likely to occur (i.e., the carriers are electrons at a large positive voltage exceeding a threshold voltage, the carriers are holes at a large negative voltage lower than the threshold voltage, and the carriers are electrons and holes near the threshold voltage), so that when the TFT is controlled to be in an off state, a source-drain current in the TFT is large, and an off-state current of the TFT is large, and thus the TFT cannot be normally used.
Disclosure of Invention
The invention provides a display screen, a control method thereof and a display device, and aims to solve the problem that a TFT cannot be used normally. The technical scheme is as follows:
in a first aspect, a display screen is provided, the display screen comprising: a display panel and a control circuit, wherein,
the array substrate in the display panel includes: a substrate base plate, and a thin film transistor disposed on the substrate base plate, the thin film transistor including: the source electrode, the drain electrode, the active layer and n grid electrodes, wherein the material of the active layer is a semiconductor type carbon nano tube, n is an integer which is more than or equal to 2,
the control circuit is respectively connected with a target grid and an auxiliary grid in the n grids, the target grid is different from the auxiliary grid, the control circuit is used for inputting a first off-state voltage to the target grid in an off-state time period, and inputting a second off-state voltage to the auxiliary grid in the off-state time period, so that a target positive and negative PN junction is formed in the active layer under the action of the voltage on the n grids, and the forward conduction direction of the target PN junction is opposite to the current flowing direction in a region except the region where the target PN junction is located in the active layer.
Optionally, the control circuit includes: an array substrate row driving GOA circuit and an auxiliary circuit,
the GOA circuit is connected with the target grid, the auxiliary circuit is connected with the auxiliary grid, the GOA circuit is used for inputting a first off-state voltage to the target grid in the off-state time period, and the auxiliary circuit is used for inputting a second off-state voltage to the auxiliary grid in the off-state time period.
Optionally, n is an integer greater than or equal to 3, and the n gates include: x first gates and y second gates, where x and y are integers greater than or equal to 1, and x + y is equal to n, the x first gates and the y second gates being spaced apart from each other,
a first grid adjacent to a second grid in the x first grids is a target grid, a second grid adjacent to the first grid in the y second grids is an auxiliary grid, the GOA circuit is connected with the target grid, and the auxiliary circuit is connected with the auxiliary grid;
when the GOA circuit inputs a first off-state voltage to the target grid electrode and the auxiliary circuit inputs a second off-state voltage to the auxiliary grid electrode, a target PN junction and an auxiliary PN junction are formed in the active layer, and the forward conduction direction of the auxiliary PN junction is opposite to the forward conduction direction of the target PN junction.
Optionally, n is an integer greater than or equal to 3, and the n gates include: x first gates and y second gates, x and y being integers greater than or equal to 1, and x + y being n, a first gate group including the x first gates, two second gate groups including the y second gates, the first gate group and the two second gate groups being arranged in a column, and the first gate group being located between the two second gate groups,
a first grid adjacent to a second grid in the x first grids is a target grid, a second grid adjacent to the first grid in the y second grids is an auxiliary grid, the GOA circuit is connected with the target grid, and the auxiliary circuit is connected with the auxiliary grid;
when the GOA circuit inputs a first off-state voltage to the target grid electrode and the auxiliary circuit inputs a second off-state voltage to the auxiliary grid electrode, a target PN junction and an auxiliary PN junction are formed in the active layer, and the forward conduction direction of the auxiliary PN junction is opposite to the forward conduction direction of the target PN junction.
Optionally, the GOA circuit is connected to each of the x first gates, the auxiliary circuit is connected to each of the y second gates,
the GOA circuit is used for inputting the first off-state voltage to the target grid in the off-state time period and inputting the on-state voltage to each first grid in the on-state time period;
the auxiliary circuit is configured to input the second off-state voltage to the auxiliary gate in the off-state period, and input the on-state voltage to each of the second gates in the on-state period.
Optionally, the n gate electrodes are all located on the same side of the active layer,
the active layer is arranged on the substrate base plate;
the source electrode and the drain electrode are arranged on the substrate base plate provided with the active layer;
a gate insulating layer is arranged on the substrate base plate provided with the source electrode and the drain electrode;
the substrate base plate provided with the grid insulation layer is provided with the n grids;
and a passivation layer is arranged on the substrate base plate provided with the n grids.
Optionally, the n gate electrodes are all located on the same side of the active layer,
the substrate base plate is provided with the n grids;
a grid electrode insulating layer is arranged on the substrate base plate provided with the n grid electrodes;
the active layer is arranged on the substrate base plate provided with the grid insulation layer;
the source electrode and the drain electrode are arranged on the substrate base plate provided with the active layer;
and a passivation layer is arranged on the substrate base plate provided with the source electrode and the drain electrode.
In a second aspect, a display device is provided, which comprises the display screen of the first aspect.
In a third aspect, a method for controlling a display screen is provided, where the display screen is the display screen of the first aspect, and the display screen includes: display panel and control circuit, array substrate includes among the display panel: a substrate base plate, and a thin film transistor disposed on the substrate base plate, the thin film transistor including: the source electrode, the drain electrode, an active layer and n grid electrodes, wherein the active layer is made of semiconductor type carbon nano tubes, n is an integer greater than or equal to 2, the control circuit is respectively connected with a target grid electrode and an auxiliary grid electrode in the n grid electrodes, and the target grid electrode is different from the auxiliary grid electrode, and the method comprises the following steps:
controlling the control circuit to input a first off-state voltage to the target grid electrode in an off-state time period;
and controlling the control circuit to input a second off-state voltage to the auxiliary grid electrode in the off-state time period, so that a target PN junction is formed in an active layer in the thin film transistor under the action of the voltages on the n grid electrodes, and the forward conduction direction of the target PN junction is opposite to the current flowing direction in the region except for the region where the target PN junction is located in the active layer.
Optionally, the control circuit includes: GOA circuit and auxiliary circuit, n is an integer greater than or equal to 3, the n gates include: x first gates and y second gates, where x and y are integers greater than or equal to 1, and x + y is equal to n, a first gate adjacent to a second gate among the x first gates is a target gate, a second gate adjacent to a first gate among the y second gates is an auxiliary gate, the GOA circuit is connected to each first gate among the x first gates, and the auxiliary circuit is connected to each second gate among the y second gates,
the controlling the control circuit to input a first off-state voltage to the target gate in an off-state time period includes: controlling the GOA circuit to input a first off-state voltage to the target gate in the off-state time period;
the controlling the control circuit to input a second off-state voltage to the auxiliary gate in the off-state time period includes: controlling the auxiliary circuit to input a second off-state voltage to the auxiliary gate in the off-state time period;
the method further comprises the following steps:
controlling the GOA circuit to input an on-state voltage to each first grid in an on-state time period;
and controlling the auxiliary circuit to input the on-state voltage to each second grid electrode in the on-state time period.
In summary, in the display panel, the thin film transistor in the display panel includes at least two gates, and the GOA circuit and the auxiliary circuit are respectively connected to different gates of the n gates, and when the GOA circuit applies a first off-state voltage to the connected gates and the auxiliary circuit applies a second off-state voltage to the connected gates, the active layer can generate a target PN junction under the action of the voltages on the n gates, and a forward conduction direction of the target PN junction is opposite to a current flowing direction in other regions in the active layer. Even if the current carriers in the active layer are inverted, the target PN junction can play a role in stopping the flow of the current carriers in the active layer, so that the off-state current of the TFT is reduced, and the TFT can be normally used.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings needed to be used in the description of the embodiments will be briefly introduced below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and it is obvious for those skilled in the art to obtain other drawings based on these drawings without creative efforts.
Fig. 1 is a schematic partial structure diagram of a display screen according to an embodiment of the present invention;
fig. 2 is a schematic partial structure diagram of another display screen according to an embodiment of the present invention;
fig. 3 is a schematic partial structure diagram of another display screen according to an embodiment of the present invention;
fig. 4 is a schematic partial structure diagram of another display screen according to an embodiment of the present invention;
fig. 5 is a schematic partial structure diagram of a display screen according to another embodiment of the present invention;
fig. 6 is a flowchart of a method of controlling a display screen according to an embodiment of the present invention;
FIG. 7 is a flowchart illustrating a method for controlling a display screen according to another embodiment of the present invention;
FIG. 8 is a schematic diagram of voltages applied to a target gate and an auxiliary gate according to an embodiment of the present invention;
fig. 9 is a schematic diagram of an energy level structure corresponding to each gate of a p-type thin film transistor in an on-state period according to an embodiment of the present invention;
fig. 10 is a schematic diagram of an energy level structure corresponding to each gate of a p-type thin film transistor in an off-state period according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, embodiments of the present invention will be described in detail with reference to the accompanying drawings.
Fig. 1 is a schematic partial structure diagram of a display screen 0 according to an embodiment of the present invention, and as shown in fig. 1, the display screen 0 may include: display panel and control circuit 01, array substrate can include in the display panel: a substrate 02, and a thin film transistor disposed on the substrate 02, the thin film transistor may include: a source 031, a drain 032, an active layer 033 and n gates 034, wherein the active layer 033 is made of a semiconductor carbon nanotube, and n is an integer greater than or equal to 2.
The control circuit 01 is connected to a target gate and an auxiliary gate of the n gates 034, the target gate and the auxiliary gate are different, the control circuit 01 is configured to input a first off-state voltage to the target gate in an off-state time period, and input a second off-state voltage to the auxiliary gate in the off-state time period, so that a target Positive and Negative (PN) junction is formed in the active layer 033 under the action of voltages on the n gates 034, and a forward conduction direction of the target PN junction is opposite to a current flowing direction in a region of the active layer except for a region where the target PN junction is located.
In summary, in the display panel provided in the embodiment of the invention, the thin film transistor includes at least two gates, the GOA circuit and the auxiliary circuit are respectively connected to different gates of the n gates, and when the GOA circuit applies a first off-state voltage to the connected gates and the auxiliary circuit applies a second off-state voltage to the connected gates, the active layer can generate a target PN junction under the action of the voltages on the n gates, and a forward conduction direction of the target PN junction is opposite to a current flowing direction in other regions in the active layer. Even if the current carriers in the active layer are inverted, the target PN junction can play a role in stopping the flow of the current carriers in the active layer, so that the off-state current of the TFT is reduced, and the TFT can be normally used.
Further, in the related art, after the inorganic passivation layer is covered by the TFT using the semiconductor type carbon nanotube as the active layer, a bipolar conduction phenomenon occurs to carriers in the active layer, when a voltage applied to the gate is greater than a threshold voltage, the carriers in the active layer are electrons, the TFT is in an on state at this time, the number of carriers in the TFT is large, and a current flowing between the source electrode and the drain electrode in the TFT is a first current; when the voltage applied to the gate electrode is close to the threshold voltage, the carriers in the active layer are electrons and holes, and the TFT is in an off state, but the number of carriers in the active layer is still large, and the current flowing between the source electrode and the drain electrode in the TFT is the second current. When the voltage applied to the gate electrode is less than the threshold voltage, the carriers in the active layer are holes, and the carriers in the active layer are more in this case, and the current flowing between the source electrode and the drain electrode in the TFT is a third current. For example, the first current and the third current are both larger than the second current, and therefore, in order to achieve the turn-off of the TFT in the related art, the voltage to be applied to the gate must be in the vicinity of the threshold voltage, and therefore, the TFT needs to apply a smaller voltage range to the gate to achieve the off-state. And even if a voltage near the threshold voltage is applied to the gate electrode, carriers in the active layer are still more, so that the off-state current of the TFT is larger.
In the embodiment of the invention, when the TFT needs to be controlled to be in the off state, the first off-state voltage can be input to the target grid electrode, and the second off-state voltage is input to the auxiliary grid electrode, so that the target PN junction which can play a role of stopping the flow of carriers in the active layer is formed. For example, the first off-state voltage applied to the target gate may be the same as the voltage applied to the gate when the TFT is off in the related art. When the TFT needs to be controlled to be in an off state, no matter the voltage applied to the target gate is close to or less than the threshold voltage, the carriers in the active layer are electrons and holes, or the carriers in the active layer are holes, the target PN junction can prevent the carriers in the active layer from moving, and therefore the off-state current of the TFT is reduced. And because not only a voltage close to the threshold voltage but also a voltage smaller than the threshold voltage is applied to the target gate when the off-state of the TFT is realized, the range of the voltage applied to the gate when the off-state of the TFT is realized is expanded.
Fig. 2 is a schematic partial structure diagram of another display screen according to an embodiment of the present invention, and as shown in fig. 2, the control circuit 01 may include: the Array substrate comprises an Array substrate row driving (Gate driver On Array, abbreviated as GOA) circuit 011 and an auxiliary circuit 012, wherein the GOA circuit 011 is connected with a target Gate, the auxiliary circuit 012 is connected with an auxiliary Gate, the GOA circuit 011 is used for inputting a first off-state voltage to the target Gate in an off-state time period, and the auxiliary circuit 012 is used for inputting a second off-state voltage to the auxiliary Gate in the off-state time period.
n may be an integer greater than or equal to 3, and the n gates 034 may include: x first gates 0341 and y second gates 0342, where x and y may be integers greater than or equal to 1, and x + y is equal to n, and the x first gates 0341 and the y second gates 0342 are spaced apart. A first gate 0341 adjacent to a second gate 0342 in the x first gates 0341 is a target gate, a second gate 0342 adjacent to the first gate 0341 in the y second gates 0342 is an auxiliary gate, the GOA circuit 011 is connected to the target gate, and the auxiliary circuit 012 is connected to the auxiliary gate. When the GOA circuit 011 inputs a first off-state voltage to the target gate and the auxiliary circuit 012 inputs a second off-state voltage to the auxiliary gate, a target PN junction and an auxiliary PN junction are formed in the active layer 033, and a forward conduction direction of the auxiliary PN junction is opposite to a forward conduction direction of the target PN junction.
For example, in fig. 2, n is equal to 3, and the three gates 034 include a first gate 0341 and two second gates 0342, where the first gate 0341 and the two second gates 0342 are disposed at intervals, that is, the second gate 0342, the first gate 0341, and the second gate 0342 are sequentially arranged. That is, the first gate 0341 in fig. 2 is the target gate, the first gate 0341 is connected to the GOA circuit 011, each of the second gates 0342 in fig. 2 is an auxiliary gate, and each of the second gates 0342 is connected to the auxiliary circuit 012. When the x first gate electrodes 0341 and the y second gate electrodes 0342 in fig. 2 are spaced, more PN junctions are formed in the active layer 033, and the PN junctions have a stronger blocking effect on the current in the active layer 033.
Fig. 3 is a schematic partial structure diagram of another display screen according to an embodiment of the present invention, and as shown in fig. 3, the control circuit 01 may include: the gate driver circuit comprises a GOA circuit 011 connected to a target gate, an auxiliary circuit 012 connected to the auxiliary gate, the GOA circuit 011 configured to input a first off-state voltage to the target gate during an off-state period, and the auxiliary circuit 012 configured to input a second off-state voltage to the auxiliary gate during the off-state period.
n may be an integer greater than or equal to 3, and the n gates 034 may include: x first grid electrodes 0341 and y second grid electrodes 0342, wherein x and y are integers greater than or equal to 1, and x + y is equal to N, the first grid electrode group M comprises x first grid electrodes 0341, the two second grid electrode groups N comprise y second grid electrodes 0342, the first grid electrode group M and the two second grid electrode groups N are arranged in a column, and the first grid electrode group M is located between the two second grid electrode groups N. Among the x first gates 0341 forming the first gate group M, the first gate 0341 adjacent to the second gate 0342 is a target gate and is connected to the GOA circuit 011; the second gate 0342 adjacent to the first gate 0341 in the y second gates 0342 constituting the two second gate groups N is an auxiliary gate, and is connected to the auxiliary circuit 012. When the GOA circuit 011 inputs a first off-state voltage to the target gate and the auxiliary circuit 012 inputs a second off-state voltage to the auxiliary gate, a target PN junction and an auxiliary PN junction are formed in the active layer 033, and a forward conduction direction of the auxiliary PN junction is opposite to a forward conduction direction of the target PN junction.
In fig. 3, for example, N is equal to 5, x is equal to 1, and y is equal to 4, that is, the five gates in fig. 3 include a first gate group M and two second gate groups N, the first gate group M includes a first gate 0341, each second gate group N includes two second gates 0342, and the second gate 0342, the first gate 0341, the second gate 0342, and the second gate 0342 are sequentially arranged.
Further, the GOA circuit in fig. 2 and 3 can be further connected to each of the x first gates, the auxiliary circuit can be further connected to each of the y second gates, and the GOA circuit can be configured to input a first off-state voltage to the target gate in the off-state time period and input an on-state voltage to each of the first gates in the on-state time period; the auxiliary circuit is used for inputting second off-state voltage to the auxiliary grid electrode in the off-state time period and inputting on-state voltage to each second grid electrode in the on-state time period.
Because the thin film transistor in the embodiment of the invention comprises at least 3 grid electrodes, the GOA circuit is connected with the target grid electrode, the auxiliary circuit is connected with the auxiliary grid electrode, when voltage is applied to the GOA circuit and the auxiliary circuit, a target PN junction and an auxiliary PN junction can be simultaneously formed in the active layer, and the forward conduction direction of the target PN junction is opposite to that of the auxiliary PN junction, so that no matter an electric signal is input from any non-grid electrode of the TFT and an electric signal is output from the other non-grid electrode, the forward conduction direction of one PN junction in the target PN junction and the auxiliary PN junction is always opposite to the flowing direction of current in the active layer. That is, a Positive and Negative Positive (PNP) junction can be formed in the active layer in fig. 2.
Fig. 4 is a schematic partial structure diagram of another display panel 0 according to an embodiment of the present invention, as shown in fig. 4, n gate electrodes 034 are all located on the same side of an active layer 033, and the active layer 033 is disposed on a substrate 02; a source electrode 031 and a drain electrode 032 are disposed on the substrate 02 on which the active layer 033 is disposed; a gate insulating layer 035 is provided on the substrate 02 provided with the source 031 and the drain 032; n gates 034 are disposed on the substrate base plate 02 provided with the gate insulating layer 035; a passivation layer 036 is disposed on the substrate base plate 02 on which the n gate electrodes 034 are disposed. That is, the thin film transistor in the display panel shown in fig. 4 is a top gate type thin film transistor.
For example, when manufacturing a thin film transistor in a display panel as shown in fig. 4, a substrate may be first cleaned, and then a semiconductor type carbon nanotube film may be deposited on the substrate by dip coating or spin coating. And processing the semiconductor type carbon nanotube film by a one-step composition process (including coating photoresist, exposing, developing, etching and stripping) to obtain an active layer in the thin film transistor. And depositing a source-drain metal layer (made of copper or nickel) with the thickness of 200 nanometers on the substrate base plate with the active layer, and processing the source-drain metal layer through a one-step composition process to obtain a source-drain electrode. Further, after the source and drain electrodes are obtained, 100 nm thick silicon oxide may be deposited (e.g., by plasma enhanced chemical vapor deposition) on the substrate on which the source and drain electrodes are formed to form the gate insulating layer.
Then, a gate metal layer (the material may be molybdenum) with a thickness of 220 nm may be deposited on the substrate with the gate insulating layer formed thereon, and the gate metal layer is processed through a one-step patterning process to obtain n gates. And depositing 300 nm thick silicon nitride on the substrate base plate on which the n gates are formed to obtain a passivation layer.
Finally, the passivation layer can be processed by adopting a one-time composition process, so that through holes respectively contacted with the source electrode, the drain electrode and the grid electrode are formed on the passivation layer. And depositing (e.g., by sputtering) a 135 nm thick ito layer in each via hole, and performing a patterning process on the ito layer to obtain the tft.
Fig. 5 is a schematic partial structure diagram of a display panel 0 according to another embodiment of the present invention, as shown in fig. 5, n gate electrodes 034 may be all located on the same side of an active layer 033, and n gate electrodes 034 are disposed on a substrate 02; a gate insulating layer 035 is provided on the substrate base plate 02 provided with the n gates 034; an active layer 033 is disposed on the substrate base plate 02 provided with the gate insulating layer 035; a source electrode 031 and a drain electrode 032 are disposed on the substrate 02 on which the active layer 033 is disposed; a passivation layer 036 is disposed on the substrate 02 on which the source electrode 031 and the drain electrode 032 are disposed. That is, the thin film transistor in the display panel shown in fig. 5 is a bottom gate thin film transistor.
For example, in manufacturing a thin film transistor in a display panel as shown in fig. 5, a substrate may be first cleaned, and a 2200 nm thick gate metal layer (which may be molybdenum) may be deposited on the surface of the substrate. And processing the gate metal layer by a one-time communication process to obtain n gates.
Then, a silicon oxide layer or a silicon nitride layer with a thickness of 100 nm to 200 nm may be deposited on the surface of the substrate on which the n gates are formed, to obtain a gate insulating layer. And a layer of semiconductor type carbon nanotube film is coated on the surface of the gate insulating layer by adopting a dip coating or spin coating mode and the like. And processing the semiconductor type carbon nanotube film by a one-step composition process (including coating photoresist, exposing, developing, etching and stripping) to obtain an active layer in the thin film transistor.
And depositing a source-drain metal layer (made of copper or nickel) with the thickness of 200 nanometers on the substrate base plate with the active layer, and processing the source-drain metal layer through a one-step composition process to obtain a source-drain electrode. Then, a passivation layer may be obtained by depositing 300 nm thick silicon nitride on the substrate where the active drain electrode is formed.
Finally, the passivation layer can be processed by adopting a one-time composition process, so that through holes respectively contacted with the source electrode, the drain electrode and the grid electrode are formed on the passivation layer. And depositing (e.g., by sputtering) a 135 nm thick ito layer in each via hole, and performing a patterning process on the ito layer to obtain the tft.
It should be noted that the auxiliary circuit in the embodiment of the present invention may be integrated in a GOA circuit, and the auxiliary circuit may also be integrated in other circuits on the display screen, for example, the auxiliary circuit may also be integrated in an electrostatic discharge (ESD) circuit on the display screen, which is not limited in the embodiment of the present invention. Optionally, in the embodiment of the present invention, the active layer may also be made of a one-dimensional material such as a silicon nanowire, a group iii-v nanowire, or a semiconductor material with an overlapping structure (e.g., a semiconductor material with an X-Y structure).
Further, the thin film transistor in the embodiment of the present invention includes at least two gates, two composition situations and arrangement situations of the at least two gates are respectively shown in fig. 2 and fig. 3, and the at least two gates in fig. 2 and fig. 3 are sequentially disposed on the substrate along a direction from the source to the drain, and an orthographic projection area of the two gates on the substrate overlaps with an orthographic projection area of the source-drain pattern on the substrate. In practical application, the at least two gates can be sequentially arranged on the substrate along the direction from the source electrode to the drain electrode, the orthographic projection areas of the two gates on the substrate do not overlap with the orthographic projection areas of the source/drain electrode patterns on the substrate, and the active layer can generate a target PN junction under the action of the at least two gates. That is, the composition and arrangement of the at least two gates are not limited in the embodiments of the present invention, but the at least two gates in the embodiments of the present invention can affect the active layer to generate the target PN junction.
In summary, in the display panel provided in the embodiment of the invention, the thin film transistor includes at least two gates, the GOA circuit and the auxiliary circuit are respectively connected to different gates of the n gates, and when the GOA circuit applies a first off-state voltage to the connected gates and the auxiliary circuit applies a second off-state voltage to the connected gates, the active layer can generate a target PN junction under the action of the voltages on the n gates, and a forward conduction direction of the target PN junction is opposite to a current flowing direction in other regions in the active layer. Even if the current carriers in the active layer are inverted, the target PN junction can play a role in stopping the flow of the current carriers in the active layer, so that the off-state current of the TFT is reduced, and the TFT can be normally used.
Embodiments of the present invention provide a display device, which may include a display screen 0 as shown in fig. 1, fig. 2, fig. 3, fig. 4, or fig. 5.
The display device may be: any product or component with a display function, such as electronic paper, a mobile phone, a tablet computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
In summary, in the display panel of the display device provided in the embodiment of the invention, the thin film transistor includes at least two gates, and the GOA circuit and the auxiliary circuit are respectively connected to different gates of the n gates, and when the GOA circuit applies the first off-state voltage to the connected gates and the auxiliary circuit applies the second off-state voltage to the connected gates, the active layer can generate the target PN junction under the action of the voltages on the n gates, and the forward conduction direction of the target PN junction is opposite to the flowing direction of the current in other regions in the active layer. Even if the current carriers in the active layer are inverted, the target PN junction can play a role in stopping the flow of the current carriers in the active layer, so that the off-state current of the TFT is reduced, and the TFT can be normally used.
As shown in fig. 6, an embodiment of the present invention provides a method for controlling a display screen, where the display screen may be the display screen 0 shown in fig. 1, fig. 2, fig. 3, fig. 4, or fig. 5, and the method for controlling the display screen may include:
601, controlling a control circuit to input a first off-state voltage to a target grid electrode in an off-state time period;
In summary, in the control method of the display panel provided by the invention, when the control circuit applies the first off-state voltage to the target gate and applies the second off-state voltage to the auxiliary gate, the active layer can generate the target PN junction under the action of the voltages on the n gates, and the forward conduction direction of the target PN junction is opposite to the current flowing direction in other regions in the active layer. Even if the current carriers in the active layer are inverted, the target PN junction can play a role in stopping the flow of the current carriers in the active layer, so that the off-state current of the TFT is reduced, and the TFT can be normally used.
Optionally, step 601 may include: controlling the GOA circuit to input a first off-state voltage to a target grid in an off-state time period;
step 602 may include: controlling the auxiliary circuit to input a second off-state voltage to the auxiliary gate in the off-state time period:
optionally, the control method of the display screen may further include:
controlling the GOA circuit to input an on-state voltage to each first grid in an on-state time period;
the control auxiliary circuit inputs an on-state voltage to each second gate in the on-state time period.
In summary, in the control method of the display panel provided by the invention, when the control circuit applies the first off-state voltage to the target gate and applies the second off-state voltage to the auxiliary gate, the active layer can generate the target PN junction under the action of the voltages on the n gates, and the forward conduction direction of the target PN junction is opposite to the current flowing direction in other regions in the active layer. Even if the current carriers in the active layer are inverted, the target PN junction can play a role in stopping the flow of the current carriers in the active layer, so that the off-state current of the TFT is reduced, and the TFT can be normally used.
As shown in fig. 7, another method for controlling a display screen according to an embodiment of the present invention is provided, where the display screen may be the display screen 0 shown in fig. 1, fig. 2, fig. 3, fig. 4, or fig. 5, and the method for controlling the display screen may include:
For example, the GOA circuit can be connected to all of the first gates at the same time, and the auxiliary circuit can be connected to all of the second gates at the same time. In the on-state time period, the GOA circuit can be simultaneously controlled to input an on-state voltage to each first gate, and the auxiliary circuit can be simultaneously controlled to input an on-state voltage to each second gate. At this time, the voltage on each gate of one thin film transistor is an on-state voltage, and at this time, the active layer is in an accumulation state and the thin film transistor is in an on state.
Fig. 8 is a schematic diagram of voltages applied to a target gate and an auxiliary gate according to an embodiment of the present invention. Fig. 9 is a schematic diagram of an energy level structure corresponding to each gate on the p-type thin film transistor in an on-state period when a source-drain voltage is zero volts according to an embodiment of the present invention, and it should be noted that fig. 8 and fig. 9 both use the arrangement of a plurality of gates as shown in fig. 2 as an example.
As shown in fig. 8, in the on-state period, the GOA circuit inputs an on-state voltage-V1 to each first gate and the auxiliary circuit inputs an on-state voltage-V1 to each second gate, and at this time, the voltage applied to the target gate is an on-state voltage-V1 and the voltage applied to the auxiliary gate is also an on-state voltage-V1. As shown in fig. 9, at this time, the voltages inputted to each gate (each first gate and each second gate) are all on-state voltages, the conduction band of the region corresponding to each gate in the active layer is the same, the valence band of the region corresponding to each gate in the active layer is also the same, and at this time, the valence band is close to the fermi level, and holes in the active layer flow to form a current. The operation state of the thin film transistor at this time is the same as that of the thin film transistor in the on-state period in the related art.
For example, a first gate adjacent to a second gate among the plurality of first gates is a target gate, and a second gate adjacent to the first gate among the plurality of second gates is an auxiliary gate. In the off-state time period (that is, when the thin film transistor needs to be turned off), the GOA circuit can be respectively controlled to input a first off-state voltage to the target gate, and the auxiliary circuit is controlled to input a second off-state voltage to the auxiliary gate, so that the target gate and the auxiliary gate form a target PN junction, and further, when the distribution states of the plurality of gates are as shown in fig. 2 or fig. 3, the target gate and the auxiliary gate can not only form the target PN junction, but also form the auxiliary PN junction, and the forward conduction direction of the target PN junction is opposite to the forward conduction direction of the auxiliary PN junction.
Fig. 10 is a schematic diagram of an energy level structure corresponding to each gate on the p-type thin film transistor in an off-state time period when a source-drain voltage is zero volts according to an embodiment of the present invention, and it should be noted that fig. 10 illustrates an arrangement of a plurality of gates as shown in fig. 2.
As shown in fig. 8, in the off-state period, the GOA circuit inputs a first off-state voltage + V1 to the target gate, and the auxiliary circuit inputs a second off-state voltage + V1-V0 to the auxiliary gate, i.e. the voltage input by the target gate and the auxiliary gate is different, for example, V0 may be a preset constant voltage. As shown in fig. 10, at this time, the voltage input on the target gate is the first off-state voltage, the conduction band of the region corresponding to the target gate in the active layer is closer to the fermi level than the valence band, that is, the carriers in the region corresponding to the target gate in the active layer are inverted, and the flow of electrons in the region corresponding to the target gate in the active layer forms a current, that is, the current appears in the region corresponding to the target gate in the active layer during the off-state period.
However, in the embodiment of the present invention, the second off-state voltage is applied to the auxiliary gates located at two sides of the target gate, so that the valence band of the region corresponding to the auxiliary gate in the active layer is closer to the fermi level than the conduction band, and more holes are in the region corresponding to the auxiliary gate in the active layer. And under the action of the voltage on the two auxiliary gates and the voltage on the target gate, two PN junctions with opposite forward conduction directions are formed in the active layer, and the forward conduction direction of at least one PN junction in the two PN junctions is opposite to the current flowing direction in the region corresponding to the target gate in the active layer. In addition, as more holes are formed in the regions corresponding to the two auxiliary gates in the active layer, the holes in the regions can be combined with electrons in the regions corresponding to the target gates in the active layer, so that the flow of electrons in the active layer is further reduced, the off-state current in the active layer is reduced, and the ratio of the on-state current to the off-state current of the thin film transistor is improved.
In summary, in the control method of the display panel provided by the invention, when the control circuit applies the first off-state voltage to the target gate and applies the second off-state voltage to the auxiliary gate, the active layer can generate the target PN junction under the action of the voltages on the n gates, and the forward conduction direction of the target PN junction is opposite to the current flowing direction in other regions in the active layer. Even if the current carriers in the active layer are inverted, the target PN junction can play a role in stopping the flow of the current carriers in the active layer, so that the off-state current of the TFT is reduced, and the TFT can be normally used.
It should be noted that, the display screen embodiment, the display screen control method embodiment, and the display device embodiment in the embodiments of the present invention may all be referred to with each other, and details of the embodiments of the present invention are not described herein.
The present invention is not limited to the above preferred embodiments, and any modifications, equivalent replacements, improvements, etc. within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (5)
1. A display screen, wherein the display screen comprises: a display panel, an array substrate row driving GOA circuit and an auxiliary circuit,
the array substrate in the display panel includes: a substrate base plate, and a thin film transistor disposed on the substrate base plate, the thin film transistor including: the transistor comprises a source electrode, a drain electrode, an active layer, a first grid electrode group and two second grid electrode groups, wherein the first grid electrode group and the two second grid electrode groups are arranged in a row; the first grid electrode group comprises x first grid electrodes, the two second grid electrode groups comprise y second grid electrodes, the active layer is made of semiconductor type carbon nano tubes, x is an integer larger than or equal to 1, and y is an integer larger than 2;
the GOA circuit is connected with each first grid electrode in the x first grid electrodes, and the auxiliary circuit is connected with each second grid electrode in the y second grid electrodes;
the GOA circuit is used for inputting a first off-state voltage to a target gate in an off-state time period, the auxiliary circuit is used for inputting a second off-state voltage to an auxiliary gate in the off-state time period, so that a target PN junction and an auxiliary PN junction which are opposite in forward conduction direction are formed in the active layer under the action of voltages on the x first gates and the y second gates, and the forward conduction direction of the target PN junction is opposite to the current flowing direction in a region except for the region where the target PN junction is located in the active layer; the target grid is a first grid adjacent to a second grid in the x first grids, and the auxiliary grid is a second grid adjacent to the first grid in the y second grids.
2. The display screen of claim 1, wherein the x first gate electrodes and the y second gate electrodes are located on the same side of the active layer,
the active layer is arranged on the substrate base plate;
the source electrode and the drain electrode are arranged on the substrate base plate provided with the active layer;
a gate insulating layer is arranged on the substrate base plate provided with the source electrode and the drain electrode;
the x first grid electrodes and the y second grid electrodes are arranged on the substrate base plate provided with the grid electrode insulating layer;
a passivation layer is arranged on the substrate base plate provided with the x first grid electrodes and the y second grid electrodes.
3. The display screen of claim 1, wherein the x first gate electrodes and the y second gate electrodes are located on the same side of the active layer,
the substrate base plate is provided with the x first grid electrodes and the y second grid electrodes;
a gate insulating layer is arranged on the substrate base plate provided with the x first gates and the y second gates;
the active layer is arranged on the substrate base plate provided with the grid insulation layer;
the source electrode and the drain electrode are arranged on the substrate base plate provided with the active layer;
and a passivation layer is arranged on the substrate base plate provided with the source electrode and the drain electrode.
4. A display device, characterized in that it comprises a display screen according to any one of claims 1 to 3.
5. A control method of a display screen, wherein the display screen is the display screen of any one of claims 1 to 3, and the display screen comprises: display panel, array substrate row drive GOA circuit and auxiliary circuit, array substrate includes among the display panel: a substrate base plate, and a thin film transistor disposed on the substrate base plate, the thin film transistor including: the transistor comprises a source electrode, a drain electrode, an active layer, a first grid electrode group and two second grid electrode groups, wherein the first grid electrode group and the two second grid electrode groups are arranged in a row; the first grid electrode group comprises x first grid electrodes, the two second grid electrode groups comprise y second grid electrodes, the active layer is made of semiconductor type carbon nano tubes, x is an integer larger than or equal to 1, and y is an integer larger than 2; the GOA circuit is connected with each first grid electrode in the x first grid electrodes, and the auxiliary circuit is connected with each second grid electrode in the y second grid electrodes; the method comprises the following steps:
controlling the GOA circuit to input a first off-state voltage to a target grid in an off-state time period;
controlling the auxiliary circuit to input a second off-state voltage to the auxiliary gate in the off-state time period, so that a target PN junction and an auxiliary PN junction with opposite forward conduction directions are formed in an active layer in the thin film transistor under the action of the voltages on the x first gates and the y second gates, and the forward conduction direction of the target PN junction is opposite to the current flowing direction in a region except for the region where the target PN junction is located in the active layer; the target grid is a first grid adjacent to a second grid in the x first grids, and the auxiliary grid is a second grid adjacent to the first grid in the y second grids;
controlling the GOA circuit to input an on-state voltage to each first grid in an on-state time period;
and controlling the auxiliary circuit to input the on-state voltage to each second grid electrode in the on-state time period.
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| EP0444712A1 (en) * | 1990-03-02 | 1991-09-04 | Nippon Telegraph And Telephone Corporation | Multigate thin film transistor |
| CN1767212A (en) * | 2004-09-13 | 2006-05-03 | 三星电子株式会社 | Transistor and manufacture method thereof with carbon nano-tube channel |
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| JPH05251702A (en) * | 1992-03-05 | 1993-09-28 | Fujitsu Ltd | Thin-film transistor and liquid-crystal display using same |
| JPH08148694A (en) * | 1994-09-22 | 1996-06-07 | Sanyo Electric Co Ltd | Thin-film transistor |
| KR100425855B1 (en) * | 1996-06-21 | 2004-07-19 | 엘지.필립스 엘시디 주식회사 | Thin film transistor and method of fabricating the same |
| KR100896167B1 (en) * | 2002-04-24 | 2009-05-11 | 이 잉크 코포레이션 | Electronic displays |
| TWI255150B (en) * | 2003-12-22 | 2006-05-11 | Lg Philips Lcd Co Ltd | Organic electroluminescent device and method of fabricating the same |
| CN104240633B (en) * | 2013-06-07 | 2018-01-09 | 上海和辉光电有限公司 | Thin film transistor (TFT) and active matrix organic light-emitting diode component and its manufacture method |
| CN103715207B (en) * | 2013-12-31 | 2017-11-10 | 合肥京东方光电科技有限公司 | The electric capacity and its manufacture method and relevant device of tft array substrate |
| EP2960943B1 (en) * | 2014-06-27 | 2019-08-07 | LG Display Co., Ltd. | Thin film transistor of display apparatus |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| EP0444712A1 (en) * | 1990-03-02 | 1991-09-04 | Nippon Telegraph And Telephone Corporation | Multigate thin film transistor |
| CN1767212A (en) * | 2004-09-13 | 2006-05-03 | 三星电子株式会社 | Transistor and manufacture method thereof with carbon nano-tube channel |
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