CN106783888A - Display screen and its control method, display device - Google Patents

Display screen and its control method, display device Download PDF

Info

Publication number
CN106783888A
CN106783888A CN201710003222.2A CN201710003222A CN106783888A CN 106783888 A CN106783888 A CN 106783888A CN 201710003222 A CN201710003222 A CN 201710003222A CN 106783888 A CN106783888 A CN 106783888A
Authority
CN
China
Prior art keywords
grid
auxiliary
active layer
target
voltage
Prior art date
Application number
CN201710003222.2A
Other languages
Chinese (zh)
Inventor
孟虎
Original Assignee
京东方科技集团股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 京东方科技集团股份有限公司 filed Critical 京东方科技集团股份有限公司
Priority to CN201710003222.2A priority Critical patent/CN106783888A/en
Publication of CN106783888A publication Critical patent/CN106783888A/en

Links

Classifications

    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259Multistep manufacturing methods

Abstract

The invention discloses a kind of display screen and its control method, display device, belong to display technology field.The display screen includes:Display panel and control circuit, the thin film transistor (TFT) in the display panel in array base palte include:Source electrode, drain electrode, active layer and n grid, the control circuit is connected with target gate and auxiliary grid in the n grid respectively, the control circuit is used to be input into the first standoff voltage to target gate in the OFF state time period, in the OFF state time period the second standoff voltage is input into auxiliary grid, so that in the presence of voltage on the n grid, target PN junction is formed in the active layer, the forward conduction direction of the target PN junction is opposite with the flow direction of electric current in the region in the active layer in addition to the target PN junction region.The present invention solves the problems, such as that TFT cannot be used normally, realizes the effect that TFT can be used normally, and the present invention is used for display screen.

Description

Display screen and its control method, display device

Technical field

The present invention relates to display technology field, more particularly to a kind of display screen and its control method, display device.

Background technology

Display screen includes that display panel and array base palte row drive (English:Gate driver On Array;Referred to as: GOA) circuit, wherein, display panel includes the array base palte and color membrane substrates to box shaping, and positioned at array base palte and color film Liquid crystal between substrate.Array base palte includes multiple films crystalline substance of underlay substrate and the array arrangement being formed on underlay substrate Body pipe (English:Thin Film Transistor;Abbreviation TFT).

In correlation technique, thin film transistor (TFT) includes grid, source electrode, drain electrode and active layer, wherein, grid, electrode and drain electrode Material be metal, the material of active layer is semiconductor type carbon nano-tube.When the voltage applied on grid reaches on-state voltage When (typically larger than threshold voltage), active layer turns on source electrode and drain electrode, and now, TFT is in ON state, and the electric current in TFT is larger, Data-signal on source electrode can be transmitted to drain electrode;When the voltage applied on grid is standoff voltage (typically smaller than threshold voltage) When, active layer cannot turn on source electrode and drain electrode, and TFT is in OFF state, and the electric current in TFT is smaller, the data-signal on source electrode without Method is transmitted to drain electrode.

But, after the TFT with semiconductor type carbon nano-tube as active layer covers inorganic passivation layer, the current-carrying in active layer (i.e. under the larger positive voltage more than threshold voltage, carrier is electronics to the phenomenon that son is easier to bipolar conduction occur, low In under the larger negative voltage of threshold voltage, carrier is hole, and near threshold voltage, carrier is electronics and hole) so that So that when controlling TFT to be in OFF state, the source-drain current in TFT is larger, and the off-state current of TFT is larger, therefore, TFT cannot be just Often use.

The content of the invention

In order to solve the problems, such as that TFT cannot be used normally, the invention provides a kind of display screen and its control method, display Device.The technical scheme is as follows:

First aspect, there is provided a kind of display screen, the display screen includes:Display panel and control circuit,

Array base palte includes in the display panel:Underlay substrate, and it is arranged on film crystal on the underlay substrate Pipe, the thin film transistor (TFT) includes:Source electrode, drain electrode, active layer and n grid, the material of the active layer is semi-conductor type carbon Nanotube, the n is the integer more than or equal to 2,

The control circuit is connected with target gate and auxiliary grid in the n grid respectively, the target grid Pole is different with the auxiliary grid, and the control circuit is used to be input into the first standoff voltage to target gate in the OFF state time period, The second standoff voltage is input into auxiliary grid so that in the presence of voltage on the n grid, institute in the OFF state time period State and the positive and negative PN junction of target is formed in active layer, the target is removed in the forward conduction direction of the target PN junction and the active layer The flow direction of electric current is opposite in region outside PN junction region.

Optionally, the control circuit includes:Array base palte row drives GOA circuits and auxiliary circuit,

The GOA circuits are connected with the target gate, and the auxiliary circuit is connected with the auxiliary grid, described GOA circuits are used to be input into the first standoff voltage to the target gate in the OFF state time period, and the auxiliary circuit is used for The OFF state time period is input into the second standoff voltage to the auxiliary grid.

Optionally, the n is the integer more than or equal to 3, and the n grid includes:X first grid and y individual second Grid, the x and the y are the integer more than or equal to 1, and x+y=n, the x first grid and the y individual second Gate spacer is set,

The first grid adjacent with second grid is target gate in the x first grid, in the y second grid The second grid adjacent with first grid is auxiliary grid, and the GOA circuits are connected with the target gate, the auxiliary electricity Road is connected with the auxiliary grid;

When the GOA circuits are input into the first standoff voltage to the target gate, the auxiliary circuit is to the supplementary gate Target PN junction and auxiliary PN junction, the positive guide of the auxiliary PN junction are formed when pole is input into the second standoff voltage, in the active layer Logical direction is in opposite direction with the forward conduction of the target PN junction.

Optionally, the n is the integer more than or equal to 3, and the n grid includes:X first grid and y individual second Grid, the x and the y are the integer more than or equal to 1, and x+y=n, and first grid group includes the x first grid Pole, two second grid groups include the y second grid, and the first grid group and described two second grid groups line up one Row, and the first grid group is between described two second grid groups,

The first grid adjacent with second grid is target gate in the x first grid, in the y second grid The second grid adjacent with first grid is auxiliary grid, and the GOA circuits are connected with the target gate, the auxiliary electricity Road is connected with the auxiliary grid;

When the GOA circuits are input into the first standoff voltage to the target gate, the auxiliary circuit is to the supplementary gate Target PN junction and auxiliary PN junction, the positive guide of the auxiliary PN junction are formed when pole is input into the second standoff voltage, in the active layer Logical direction is in opposite direction with the forward conduction of the target PN junction.

Optionally, the GOA circuits are connected with each first grid in the x first grid, the auxiliary electricity Road is connected with each second grid in y second grid,

The GOA circuits are used to be input into first standoff voltage to the target gate in the OFF state time period, with And it is input into on-state voltage to described each first grid in ON time section;

The auxiliary circuit is used to be input into second standoff voltage to the auxiliary grid in the OFF state time period, with And it is input into the on-state voltage to described each second grid in ON time section.

Optionally, the n grid is respectively positioned on the homonymy of the active layer,

The active layer is provided with the underlay substrate;

It is provided with the underlay substrate of the active layer and is provided with the source electrode and the drain electrode;

It is provided with the underlay substrate of the source electrode and the drain electrode and is provided with gate insulator;

It is provided with the underlay substrate of the gate insulator and is provided with the n grid;

It is provided with the underlay substrate of the n grid and is provided with passivation layer.

Optionally, the n grid is respectively positioned on the homonymy of the active layer,

The n grid is provided with the underlay substrate;

It is provided with the underlay substrate of the n grid and is provided with gate insulator;

It is provided with and the active layer is provided with the underlay substrate of the gate insulator;

It is provided with the underlay substrate of the active layer and is provided with the source electrode and the drain electrode;

It is provided with the underlay substrate of the source electrode and the drain electrode and is provided with passivation layer.

A kind of second aspect, there is provided display device, the display device includes the display screen described in first aspect.

A kind of third aspect, there is provided control method of display screen, the display screen is the display screen described in first aspect, The display screen includes:Display panel and control circuit, array base palte includes in the display panel:Underlay substrate, Yi Jishe The thin film transistor (TFT) on the underlay substrate is put, the thin film transistor (TFT) includes:Source electrode, drain electrode, active layer and n grid, institute The material of active layer is stated for semiconductor type carbon nano-tube, the n is the integer more than or equal to 2, the control circuit respectively with Target gate in the n grid is connected with auxiliary grid, and the target gate is different from the auxiliary grid, the side Method includes:

The control control circuit is input into the first standoff voltage in the OFF state time period to the target gate;

The control control circuit is input into the second standoff voltage in the OFF state time period to the auxiliary grid so that On the n grid in the presence of voltage, target PN junction is formed in the active layer in thin film transistor (TFT), the target PN junction is just It is opposite with the flow direction of electric current in the region in the active layer in addition to the target PN junction region to conducting direction.

Optionally, the control circuit includes:GOA circuits and auxiliary circuit, the n are the integer more than or equal to 3, institute Stating n grid includes:X first grid and y second grid, the x and the y are the integer more than or equal to 1, and x+ Y=n, in the x first grid first grid adjacent with second grid be target gate, in the y second grid and The adjacent second grid of first grid is each first grid in auxiliary grid, the GOA circuits and the x first grid It is connected, the auxiliary circuit is connected with each second grid in y second grid,

The control control circuit is input into the first standoff voltage in the OFF state time period to the target gate, including: The GOA circuits are controlled to be input into the first standoff voltage to the target gate in the OFF state time period;

The control control circuit is input into the second standoff voltage, bag in the OFF state time period to the auxiliary grid Include:The auxiliary circuit is controlled to be input into the second standoff voltage to the auxiliary grid in the OFF state time period;

Methods described also includes:

The GOA circuits are controlled to be input into on-state voltage to described each first grid in ON time section;

The auxiliary circuit is controlled to be input into the on-state voltage to described each second grid in ON time section.

In sum, the present invention is provided a kind of display screen and its control method, display device, the film in the display screen Transistor includes at least two grids, and GOA circuits and auxiliary circuit are connected from the different grids in n grid respectively, and Apply the first standoff voltage to the grid being connected in GOA circuits, auxiliary circuit applies the second OFF state electricity to the grid being connected During pressure, active layer can produce target PN junction in the presence of voltage on n grid, and the target PN junction forward conduction direction Flow direction with electric current in other regions in active layer is opposite.Even if the carrier in the active layer there occurs transoid, the mesh Mark PN junction also can play interception to the flowing of carrier in active layer, so as to reduce the off-state current of TFT so that TFT can be used normally.

Brief description of the drawings

Technical scheme in order to illustrate more clearly the embodiments of the present invention, below will be to that will make needed for embodiment description Accompanying drawing is briefly described, it should be apparent that, drawings in the following description are only some embodiments of the present invention, for For those of ordinary skill in the art, on the premise of not paying creative work, other can also be obtained according to these accompanying drawings Accompanying drawing.

Fig. 1 is a kind of partial structural diagram of display screen provided in an embodiment of the present invention;

Fig. 2 is the partial structural diagram of another display screen provided in an embodiment of the present invention;

Fig. 3 is the partial structural diagram of another display screen provided in an embodiment of the present invention;

Fig. 4 is the partial structural diagram of another display screen provided in an embodiment of the present invention;

A kind of partial structural diagram of display screen that Fig. 5 is provided for another embodiment of the present invention;

Fig. 6 is a kind of method flow diagram of the control method of display screen provided in an embodiment of the present invention;

Fig. 7 is the method flow diagram of the control method of another display screen provided in an embodiment of the present invention;

Fig. 8 is the schematic diagram of the voltage applied on a kind of target gate provided in an embodiment of the present invention and auxiliary grid;

Fig. 9 is corresponding for a kind of each grid on ON time section p-type thin film transistor provided in an embodiment of the present invention Level structure schematic diagram;

Figure 10 is corresponding for one kind each grid on OFF state time period p-type thin film transistor provided in an embodiment of the present invention Level structure schematic diagram.

Specific embodiment

To make the object, technical solutions and advantages of the present invention clearer, below in conjunction with accompanying drawing to embodiment party of the present invention Formula is described in further detail.

Fig. 1 is a kind of partial structural diagram of display screen 0 provided in an embodiment of the present invention, as shown in figure 1, the display screen 0 can include:Display panel and control circuit 01, array base palte can include in display panel:Underlay substrate 02, and set The thin film transistor (TFT) on underlay substrate 02, thin film transistor (TFT) can include:Source electrode 031, drain electrode 032, active layer 033 and n grid Pole 034, the material of active layer 033 is semiconductor type carbon nano-tube, and n is the integer more than or equal to 2.

Control circuit 01 is connected with target gate and auxiliary grid in n grid 034 respectively, target gate and auxiliary Grid is different, and control circuit 01 is used to be input into the first standoff voltage to target gate in the OFF state time period, the OFF state time period to Auxiliary grid is input into the second standoff voltage so that in the presence of voltage on n grid 034, and target is being formed just in active layer 033 Negative (English:Positive and negative;Referred to as:PN) tie, mesh is removed in the forward conduction direction of target PN junction and active layer The flow direction of electric current is opposite in region outside mark PN junction region.

In sum, because in display screen provided in an embodiment of the present invention, thin film transistor (TFT) includes at least two grids, and GOA circuits and auxiliary circuit are connected from the different grids in n grid respectively, and are applied to the grid being connected in GOA circuits Plus first standoff voltage, when auxiliary circuit applies the second standoff voltage to the grid being connected, active layer can be on n grid Target PN junction, and the forward conduction direction of the target PN junction and electric current in other regions in active layer are produced in the presence of voltage Flow direction is opposite.Even if the carrier in the active layer there occurs transoid, the target PN junction also can be to current-carrying in active layer Interception is played in the flowing of son, so as to reduce the off-state current of TFT so that TFT can be used normally.

Further, in correlation technique, after the TFT covering inorganic passivation layers with semiconductor type carbon nano-tube as active layer, There is the phenomenon of bipolar conduction in carrier in active layer, when the voltage applied on grid is more than threshold voltage, active layer In carrier be electronics, now TFT is in ON state, and the carrier in TFT is more, is flowed between source electrode and drain electrode in TFT Electric current is the first electric current;When the voltage applied on grid is close to threshold voltage, carrier in active layer is electronics and hole, OFF state is now in TFT, but the carrier in active layer is still more, the electric current flowed between source electrode and drain electrode in TFT It is the second electric current.When the voltage applied on grid is less than threshold voltage, the carrier in active layer is hole, now active layer In carrier it is more, in TFT source electrode and drain electrode between flow electric current be the 3rd electric current.Example, the first electric current and the 3rd Electric current is all higher than the second electric current, therefore, in order to realize the closing of TFT, it is necessary to necessary to the voltage that grid applies in correlation technique Positioned near threshold voltage, therefore, TFT realizes that OFF state needs the voltage range to grid applying smaller.Even and if being applied to grid Plus positioned at the voltage of near threshold voltage, the carrier in active layer is still more so that the off-state current of TFT is larger.

In the embodiment of the present invention, when needing control TFT to be in OFF state, the first OFF state electricity can be input into target gate Pressure, the second standoff voltage is input into auxiliary grid, and formation can play the mesh of interception to the flowing of carrier in active layer Mark PN junction.Example, the first standoff voltage applied in the target gate can with correlation technique in TFT OFF state on grid The voltage of applying is identical.When needing control TFT to be in OFF state, no matter to the voltage applied in target gate close to threshold voltage Threshold voltage is also less than, the carrier in active layer is that the carrier in electronics and hole, or active layer is hole, target PN junction can prevent the motion of carrier in active layer, it therefore reduces the off-state current of TFT.And due to realizing TFT passes During state, not only apply the voltage close to threshold voltage to target gate, can also apply to be less than threshold voltage to target gate Voltage, therefore, expand when TFT OFF state is realized, on grid apply voltage range.

Fig. 2 is the partial structural diagram of another display screen provided in an embodiment of the present invention, as shown in Fig. 2 control electricity Road 01 can include:Array base palte row drives (English:Gate driver On Array;Referred to as:GOA) circuit 011 and auxiliary Circuit 012, GOA circuits 011 are connected with target gate, and auxiliary circuit 012 is connected with auxiliary grid, and GOA circuits 011 are used for The first standoff voltage is input into target gate in the OFF state time period, auxiliary circuit 012 is used in the OFF state time period to auxiliary grid It is input into the second standoff voltage.

N can be the integer more than or equal to 3, and n grid 034 can include:X first grid 0341 and y individual second Grid 0342, wherein, x and y can be the integer more than or equal to 1, and x+y=n, x first grid 0341 and y second The interval setting of grid 0342.The first grid 0341 adjacent with second grid 0342 is target gate in x first grid 0341, The second grid 0342 adjacent with first grid 0341 is auxiliary grid, GOA circuits 011 and target in y second grid 0342 Grid is connected, and auxiliary circuit 012 is connected with auxiliary grid.When GOA circuits 011 are input into the first OFF state electricity to target gate Pressure, forms target PN junction and auxiliary PN junction when auxiliary circuit 012 is input into the second standoff voltage to auxiliary grid, in active layer 033, Aid in the forward conduction direction of PN junction in opposite direction with the forward conduction of target PN junction.

Example, it is equal to as a example by 3 by n in Fig. 2, and three grids 034 include a first grid 0341 and two second Grid 0342, a first grid 0341 and two interval settings of second grid 0342, namely second grid 0342, first grid 0341 and second grid 0342 be arranged in order.Namely the first grid 0341 in Fig. 2 is exactly target gate, first grid 0341 with GOA circuits 011 are connected, and each second grid 0342 in Fig. 2 is auxiliary grid, each second grid 0342 with auxiliary Circuit 012 is connected.When x first grid 0341 in Fig. 2 is with y 0342 interval setting of second grid, shape in active layer 033 Into PN junction it is more, PN junction is stronger to the barrier effect of electric current in active layer 033.

Fig. 3 is the partial structural diagram of another display screen provided in an embodiment of the present invention, as shown in figure 3, control electricity Road 01 can include:GOA circuits 011 and auxiliary circuit 012, GOA circuits 011 are connected with target gate, auxiliary circuit 012 with Auxiliary grid is connected, and GOA circuits 011 are used to be input into the first standoff voltage, auxiliary circuit to target gate in the OFF state time period 012 is used to be input into the second standoff voltage to auxiliary grid in the OFF state time period.

N can be the integer more than or equal to 3, and n grid 034 can include:X first grid 0341 and y individual second Grid 0342, x and y are the integer more than or equal to 1, and x+y=n, and first grid group M includes x first grid 0341, two Individual second grid group N includes y second grid 0342, and first grid group M and two second grid group N form a line, first Grid group M is located between two second grid group N.Wherein, in the x first grid 0341 of composition first grid group M with second The adjacent first grid 0341 of grid 0342 is target gate, and is connected with GOA circuits 011;Two second grid group N of composition Y second grid 0342 in the second grid 0342 adjacent with first grid 0341 be auxiliary grid, and with auxiliary circuit 012 It is connected.When GOA circuits 011 are input into the first standoff voltage to target gate, auxiliary circuit 012 is closed to auxiliary grid input second Target PN junction and auxiliary PN junction are formed during state voltage, in active layer 033, forward conduction direction and the target PN junction of PN junction is aided in Forward conduction is in opposite direction.

5, x is equal in Fig. 3 with n to be equal to as a example by 4 equal to 1, y, that is, five grids in Fig. 3 include a first grid Group M and two second grid group N, first grid group M include a first grid 0341, and each second grid group N includes two Second grid 0342, second grid 0342, second grid 0342, first grid 0341, second grid 0342 and second grid 0342 is arranged in order.

Further, the GOA circuits in Fig. 2 and Fig. 3 can also be connected with each first grid in x first grid Connect, auxiliary circuit can also be connected with each second grid in y second grid, and GOA circuits can be used in OFF state Between section to target gate be input into the first standoff voltage, and ON time section to each first grid be input into on-state voltage;It is auxiliary Helping circuit is used to be input into the second standoff voltage to auxiliary grid in the OFF state time period, and in ON time section to each second gate Pole is input into on-state voltage.

Because the thin film transistor (TFT) in the embodiment of the present invention includes at least 3 grids, and GOA circuits are connected with target gate Connect, auxiliary circuit is connected with auxiliary grid, when GOA circuits and auxiliary circuit applied voltage, can be while shape in active layer Into target PN junction and auxiliary PN junction, and the forward conduction direction of target PN junction is in opposite direction with the forward conduction of auxiliary PN junction, makes No matter from any non-grid input electrical signal of TFT, and from another non-grid output electric signal, the target PN junction and auxiliary PN In knot, always there is the forward conduction direction of a PN junction opposite with the flow direction of electric current in active layer.That is, active in Fig. 2 A positive negative and positive (English can be produced in layer:Positive negative and Positive;Referred to as:PNP) tie.

Fig. 4 is the partial structural diagram of another display screen 0 provided in an embodiment of the present invention, as shown in figure 4, n grid Pole 034 is respectively positioned on the homonymy of active layer 033, and active layer 033 is provided with underlay substrate 02;It is provided with the substrate of active layer 033 Source electrode 031 and drain electrode 032 are provided with substrate 02;It is provided with the underlay substrate 02 of source electrode 031 and drain electrode 032 and is provided with grid Insulating barrier 035;It is provided with the underlay substrate 02 of gate insulator 035 and is provided with n grid 034;It is provided with n grid 034 Underlay substrate 02 on be provided with passivation layer 036.That is, the thin film transistor (TFT) in display screen shown in Fig. 4 is top gate type thin film Transistor.

Example, in the thin film transistor (TFT) in manufacturing display screen as shown in Figure 4, underlay substrate can be carried out first Cleaning, then using modes such as dip-coating or spin coatings on underlay substrate, deposits layer of semiconductor type carbon nano-tube film.And lead to A patterning processes (including coating photoresist, exposure, development, etching and stripping) is crossed to enter the semiconductor type carbon nano-tube film Row treatment, obtains the active layer in thin film transistor (TFT).And the source of 200 nanometer thickness is deposited on the underlay substrate for be formed with active layer Leakage metal level (material be copper or nickel), and after being processed the Source and drain metal level by a patterning processes, obtain source and drain Pole.Further, after source-drain electrode is obtained, (such as using plasma can be deposited on the underlay substrate for be formed with source-drain electrode Enhancing chemical vapor deposition) 100 nanometer thickness silica, formed gate insulator.

Afterwards, the barrier metal layer of 220 nanometer thickness can be deposited on the underlay substrate for be formed with gate insulator, and (material can Think molybdenum), and n grid is obtained after being processed the barrier metal layer by a patterning processes.And it is being formed with n grid Underlay substrate on deposit the silicon nitride of 300 nanometer thickness and obtain passivation layer.

Finally, the passivation layer can be processed using a patterning processes so that formed on the passivation layer respectively with The via that source electrode, drain electrode and grid are in contact.And (such as the method using sputtering) 135 nanometer thickness are deposited in each via Indium tin oxide layer, and a patterning processes treatment is carried out to the indium tin oxide layer, obtain the thin film transistor (TFT).

The partial structural diagram of a kind of display screen 0 that Fig. 5 is provided for another embodiment of the present invention, as shown in figure 5, n Grid 034 can be respectively positioned on the homonymy of active layer 033, and n grid 034 is provided with underlay substrate 02;It is provided with n grid Gate insulator 035 is provided with 034 underlay substrate 02;It is provided with the underlay substrate 02 of gate insulator 035 and is provided with Active layer 033;It is provided with the underlay substrate 02 of active layer 033 and is provided with source electrode 031 and drain electrode 032;It is provided with the He of source electrode 031 Passivation layer 036 is provided with the underlay substrate 02 of drain electrode 032.That is, the thin film transistor (TFT) in display screen shown in Fig. 5 is bottom gate Type thin film transistor (TFT).

Example, in the thin film transistor (TFT) in manufacturing display screen as shown in Figure 5, underlay substrate can be carried out first Cleaning, and deposit the barrier metal layer (material can be molybdenum) of 2200 nanometer thickness on underlay substrate surface.And by once linking up work Skill to the barrier metal layer process and obtains n grid.

It is then possible to deposit 100 nanometers of silica to 200 nanometer thickness the n underlay substrate surface of grid is formed with Layer or silicon nitride layer, obtain gate insulator.And it is coated with one using modes such as dip-coating or spin coatings in gate insulator layer surface Layer semiconductor type carbon nano-tube film.And (including coating photoresist, exposure, development, etched and stripping by patterning processes From) the semiconductor type carbon nano-tube film is processed, obtain the active layer in thin film transistor (TFT).

And deposited on the underlay substrate for be formed with active layer 200 nanometer thickness Source and drain metal level (material be copper or Nickel), and after being processed the Source and drain metal level by a patterning processes, obtain source-drain electrode.Afterwards, can form active The silicon nitride that 300 nanometer thickness are deposited on the underlay substrate of drain electrode obtains passivation layer.

Finally, the passivation layer can be processed using a patterning processes so that formed on the passivation layer respectively with The via that source electrode, drain electrode and grid are in contact.And (such as the method using sputtering) 135 nanometer thickness are deposited in each via Indium tin oxide layer, and a patterning processes treatment is carried out to the indium tin oxide layer, obtain the thin film transistor (TFT).

It should be noted that the auxiliary circuit in the embodiment of the present invention can be integrated in GOA circuits, the auxiliary circuit Can be so that in integrated other circuits on a display screen, such as auxiliary circuit can be with integrated static release circuit on a display screen (English:Electro-Static discharge;Referred to as:ESD in), the embodiment of the present invention is not construed as limiting to this.Optionally, originally The material of active layer can also be the one-dimensional material such as silicon nanowires, III-V nano wire in inventive embodiments, or overlapping configuration Semiconductor material (such as X, the semiconductor material of y-type structure).

Further, the thin film transistor (TFT) in the embodiment of the present invention includes at least two grids, and Fig. 2 and Fig. 3 are shown respectively At least two grids in two kinds of composition situations and arrangement situation, and Fig. 2 and Fig. 3 of at least two grid are arrived along source electrode The direction of drain electrode sets gradually on underlay substrate, and the orthographic projection region of two grids on underlay substrate and source-drain electrode pattern There is overlap in the orthographic projection region on underlay substrate.In practical application, at least two grid can also be along source electrode to drain electrode Direction set gradually on underlay substrate, and the orthographic projection region of two grids on underlay substrate and source-drain electrode pattern exist Orthographic projection region on underlay substrate is in the absence of overlap, and active layer can produce target in the presence of at least two grid PN junction.That is, the embodiment of the present invention is not defined to the composition situation and arrangement situation of at least two grids, but this hair At least two grids in bright embodiment can influence active layer to produce target PN junction.

In sum, because in display screen provided in an embodiment of the present invention, thin film transistor (TFT) includes at least two grids, and GOA circuits and auxiliary circuit are connected from the different grids in n grid respectively, and are applied to the grid being connected in GOA circuits Plus first standoff voltage, when auxiliary circuit applies the second standoff voltage to the grid being connected, active layer can be on n grid Target PN junction, and the forward conduction direction of the target PN junction and electric current in other regions in active layer are produced in the presence of voltage Flow direction is opposite.Even if the carrier in the active layer there occurs transoid, the target PN junction also can be to current-carrying in active layer Interception is played in the flowing of son, so as to reduce the off-state current of TFT so that TFT can be used normally.

The embodiment of the invention provides a kind of display device, the display device can include as shown in Figure 1, Figure 2, Fig. 3, Fig. 4 or Display screen 0 shown in Fig. 5.

The display device can be:Electronic Paper, mobile phone, panel computer, television set, display, notebook computer, digital phase Any product or part with display function such as frame, navigator.

In sum, because in the display screen in display device provided in an embodiment of the present invention, thin film transistor (TFT) is included extremely Lack two grids, and GOA circuits and auxiliary circuit are connected from the different grids in n grid respectively, and in GOA circuits to phase The grid of connection applies the first standoff voltage, when auxiliary circuit applies the second standoff voltage to the grid being connected, active layer energy It is enough to produce target PN junction in the presence of voltage on n grid, and the target PN junction forward conduction direction and active layer in its The flow direction of electric current is opposite in his region.Even if the carrier in the active layer there occurs transoid, the target PN junction also can Interception is played in flowing to carrier in active layer, so as to reduce the off-state current of TFT so that TFT can normally make With.

As shown in fig. 6, the embodiment of the invention provides a kind of control method of display screen, the display screen can be Fig. 1, figure 2nd, the display screen 0 shown in Fig. 3, Fig. 4 or Fig. 5, the control method of the display screen can include:

Step 601, control control circuit are input into the first standoff voltage in the OFF state time period to target gate;

Step 602, control control circuit are input into the second standoff voltage in the OFF state time period to auxiliary grid so that at n On grid in the presence of voltage, target PN junction, the forward conduction direction of target PN junction are formed in the active layer in thin film transistor (TFT) Flow direction with electric current in the region in active layer in addition to target PN junction region is opposite.

In sum, in the control method of the display screen for being provided due to the present invention, apply to target gate in control circuit First standoff voltage, when applying the second standoff voltage to auxiliary grid, active layer can be produced in the presence of voltage on n grid Raw target PN junction, and the forward conduction direction of the target PN junction is opposite with the flow direction of electric current in other regions in active layer. Even if the carrier in the active layer there occurs transoid, the target PN junction also can play resistance to the flowing of carrier in active layer Only act on, so as to reduce the off-state current of TFT so that TFT can be used normally.

Optionally, step 601 can include:Control GOA circuits are input into the first OFF state in the OFF state time period to target gate Voltage;

Step 602 can include:Control auxiliary circuit is input into the second standoff voltage in the OFF state time period to auxiliary grid:

Optionally, the control method of the display screen can also include:

Control GOA circuits are input into on-state voltage in ON time section to each first grid;

Control auxiliary circuit is input into on-state voltage in ON time section to each second grid.

In sum, in the control method of the display screen for being provided due to the present invention, apply to target gate in control circuit First standoff voltage, when applying the second standoff voltage to auxiliary grid, active layer can be produced in the presence of voltage on n grid Raw target PN junction, and the forward conduction direction of the target PN junction is opposite with the flow direction of electric current in other regions in active layer. Even if the carrier in the active layer there occurs transoid, the target PN junction also can play resistance to the flowing of carrier in active layer Only act on, so as to reduce the off-state current of TFT so that TFT can be used normally.

As shown in fig. 7, the embodiment of the invention provides the control method of another display screen, the display screen can for Fig. 1, Display screen 0 shown in Fig. 2, Fig. 3, Fig. 4 or Fig. 5, the control method of the display screen can include:

Step 701, ON time section respectively control GOA circuits to each first grid be input into on-state voltage, and control Auxiliary circuit processed is input into on-state voltage to each second grid.

Example, GOA circuits can simultaneously be connected with all of first grid, and auxiliary circuit can also simultaneously with institute Some second grids are connected.In ON time section, GOA circuits can be simultaneously controlled to each first grid input ON state electricity Pressure, and control auxiliary circuit is input into on-state voltage to each second grid.Now, each grid in a thin film transistor (TFT) On voltage be on-state voltage, now, active layer be in accumulated state, thin film transistor (TFT) be in open state.

Fig. 8 is the schematic diagram of the voltage applied on a kind of target gate provided in an embodiment of the present invention and auxiliary grid.Fig. 9 Be provided in an embodiment of the present invention a kind of when source-drain voltage is zero volt, on ON time section p-type thin film transistor each The corresponding level structure schematic diagram of grid is, it is necessary to illustrate, Fig. 8 and Fig. 9 is illustrated in figure 2 with the arrangement of multiple grids Example.

As shown in figure 8, in ON time section, GOA circuits are input into on-state voltage-V1, auxiliary circuit to each first grid On-state voltage-V1 is input into each second grid, now, the voltage applied in target gate is on-state voltage-V1, auxiliary grid The voltage of upper applying is also on-state voltage-V1.As shown in figure 9, now, each grid (each first grid and each second gate Pole) on the voltage that is input into be on-state voltage, the conduction band all same in the corresponding region of each grid in active layer is every in active layer The valence band in the corresponding region of individual grid is also identical, and now valence band near fermi level, the hole flow in active layer forms electricity Stream.The now working condition phase of the working condition of the thin film transistor (TFT) and thin film transistor (TFT) in correlation technique in ON time section Together.

Step 702, the OFF state time period control respectively GOA circuits to target gate be input into the first standoff voltage, and control Auxiliary circuit processed is input into the second standoff voltage to auxiliary grid.

Example, the first grid adjacent with second grid is target gate, multiple second grids in multiple first grids In the second grid adjacent with first grid be auxiliary grid.(namely need to close thin film transistor (TFT) in the OFF state time period When), can respectively control GOA circuits to be input into the first standoff voltage, and control auxiliary circuit to auxiliary grid to target gate It is input into the second standoff voltage so that target gate forms target PN junction with auxiliary grid, further, when the distribution of multiple grids State as shown in Figure 2 or Figure 3 when, target gate and auxiliary grid can not only form target PN junction, additionally it is possible to formed auxiliary PN junction, and the forward conduction direction of target PN junction is in opposite direction with the forward conduction of auxiliary PN junction.

Figure 10 is provided in an embodiment of the present invention a kind of when in source-drain voltage for zero volt, OFF state time period p-type thin film The corresponding level structure schematic diagram of each grid on transistor is, it is necessary to explanation, Figure 10 is with the arrangement of multiple grids such as Fig. 2 institutes It is shown as example.

As shown in figure 8, in the OFF state time period, GOA circuits are input into the first standoff voltage+V1, auxiliary circuit to target gate The second standoff voltage+V1-V0 is input into auxiliary grid, that is, now target gate is different from the voltage that auxiliary grid is input into, is shown Example, V0 can be a default constant voltage.As shown in Figure 10, now, the voltage being input into target gate is closed for first State voltage, namely now there is the conduction band in the corresponding region of target gate compared to valence band closer to fermi level in active layer Carrier in active layer in the corresponding region of target gate there occurs transoid, now in active layer in the corresponding region of target gate Electronics flow to form electric current, that is, in the OFF state time period, electric current is occurred in that in the corresponding region of target gate in active layer.

But, due to the second OFF state electricity is applied with the embodiment of the present invention on the auxiliary grid of target gate both sides Pressure so that in active layer the valence band in the corresponding region of auxiliary grid compared to conduction band closer to fermi level, it is auxiliary in active layer The hole helped in the corresponding region of grid is more.And in the voltage on two auxiliary grids and target gate voltage effect Under, two forward conductions PN junction in opposite direction is formed in active layer, and there is at least one PN junction just in two PN junctions Flow direction to electric current in conducting direction region corresponding with target gate in active layer is opposite.Further, since in active layer Hole in the corresponding region of two auxiliary grids is more, and the hole in the region can be corresponding with target gate in active layer Electronics in region is combined, so as to further reduce the flowing of electronics in active layer, reduces the OFF state electricity in active layer Stream, improves the ON state current of thin film transistor (TFT) and the ratio of off-state current.

In sum, in the control method of the display screen for being provided due to the present invention, apply to target gate in control circuit First standoff voltage, when applying the second standoff voltage to auxiliary grid, active layer can be produced in the presence of voltage on n grid Raw target PN junction, and the forward conduction direction of the target PN junction is opposite with the flow direction of electric current in other regions in active layer. Even if the carrier in the active layer there occurs transoid, the target PN junction also can play resistance to the flowing of carrier in active layer Only act on, so as to reduce the off-state current of TFT so that TFT can be used normally.

It should be noted that the control method embodiment of display screen embodiment, display screen in the embodiment of the present invention and Display device embodiment can be referred to mutually, and the embodiment of the present invention will not be described here.

Presently preferred embodiments of the present invention is these are only, is not intended to limit the invention, it is all in the spirit and principles in the present invention Within, any modification, equivalent substitution and improvements made etc. should be included within the scope of the present invention.

Claims (10)

1. a kind of display screen, it is characterised in that the display screen includes:Display panel and control circuit,
Array base palte includes in the display panel:Underlay substrate, and thin film transistor (TFT) on the underlay substrate is arranged on, institute Stating thin film transistor (TFT) includes:Source electrode, drain electrode, active layer and n grid, the material of the active layer is semi-conductor type carbon nanometer Pipe, the n is the integer more than or equal to 2,
It is described control circuit be connected with target gate and auxiliary grid in the n grid respectively, the target gate with The auxiliary grid is different, and the control circuit is used to be input into the first standoff voltage to target gate in the OFF state time period, in institute The OFF state time period is stated to auxiliary grid the second standoff voltage of input so that described to have in the presence of voltage on the n grid The positive and negative PN junction of target is formed in active layer, the target PN junction is removed in the forward conduction direction of the target PN junction and the active layer The flow direction of electric current is opposite in region outside region.
2. display screen according to claim 1, it is characterised in that the control circuit includes:Array base palte row drives GOA Circuit and auxiliary circuit,
The GOA circuits are connected with the target gate, and the auxiliary circuit is connected with the auxiliary grid, the GOA Circuit is used to be input into the first standoff voltage to the target gate in the OFF state time period, and the auxiliary circuit is used for described The OFF state time period is input into the second standoff voltage to the auxiliary grid.
3. display screen according to claim 2, it is characterised in that the n is the integer more than or equal to 3, the n grid Pole includes:X first grid and y second grid, the x and the y are the integer more than or equal to 1, and x+y=n, institute X first grid and the y second grid interval setting are stated,
The first grid adjacent with second grid is target gate in the x first grid, with the in the y second grid The adjacent second grid of one grid is auxiliary grid, and the GOA circuits are connected with the target gate, the auxiliary circuit with The auxiliary grid is connected;
When the GOA circuits are input into the first standoff voltage to the target gate, the auxiliary circuit is defeated to the auxiliary grid Target PN junction and auxiliary PN junction, the forward conduction side of the auxiliary PN junction are formed when entering the second standoff voltage, in the active layer To in opposite direction with the forward conduction of the target PN junction.
4. display screen according to claim 2, it is characterised in that the n is the integer more than or equal to 3, the n grid Pole includes:X first grid and y second grid, the x and the y are the integer more than or equal to 1, and x+y=n, the One grid group includes the x first grid, and two second grid groups include the y second grid, the first grid group Formed a line with described two second grid groups, and the first grid group is located between described two second grid groups,
The first grid adjacent with second grid is target gate in the x first grid, with the in the y second grid The adjacent second grid of one grid is auxiliary grid, and the GOA circuits are connected with the target gate, the auxiliary circuit with The auxiliary grid is connected;
When the GOA circuits are input into the first standoff voltage to the target gate, the auxiliary circuit is defeated to the auxiliary grid Target PN junction and auxiliary PN junction, the forward conduction side of the auxiliary PN junction are formed when entering the second standoff voltage, in the active layer To in opposite direction with the forward conduction of the target PN junction.
5. the display screen according to claim 3 or 4, it is characterised in that in the GOA circuits and the x first grid Each first grid be connected, the auxiliary circuit is connected with each second grid in y second grid,
The GOA circuits are used to be input into first standoff voltage, Yi Ji to the target gate in the OFF state time period ON time section is input into on-state voltage to described each first grid;
The auxiliary circuit is used to be input into second standoff voltage, Yi Ji to the auxiliary grid in the OFF state time period The ON time section is input into the on-state voltage to described each second grid.
6. display screen according to claim 1 and 2, it is characterised in that the n grid is respectively positioned on the same of the active layer Side,
The active layer is provided with the underlay substrate;
It is provided with the underlay substrate of the active layer and is provided with the source electrode and the drain electrode;
It is provided with the underlay substrate of the source electrode and the drain electrode and is provided with gate insulator;
It is provided with the underlay substrate of the gate insulator and is provided with the n grid;
It is provided with the underlay substrate of the n grid and is provided with passivation layer.
7. display screen according to claim 1 and 2, it is characterised in that the n grid is respectively positioned on the same of the active layer Side,
The n grid is provided with the underlay substrate;
It is provided with the underlay substrate of the n grid and is provided with gate insulator;
It is provided with and the active layer is provided with the underlay substrate of the gate insulator;
It is provided with the underlay substrate of the active layer and is provided with the source electrode and the drain electrode;
It is provided with the underlay substrate of the source electrode and the drain electrode and is provided with passivation layer.
8. a kind of display device, it is characterised in that the display device includes any described display screen of claim 1 to 7.
9. a kind of control method of display screen, it is characterised in that the display screen is any described display of claim 1 to 7 Screen, the display screen includes:Display panel and control circuit, array base palte includes in the display panel:Underlay substrate, and Thin film transistor (TFT) on the underlay substrate is arranged on, the thin film transistor (TFT) includes:Source electrode, drain electrode, active layer and n grid, The material of the active layer is semiconductor type carbon nano-tube, and the n is the integer more than or equal to 2, the control circuit difference It is connected with target gate and auxiliary grid in the n grid, the target gate is different from the auxiliary grid, described Method includes:
The control control circuit is input into the first standoff voltage in the OFF state time period to the target gate;
The control control circuit is input into the second standoff voltage in the OFF state time period to the auxiliary grid so that described On n grid in the presence of voltage, target PN junction, the positive guide of the target PN junction are formed in the active layer in thin film transistor (TFT) Logical direction is opposite with the flow direction of electric current in the region in the active layer in addition to the target PN junction region.
10. method according to claim 9, it is characterised in that the control circuit includes:GOA circuits and auxiliary circuit, The n is the integer more than or equal to 3, and the n grid includes:X first grid and y second grid, the x and described Y is the integer more than or equal to 1, and x+y=n, and the first grid adjacent with second grid is mesh in the x first grid Mark grid, the second grid adjacent with first grid is auxiliary grid, the GOA circuits and the x in the y second grid Each first grid in individual first grid is connected, each the second grid phase in the auxiliary circuit and y second grid Connection,
The control control circuit is input into the first standoff voltage in the OFF state time period to the target gate, including:Control The GOA circuits are input into the first standoff voltage in the OFF state time period to the target gate;
The control control circuit is input into the second standoff voltage in the OFF state time period to the auxiliary grid, including: The auxiliary circuit is controlled to be input into the second standoff voltage to the auxiliary grid in the OFF state time period;
Methods described also includes:
The GOA circuits are controlled to be input into on-state voltage to described each first grid in ON time section;
The auxiliary circuit is controlled to be input into the on-state voltage to described each second grid in ON time section.
CN201710003222.2A 2017-01-03 2017-01-03 Display screen and its control method, display device CN106783888A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201710003222.2A CN106783888A (en) 2017-01-03 2017-01-03 Display screen and its control method, display device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201710003222.2A CN106783888A (en) 2017-01-03 2017-01-03 Display screen and its control method, display device

Publications (1)

Publication Number Publication Date
CN106783888A true CN106783888A (en) 2017-05-31

Family

ID=58950948

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201710003222.2A CN106783888A (en) 2017-01-03 2017-01-03 Display screen and its control method, display device

Country Status (1)

Country Link
CN (1) CN106783888A (en)

Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0444712A1 (en) * 1990-03-02 1991-09-04 Nippon Telegraph And Telephone Corporation Multigate thin film transistor
JPH05251702A (en) * 1992-03-05 1993-09-28 Fujitsu Ltd Thin-film transistor and liquid-crystal display using same
US20010028058A1 (en) * 1996-06-21 2001-10-11 Lg Electronics, Inc. Thin film transistor and a method of forming the same
CN1638576A (en) * 2003-12-22 2005-07-13 Lg.菲利浦Lcd株式会社 Organic electro-luminescence device and fabricating method thereof
CN1767212A (en) * 2004-09-13 2006-05-03 三星电子株式会社 Transistor with carbon nanotube channel and method of manufacturing the same
CN103715207A (en) * 2013-12-31 2014-04-09 合肥京东方光电科技有限公司 Capacitor of TFT array substrate and manufacturing method and relevant device thereof
CN104240633A (en) * 2013-06-07 2014-12-24 上海和辉光电有限公司 Thin-film transistor, active matrix organic light-emitting diode assembly, and manufacturing method thereof
US20150380567A1 (en) * 2014-06-27 2015-12-31 Lg Display Co., Ltd. Thin film transistor of display apparatus

Patent Citations (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0444712A1 (en) * 1990-03-02 1991-09-04 Nippon Telegraph And Telephone Corporation Multigate thin film transistor
JPH05251702A (en) * 1992-03-05 1993-09-28 Fujitsu Ltd Thin-film transistor and liquid-crystal display using same
US20010028058A1 (en) * 1996-06-21 2001-10-11 Lg Electronics, Inc. Thin film transistor and a method of forming the same
CN1638576A (en) * 2003-12-22 2005-07-13 Lg.菲利浦Lcd株式会社 Organic electro-luminescence device and fabricating method thereof
CN1767212A (en) * 2004-09-13 2006-05-03 三星电子株式会社 Transistor with carbon nanotube channel and method of manufacturing the same
CN104240633A (en) * 2013-06-07 2014-12-24 上海和辉光电有限公司 Thin-film transistor, active matrix organic light-emitting diode assembly, and manufacturing method thereof
CN103715207A (en) * 2013-12-31 2014-04-09 合肥京东方光电科技有限公司 Capacitor of TFT array substrate and manufacturing method and relevant device thereof
US20150380567A1 (en) * 2014-06-27 2015-12-31 Lg Display Co., Ltd. Thin film transistor of display apparatus

Similar Documents

Publication Publication Date Title
JP5969995B2 (en) Method for manufacturing oxide thin film transistor array
CN103489824B (en) A kind of array base palte and preparation method thereof and display device
US9929277B2 (en) Thin film transistor and fabrication method thereof, array substrate and display
CN103400862B (en) Semiconductor device
Hayashi et al. Circuits using uniform TFTs based on amorphous In‐Ga‐Zn‐O
CN104332411B (en) Semiconductor device and its manufacture method
US9488890B2 (en) Semiconductor device and method for manufacturing the same
JP5775253B2 (en) Thin film transistor substrate and manufacturing method thereof
KR101512818B1 (en) Oxide semiconductor transistor and method of manufacturing the same
KR100729043B1 (en) Transparent Thin Film Transistor and Fabrication Method for the same
CN105074806B (en) Semiconductor device, drive circuit and display device
CN104637925B (en) Array base palte and its manufacture method for display panel
TWI585985B (en) Thin film transistor and method of making the same
CN100474621C (en) Semiconductor device and manufacturing method thereof
US8659017B2 (en) Array substrate and method of fabricating the same
US9818813B2 (en) Method for producing array substrate and array substrate
KR20110054045A (en) Semiconductor device and manufacturing method thereof
TWI582993B (en) Semiconductor device
US9230951B2 (en) Antistatic device of display device and method of manufacturing the same
US8586979B2 (en) Oxide semiconductor transistor and method of manufacturing the same
CN103299429B (en) Active-matrix substrate and manufacture method thereof and display floater
CN104282769B (en) Thin film transistor manufacturing method, and manufacturing method of array substrate
CN103413812B (en) Array base palte and preparation method thereof, display device
JP2006041457A (en) Thin film transistor structure and its manufacturing method
US10013124B2 (en) Array substrate, touch screen, touch display device, and fabrication method thereof

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination