CN106782644A - SiDNA sequences are generated and recognition methods and device - Google Patents
SiDNA sequences are generated and recognition methods and device Download PDFInfo
- Publication number
- CN106782644A CN106782644A CN201611109619.1A CN201611109619A CN106782644A CN 106782644 A CN106782644 A CN 106782644A CN 201611109619 A CN201611109619 A CN 201611109619A CN 106782644 A CN106782644 A CN 106782644A
- Authority
- CN
- China
- Prior art keywords
- sidna
- phase inverter
- chip
- dna
- output end
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/41—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
- G11C11/413—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction
- G11C11/417—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing, timing or power reduction for memory cells of the field-effect type
- G11C11/419—Read-write [R-W] circuits
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Computer Hardware Design (AREA)
- Apparatus Associated With Microorganisms And Enzymes (AREA)
Abstract
A kind of semiconductor chip DNA sequence dna generation and recognition methods and device, by setting up some groups of in parallel and/or series connection the latch with buffer register between the operating voltage and common ground terminal voltage that the design phase is each semiconductor chip, that is SiDNA units, cause that latch realizes non-critical state through manufacture of semiconductor technique, 0 or 1 for fixing and differing is produced, so as to form the corresponding DNA sequence dna of the semiconductor chip.The present invention can be on the premise of chip size and processing step not be increased for each semiconductor chip generates a changeless sequence and reads the content of the sequence when needed.
Description
Technical field
It is specifically a kind of (semiconductor-based using SiDNA the present invention relates to a kind of technology of semiconductor design arts
Cause) and its adapter circuit detect and record on semiconductor chip the different information of CMOS transistor and be converted into 0/1 sequence
Method and device.
Background technology
Much study and show when CMOS transistor is produced, the length of grid, width, thickness, the concentration of filler etc.
The difference of random journey normal distribution is had, although these difference very littles can be to the electrical property of transistor such as threshold value electricity more
Pressure, drain-source current, gate voltage etc. produce difference slightly.The also all random and normal distributions of these differences.In design chips
Time, in order to consider the factor of these change at random, semiconductor manufacturers can all provide the journey normal distribution of chip design department
Mathematical Modeling.If not considering this data without this model or when designing, then product fine rate will be very low.
Existing chip sequence is general to be manually generated by way of electrical fuse is programmed, by several memory bitcells
The nonvolatile memory of composition is write information in the nonvolatile memory, and it is unique that this is read from memory
Chip identifier or part number identification are accorded with, but the realization of the technology needs the extra increase fuse programming work after semiconductor preparation
Skill, and excessive memory cell also results in unnecessary chip size increase.
The generation of existing chip id number also include using PUF (Physically Unclonable Functions,
The anti-clone of physics) technology realization, PUF technologies are recognized each using the variability of the unique physical characteristic of silicon chip and IC manufacturing processes
Individual silicon, judges their true or false, without using key or storage key.Because technology generation password is convenient, and
It also is difficult to replicate id number even with identical manufacturing process, therefore is usually used in security field.
Most typical PUF technologies application is SRAM (SRAM) PUF technologies, the semiconductor in the memory
Unit is designed as with symmetrical structure, the semiconductor unit is at logic critical condition.Once process for making
When producing the difference on processing procedure parameter, each semiconductor unit produces nonrandom logic state after powered up, so that by
The array that memory cell is constituted generates unique id number.As Chinese patent literature CN104347111A discloses (bulletin) day
2015.02.11, a kind of semiconductor device, the application of as above-mentioned typical SRAM PUF technologies are disclosed.
But the defect of above-mentioned SRAM PUF technologies is that stability is difficult to meet industrial requirement, the output knot of memory cell
Fruit is largely influenceed by peripheral circuit or external environment condition, and above-mentioned technical problem constitutes SRAM PUF technologies at this stage
In the main obstruction of application link.
The content of the invention
The present invention is directed to deficiencies of the prior art, proposes a kind of SiDNA sequences generation and recognition methods and dress
Put, the difference produced during semiconductor is made up of latch cicuit and buffer circuits is converted into 0 and 1 and they are stored
Get up, then read at any time.
The present invention is achieved by the following technical solutions：
The present invention relates to a kind of SiDNA sequence generating methods, it is characterised in that by the design phase be each semiconductor
Some groups of in parallel and/or series connection the locks with buffer register are set up between the operating voltage and common ground terminal voltage of chip
Storage, i.e. SiDNA units, cause that latch realizes non-critical state through manufacture of semiconductor technique, that is, produce fixed and differ
0 or 1, so as to form the corresponding DNA sequence dna of the semiconductor chip.
As shown in figure 1, being the DNA sequence dna being achieved according to the above method.Above-mentioned sequence is in chip design process
Matrix arrangement as shown in Figure 2 can also be used.
Described latch has mirror image.
It is two phase inverters of symmetrical coupled the present invention relates to a kind of SiDNA sequence generating units for realizing the above method
The latch of composition.
Described is symmetrical, refers to that the first phase inverter and the second phase inverter have the technologic symmetrical structure of manufacture of semiconductor.
Described coupling, is connected by the input of the first phase inverter with the output end of the second phase inverter, the second phase inverter
Input be connected with the output end of the first phase inverter, it is such design cause the first phase inverter it is defeated with the input of the second phase inverter
Go out and be able to anti-phase reinforcing.
A pair of buffer registers further preferably are provided with described SiDNA sequence generating units, the buffer register pair
Title is arranged at the both sides of above-mentioned latch.
The present invention relates to a kind of chip with SiDNA sequences, including：Several above-mentioned SiDNA sequence generating units with
And multistage reading mechanism, wherein：SiDNA cell distributions are connected in each position of chip and with multilevel scanning chain element.
Described multistage reading mechanism, is to include the multilevel scanning chain element of several sweep triggers for cascading, and this is swept
Retouch the input of trigger to be connected with the DNA ends or DNAC ends of the output end of above-mentioned latch or buffer register, when scanning is touched
Hair device will be corresponding in the triggered corresponding signal of generation of output end after receiving clock signal.
The present invention relates to a kind of system single chip, including：Several logics with I/O circuits being connected with bus respectively
Unit and a processing unit, the logic unit transmit data by bus and processing unit, and above-mentioned logic unit is dispersed throughout core
The diverse location of piece；Include one or more SiDNA units as described in above-mentioned any claim in the logic unit, often
The DNA information of the SiDNA units that the I/O circuits in individual logic unit will be attached thereto by bus is exported to treatment by bus
Unit, complete DNA sequence dna is integrated into by processing unit according to different logic units by corresponding DNA information.
Brief description of the drawings
Fig. 1 is DNA sequence dna schematic diagram of the present invention.
Fig. 2 is DNA sequence dna schematic layout pattern of the present invention；
Fig. 3 is embodiment SiDNA structural representations；
Fig. 4 is that embodiment SiDNA reads schematic diagram；
Fig. 5 has the chip schematic diagram of SiDNA sequences for embodiment；
Fig. 6 is embodiment signal timing diagram；
Fig. 7 is embodiment system single chip schematic diagram.
Specific embodiment
Embodiments of the invention are elaborated below, the present embodiment is carried out under premised on technical solution of the present invention
Implement, give detailed implementation method and specific operating process, but protection scope of the present invention is not limited to following implementations
Example.
Embodiment 1
As shown in figure 3, being a SiDNA sequence generating unit of the invention, specially two phase inverters of symmetrical coupled
The latch 1 of composition, wherein：Each phase inverter includes a NMOS tube N1 (N2) and a PMOS P1 (P2), wherein：P1's
Source electrode is connected with supply voltage Vdd, and drain electrode is connected with the drain electrode of N1 and constitutes input, and grid is connected with the grid of N1 and constitutes output
End, the source electrode of N1 is then connected with ground voltage Vss.
Described is symmetrical, refers to that the first phase inverter and the second phase inverter have the technologic symmetrical structure of manufacture of semiconductor,
I.e. P1 is identical from design parameter with P2, N1 and N2.
Described coupling, is connected by the input of the first phase inverter with the output end of the second phase inverter, the second phase inverter
Input be connected with the output end of the first phase inverter, it is such design cause the first phase inverter it is defeated with the input of the second phase inverter
Go out and be able to anti-phase reinforcing.
Due to being made the local different of technique, even if experiencing identical manufacturing process and parameter, two phase inverters according to
It is old will not be identical, wherein the channel width and length of metal-oxide-semiconductor, grid length, width and depth, doping concentration, distribution and
The difference of depth, the thickness of gate insulator etc. factor can produce influence to electric transistor, ultimately result in two instead
Phase device it is asymmetric.So that the output end of any one in two phase inverters is produced when deviateing critical condition, it is corresponding
Another phase inverter will further strengthen the result so that finally realize 0 or 1 output.
As shown in figure 4, being preferably further provided with a pair of buffer registers 2 in described SiDNA sequence generating units, this delays
Rush the both sides that register 2 is symmetricly set in above-mentioned latch 1.
Described buffer register can use phase inverter or other common semiconductor structures, it is preferred to use with described lock
First, second phase inverter identical structure in storage 1, the buffer register 2 in the present embodiment uses a NMOS tube N3 (N4)
The phase inverter constituted with a PMOS P3 (P4), for example：The source electrode of P4 is connected with supply voltage Vdd, the drain electrode drained with N4
It is connected and the output end with above-mentioned first phase inverter, the input of the second phase inverter is connected, the grid of P4 is connected with the grid of N4
DNAC ends are constituted, the source electrode of N4 is then connected with ground voltage Vss, the phase inverter of opposite side uses identical structure and constitutes DNA ends.
As shown in figure 4, be a scan chain cell for reading data in above-mentioned SiDNA units, including：One scanning
Trigger 3, the input of the sweep trigger 3 and the output end of above-mentioned latch or the DNA ends of buffer register or DNAC ends
It is connected, will be corresponding in the triggered corresponding signals of generation of output end Q after sweep trigger 3 receives clock signal.
The input of described sweep trigger 3 is further provided with MUX 4, and the MUX 4 includes multiple
Input and an output end, wherein：Any input and the output end of above-mentioned latch or the DNA of buffer register
End or DNAC ends are connected, and output end is connected with the input of sweep trigger 3, and by reading control signal and reading selection letter
Number realize piece choosing and output selection.
The above-mentioned scan chain cell of the present embodiment can further realize multi-stage cascade, so as to realize in Fig. 1 or Fig. 2
The reading of SiDNA arrays.
As shown in Figure 5 and Figure 6, it is a kind of chip and its control signal waveform with DNA sequence dna generation and read functions,
The chip includes：Several above-mentioned SiDNA units and multilevel scanning chain element, wherein：SiDNA cell distributions are in each of chip
Individual position is simultaneously connected with multilevel scanning chain element.
Each described position refers to：Above-mentioned SiDNA cell distributions are arranged at chip in the chip layout design phase
Different geometric positions.
Described multilevel scanning chain element is realized by sweep trigger in the present embodiment, per one-level scan chain cell bag
The sweep trigger 3 for including has for reading the input of DNA information, the selection end for receiving reading control signal, being used for
Data input pin, clock signal terminal and the output end Q of external information are received, wherein：When selection end receives reading control signal
When, DNA information will be read by input after the arrival of next clock edges, otherwise sweep trigger 3 is then by number
External information is received according to input, and next stage scan chain cell is transferred to eventually through output end Q.
Demultplexer 6 is preferably further provided between two neighboring scan chain cell, the input of the demultplexer 6
End is connected with the output end Q of sweep trigger 3, multiple output ends of demultplexer 6 respectively at other ports of chip 7 and
Next stage scan chain cell is connected.Selected by reading output of the selection information to the demultplexer 6, when scanning is triggered
When device 3 receives external information, the reading selection information under identical sequential will control demultplexer 6 to export the external information
To other ports of chip 7.
Similarly, when multiple inputs different port, above-mentioned multichannel respectively with chip 7 of described MUX 4
When one output end of distributor 6 and the input of SiDNA units are connected, then can be by reading the different sequential of selection information
The functions such as the transmission of other information in DNA sequence dna collection, the chip for realize the multilevel scanning chain element are set.
As shown in fig. 7, a kind of system single chip (System-on-a-chip, SoC) being related to for the present embodiment, the chip
Including：Several logic units 9 and a processing unit 10 with I/O circuits 8, the logic list being connected with bus 11 respectively
Data are transmitted by bus 11 and processing unit 10 in unit 9, and above-mentioned logic unit 9 is dispersed throughout the diverse location of chip.
One or more SiDNA units are further may include in described logic unit 9.I/O in each logic unit 9
The DNA information of the SiDNA units that circuit 8 will be attached thereto by bus 11 is exported to processing unit 10 by bus 11, by
Corresponding DNA information is integrated into complete DNA sequence dna by reason unit 10 according to different logic units 9.For example：Logic unit 9
The data block comprising DNA information is sent to bus 11, processing unit 10 is rearranged after receiving data block.In the data block
Can also further comprising information such as the addresses for rearranging.
In addition to above-mentioned application, SiDNA units can also realize circuit diagnostics.For example：When processing unit 10 does not receive certain
During individual 9 corresponding DNA information of specific logical unit, the logic unit 9 or its peripheral circuit are possible existing defects or damage, reality
Now to the quick positioning of chip circuit defect, and chip globality is can be used to ensure that, prevent chip from forging.
Claims (15)
1. a kind of SiDNA sequence generating methods, it is characterised in that by the work electricity that the design phase is each semiconductor chip
Some groups of in parallel and/or series connection the latch with buffer register, i.e. SiDNA are set up between pressure and common ground terminal voltage
Unit, causes that latch realizes non-critical state through manufacture of semiconductor technique, that is, 0 or 1 for fixing and differing is produced, so that shape
Into the corresponding DNA sequence dna of the semiconductor chip.
2. method according to claim 1, it is characterized in that, described latch has mirror image.
3. a kind of SiDNA sequence generating units for realizing the methods described of claim 1 or 2, it is characterised in that be two symmetrical couplings
The latch of the phase inverter composition of conjunction, wherein：Each phase inverter includes a NMOS tube and a PMOS, wherein：PMOS
Source electrode be connected with supply voltage Vdd, drain electrode is connected with the drain electrode of NMOS tube and constitutes input, the grid phase of grid and NMOS tube
Output end is even constituted, the source electrode of NMOS tube is then connected with ground voltage Vss.
4. SiDNA sequence generating units according to claim 3, it is characterized in that, described is symmetrical, refers to the first phase inverter
There is the technologic symmetrical structure of manufacture of semiconductor with the second phase inverter, i.e., two NMOS tubes and two PMOSs are joined from design
It is identical on number.
5. SiDNA sequence generating units according to claim 3, it is characterized in that, described coupling, by the first phase inverter
Input be connected with the output end of the second phase inverter, the input of the second phase inverter is connected with the output end of the first phase inverter,
Such design causes that the first phase inverter and the input and output of the second phase inverter are able to anti-phase reinforcing.
6. according to any described SiDNA sequence generating units in claim 3~5, it is characterized in that, described SiDNA sequences
A pair of buffer registers are provided with generation unit, the buffer register is symmetricly set in the both sides of above-mentioned latch.
7. SiDNA sequence generating units according to claim 6, it is characterized in that, described buffer register is using anti-phase
Device is realized.
8. SiDNA sequence generating units according to claim 6 or 7, it is characterized in that, described buffer register use with
First, second phase inverter identical structure is realized in described latch, wherein：The source electrode of the PMOS of buffer register and electricity
Source voltage is connected, and drain electrode is connected and output end, the input phase of the second phase inverter with the first phase inverter with the drain electrode of NMOS tube
Connect, the grid of PMOS is connected with the grid of NMOS tube and constitutes DNAC ends, and the source electrode of NMOS tube is then connected with ground voltage, opposite side
Phase inverter using identical structure and constituting DNA ends.
9. a kind of chip with SiDNA sequences, it is characterised in that including：Several are as described in any in claim 2~8
SiDNA sequence generating units and multistage reading mechanism, wherein：SiDNA cell distributions in each position of chip and with it is many
Level scan chain cell is connected.
10. the chip with SiDNA sequences according to claim 9, it is characterized in that, described multistage reading mechanism is
Multilevel scanning chain element including several sweep triggers for cascading.
11. chips with SiDNA sequences according to claim 10, it is characterized in that, described sweep trigger it is defeated
Enter end to be connected with the output end of above-mentioned latch or the DNA ends of buffer register or DNAC ends, when sweep trigger is received
Will be corresponding in the triggered corresponding signal of generation of output end after clock signal.
12. chips with SiDNA sequences according to claim 10, it is characterized in that, described multilevel scanning chain element
In be provided with MUX, the MUX includes multiple inputs and an output end, wherein：Any input
It is connected with the output end of above-mentioned latch or the DNA ends of buffer register or DNAC ends, the input of output end and sweep trigger
End is connected, and realizes that piece is selected and output selection by reading control signal and read select signal.
13. according to any described chip with SiDNA sequences in claim 9~12, it is characterized in that, swept two neighboring
Retouch and be provided with demultplexer between chain element, the input of the demultplexer is connected with the output end of sweep trigger, multichannel
Multiple output ends of distributor are connected respectively at other ports of chip and next stage scan chain cell.By reading selection letter
Cease and the output of the demultplexer is selected, when sweep trigger receives external information, the reading choosing under identical sequential
The information of selecting will control demultplexer to export to other ports of chip the external information.
A kind of 14. system single chips, it is characterised in that including：Several logics with I/O circuits being connected with bus respectively
Unit and a processing unit, the logic unit transmit data by bus and processing unit, and above-mentioned logic unit is dispersed throughout core
The diverse location of piece；
Include one or more SiDNA units as described in above-mentioned any claim in described logic unit, each is patrolled
The DNA information for collecting the SiDNA units that the I/O circuits in unit will be attached thereto by bus exports single to treatment by bus
Unit, complete DNA sequence dna is integrated into by processing unit according to different logic units by corresponding DNA information.
15. a kind of failure of chip diagnostic methods of the system single chip according to claim 14, it is characterised in that by comparing
The integrality of DNA sequence dna, obtains the normal operating conditions of counterlogic unit, so as to realize the quick fixed of chip circuit failure
Position.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611109619.1A CN106782644A (en) | 2016-12-06 | 2016-12-06 | SiDNA sequences are generated and recognition methods and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611109619.1A CN106782644A (en) | 2016-12-06 | 2016-12-06 | SiDNA sequences are generated and recognition methods and device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN106782644A true CN106782644A (en) | 2017-05-31 |
Family
ID=58879055
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201611109619.1A Pending CN106782644A (en) | 2016-12-06 | 2016-12-06 | SiDNA sequences are generated and recognition methods and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN106782644A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112468296A (en) * | 2020-11-26 | 2021-03-09 | 湖南国科微电子股份有限公司 | Key programming method, system, electronic equipment and storage medium |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101877248A (en) * | 2009-05-01 | 2010-11-03 | 索尼公司 | SIC (semiconductor integrated circuit), signal conditioning package and output data diffusion method |
| CN103971730A (en) * | 2013-02-01 | 2014-08-06 | 上海华虹宏力半导体制造有限公司 | Static random access memory unit circuit |
| CN104347111A (en) * | 2013-07-25 | 2015-02-11 | 瑞萨电子株式会社 | Semiconductor integrated circuit device |
-
2016
- 2016-12-06 CN CN201611109619.1A patent/CN106782644A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101877248A (en) * | 2009-05-01 | 2010-11-03 | 索尼公司 | SIC (semiconductor integrated circuit), signal conditioning package and output data diffusion method |
| CN103971730A (en) * | 2013-02-01 | 2014-08-06 | 上海华虹宏力半导体制造有限公司 | Static random access memory unit circuit |
| CN104347111A (en) * | 2013-07-25 | 2015-02-11 | 瑞萨电子株式会社 | Semiconductor integrated circuit device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112468296A (en) * | 2020-11-26 | 2021-03-09 | 湖南国科微电子股份有限公司 | Key programming method, system, electronic equipment and storage medium |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN105897249B (en) | A kind of number based on pin multiplexing trims system | |
| TWI392076B (en) | Low voltage programmable efuse with differential sensing scheme | |
| CN103107808B (en) | Duty cycle distortion correction circuitry | |
| CN101663816B (en) | Software programmable logic using spin transfer torque magnetoresistive devices | |
| US8191021B2 (en) | Single event transient mitigation and measurement in integrated circuits | |
| US6373771B1 (en) | Integrated fuse latch and shift register for efficient programming and fuse readout | |
| CN100505458C (en) | Fuse circuit | |
| KR100875786B1 (en) | Random number generation method and semiconductor integrated circuit device | |
| CN104579249B (en) | Scan flip-flop and related method | |
| US9431398B2 (en) | Semiconductor chip having a circuit with cross-coupled transistors to thwart reverse engineering | |
| JPH03183154A (en) | Integrated circuit chip which is manufactured into a shape of mutual connection by metal and logic cell array device which assumes the form of mask and demonstration as well as testing with respect to elements thereof | |
| CN112713894B (en) | Strong and weak mixed PUF circuit | |
| KR20120101837A (en) | Apparatus for generating random number | |
| TW200400514A (en) | Semiconductor integrated circuit and its testing method | |
| US9941886B2 (en) | Integrated circuit (IC) chip comprising an identification circuit | |
| US7975195B1 (en) | Scan architecture for full custom blocks with improved scan latch | |
| US7721168B2 (en) | eFuse programming data alignment verification | |
| US20190319810A1 (en) | Method and circuit for de-biasing puf bits | |
| Chellappa et al. | Improved circuits for microchip identification using SRAM mismatch | |
| US4583179A (en) | Semiconductor integrated circuit | |
| US4458163A (en) | Programmable architecture logic | |
| WO2005062212A1 (en) | Template-based domain-specific reconfigurable logic | |
| US10585143B2 (en) | Flip flop of a digital electronic chip | |
| CN106782644A (en) | SiDNA sequences are generated and recognition methods and device | |
| US6334208B1 (en) | Method and apparatus for in-system programming with a status bit |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| AD01 | Patent right deemed abandoned | ||
| AD01 | Patent right deemed abandoned |
Effective date of abandoning: 20230407 |