CN1067780C

CN1067780C - Practical ROM simulation type general-purpose computer development system

Info

Publication number: CN1067780C
Application number: CN93117609A
Authority: CN
Inventors: 阎辛
Original assignee: Individual
Current assignee: Individual
Priority date: 1993-09-10
Filing date: 1993-09-10
Publication date: 2001-06-27
Anticipated expiration: 2013-09-10
Also published as: CN1087188A

Abstract

The present invention discloses a computer stimulation development system which can develop and debug different target computer systems without the replacement of a stimulation head. The present invention adopts an ROM stimulation form, and the present invention completes breakpoint setting and state automatic switchover by setting breakpoint judgement and state control logic, knows the internal state of a target CPU by a method that a target CPU executes a debugged program of a certain section to make certain state at the internal part react on a stimulation bus and a latch connected with the bus latched, and changes the state of the internal part of the target CPU or carries out reading and writing operation to an external RAM of the target CPU by the target CPU executing a certain section of debugged program. Thus, the present invention has all the functions of the common market-sold CPU stimulation type computer stimulation development system.

Description

Practical ROM simulation computer development method

The present invention relates to a kind of practical ROM simulation computer development method, adopt the Computer Simulation development system (hereinafter to be referred as development system) of this method needn't change artificial head can to various be that the target computer system (hereinafter to be referred as goal systems) of program storage is developed debugging work with ROM (comprising PROM, EPROM and EEPROM) chip.

Existing development system can divide CPU emulation and ROM emulation two classes, the former replaces the CPU and the program storage of goal systems with emulation CPU and emulation RAM, goal systems is debugged exploitation, its shortcoming is that the artificial head part is not general---the goal systems that exploitation variety classes CPU constitutes need be changed different artificial heads, and the development system of Chu Shouing all belongs to this class in the market; The latter debugs exploitation with the program storage that emulation RAM replaces goal systems to goal systems.This development system is general, but present such development system does not all have solution how breakpoint is set, how to finish the switching of debugging and simulation status automatically and how target CPU internal state and external RAM thereof is carried out problems such as read-write operation, thereby development function is very limited.

Task of the present invention is that a kind of practical ROM simulation computer development method will be provided, this method is improved existing ROM simulation type development system, make its can accomplish need not to change artificial head can to various be that the goal systems of program storage is developed debugging work with the rom chip, possess all functions of the CPU simulation type development system of selling in the market again.

The function of ROM simulation type development system will reach the level of general commercially available CPU simulation type development system just must separate decision point setting, state automatic switchover and CPU internal state and these several problems of external RAM read-write operation thereof.Preceding two problems can breakpoint be judged and state control circuit is realized by being provided with.The 3rd problem realizes more complicated, because target CPU can not produce on its program storage socket with imitating signal, so can't understand the internal state of target CPU with conventional method.The present invention finishes by the following method: after target CPU carries out breakpoint address, control circuit makes target CPU carry out one section debugged program in the artificial head, this program cooperates the internal state that can make target CPU to be reacted to the latches that is connected on the emulation bus on the emulation bus with control circuit in the artificial head, and artificial head is understood target CPU internal state by this latch.The debugged program section that adopts said method to make target CPU carry out corresponding function can make target CPU finish to change internal state or its external RAM be carried out task such as read-write operation.

The present invention is described in further detail below with reference to accompanying drawing.

Figure one is a kind of logic figure that adopts development system of the present invention.(the artificial head part of only drawing among the figure, other parts are identical with general development system).

C1 is 28 pin emulation plugs among the figure, and it is inserted on the program storage socket of goal systems during exploitation; U0 is 8255 (programmable parallel interfaces), and the host computer system of development system (hereinafter to be referred as system) is controlled the various operations of artificial head by it; U1 is 62256 (32KRAM), and it is used for depositing debugged target program as emulation memory; U2 is 6264 (8KRAM), its low 4K is as the breakpoint address storer, each address of every correspondence 62256 wherein, set represents that this corresponding address is a breakpoint address, and it and U3 (74LS151---eight choosing-data selectors) constitute the breakpoint address decision circuitry in simulation status; The high 4K of U2 is temporary RAM in debugging mode; U5 and U6 are 74LS373 (eight ternary output latches), and the two deposits one the two unconditional steering order of byte---PC ← PC-2 jointly; U7 and U9 are 74LS245 (eight bidirectional bus switches), and they and U8 (74LS373) constitute the logic switch between emulation memory and emulation bus jointly; The double status latch of being target CPU of U8 is used for latching the state of the target cpu address bus A0-A7 of breakpoint place; U4 (74LS245) is used for cutting off the logical path between emulation memory and breakpoint address decision circuitry when emulation; U10 is 74LS139 (two 2-4 code translator), and U11 and U12 are 74LS74 (double D trigger); U10, U11 and U12 and other gate circuit constitute the artificial head control circuit jointly.

During use, earlier CT is inserted goal systems program storage socket, development system is resetted, systematic reset signal makes the whole sets of U11_1, U11_2, U12_1 and U12_2, then system by U0 with target program pack into U1, with the breakpoint address U2 that packs into, again with one two byte unconditional branch instruction (PC ← PC-2) pack into U5 and U6.Make the goal systems power-on reset during exploitation, this moment, artificial head was in debugging mode; The logic switch that U7, U8, U9 constitute is closed; Target CPU reader memory signals makes the output of U5 and U6 effective repeatedly, makes target CPU be forced to carry out repeatedly PC ← PC-2 instruction, thereby programmable counter among the target CPU " is remained where one is ".Make artificial head enter simulation status then, its method is: the Y2 end effective (low level) that makes U10_2 by U0, then the CP of U11_2 end is low level, then each mouthful of U0 line all is set to input state, because PC7 has pull-up resistor to be high level, thereby making each output terminal of U10_1 and U10_2 is high level, thereby bring out an existing positive transition and make its reset at the CP of U11_2, after target CPU runs through a complete PC ← PC-2 instruction, the CP end of U12_1 a saltus step also occurs and makes its reset, and artificial head enters simulation status; The logic switch that U7, U8, U9 constitute is opened; The output of U5 and U6 is blocked; Target CPU carries out the target program among the U1, and the output of U3 makes the U12_1 set when running into breakpoint, and artificial head returns debugging mode and sends interrupt request to system.Have no progeny in the system responses and can carry out read-write operation to U1 by U0.Operation to target CPU internal state and external RAM thereof can followingly be finished: replace former breakpoint with one section debugged program (effect of this section program is that the internal state of target CPU is appeared on the A0-A7) and sentence target program position down (its process is earlier former breakpoint to be sentenced down target program with this section program equal length to move to the high 4K of U2 and keep in when carrying out to breakpoint, then this section program is write into this position), and at EOP (end of program) place breaking, make artificial head enter simulation status then, at this moment target CPU does not carry out target program but is carrying out this debugged program, return debugging mode after carrying out breakpoint, the internal state of target CPU was latched among the U8 and can reads for U0 this moment.Last artificial head still adopts said method to make one section program of returning to form of target CPU execution recover its inner ruined state of possibility and returns former breakpoint address, can make it continue to carry out target program after artificial head moves back former target program original position and resets breakpoint.Change target CPU internal state and its external RAM is carried out read-write operation can adopt said method to carry out corresponding debugged program section to finish.In the whole simulation performance history, target CPU alternately operates emulation memory together with open system under development system control, finishes exploitation debugging work jointly.

Be provided with on-line switch K among the figure, when using the goal systems of 8 above CPU formations of the online exploitation of two or more artificial heads, A point multiple connection with each artificial head, and make the K closure (output synchronous control signal) of one of them artificial head, K in other artificial heads disconnects (reception synchronizing signal), like this, system just can use a plurality of artificial heads that the goal systems that 8 above CPU constitute is developed debugging work simultaneously.

The computer development system of introducing above as stated above can emulation 2764,27128,27256 etc. rom chip develop various goal systems, but capacity emulation 27512 grades that increase emulation RAM are the chip of high power capacity more, and it can be finished read-write target program, read-write target CPU internal state and external RAM thereof, breakpoint is set, functions such as (every instruction all are provided with breakpoint) is carried out in single step.The goal systems that the exploitation different CPU constitutes only need be carried out different simulating developer programs and get final product.

Adopt the structure of development system of the present invention also can make an independent artificial head, it and target CPU constitute a complete development system jointly.Figure two is logic schematic diagrams of its a kind of concrete structure.CT is 28 pin emulation plugs among the figure; U0 is 8255, is used for doing the interface of keyboard, light-emitting nixie tube display and serial port; U1 is 27256 (32KEPROM), is wherein depositing watchdog routine and the artificial debugging program of various CPU to native system; U2 (62256) is an emulation memory, is used for depositing the target program that is developed; U5, U6 and U7 are 74LS244 (eight unidirectional bus switches), and they play driving action on emulation bus; U3 (74LS373) is the status latch of target CPU, it makees the data working storage in write operation---because target CPU can not produce on its program storage socket with imitating signal, therefore, target CPU writes temporary register and write operation two to the write operation of RAM in the artificial head and I/O mouth by watchdog routine and CON (artificial head control circuit---comprise that breakpoint is judged, circuit such as state is changed automatically, write operation control) branchs that match and goes on foot and finish.

Claims

1, a kind of practical ROM simulation computer development method is characterized in that:

Judge and state control circuit is finished switching between simulation status and debugging mode by breakpoint.

Target CPU is carried out be used to the debugged program that changes its internal state to change its internal state by control circuit in the artificial head.

Target CPU is carried out be used for the debugged program that its external RAM is carried out read-write operation to come its external RAM is carried out read-write operation by control circuit in the artificial head.

Make target CPU carry out the debugged program that is used to its internal state is reflected on the emulation bus by control circuit in the artificial head and make its internal state be reflected at emulation bus, thereby the latches that is connected on this bus is understood target CPU internal state.

2, as claim 1 described development approach, the latch that it is characterized in that being connected on the emulation bus only is connected on the low eight bit address lines of emulation bus.

3, as claim 1 described development approach, it is characterized in that when target CPU carries out to breakpoint, control circuit forces target CPU to carry out one the two unconditional steering order of byte " PC ← PC-2 " repeatedly in the artificial head, thereby make target CPU under the situation of not destroying internal state, prepare at any time to carry out target program or debugged program, and then emulation memory is carried out read-write operation from former breakpoint succession.

4, as claim 1 described development approach, adopt the Computer Simulation development system of this method to make target CPU under the control of its control circuit, in the whole simulation performance history, alternately emulation memory is operated together with described development system, finished exploitation debugging work jointly.

5,, it is characterized in that adopting independent artificial head and complete Computer Simulation development system of the common formation of target CPU of this method as claim 1 described development approach.

6, as claim 1,5 described development approaches, target CPU is to match with control circuit by the watchdog routine in the artificial head that branch is write target CPU status latch and two steps of write operation finish to the write operation of artificial head.