CN106776188A - Bus failure injected system based on DSP and FPGA - Google Patents
Bus failure injected system based on DSP and FPGA Download PDFInfo
- Publication number
- CN106776188A CN106776188A CN201611260831.8A CN201611260831A CN106776188A CN 106776188 A CN106776188 A CN 106776188A CN 201611260831 A CN201611260831 A CN 201611260831A CN 106776188 A CN106776188 A CN 106776188A
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- fpga
- dsp
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- bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/26—Functional testing
- G06F11/263—Generation of test inputs, e.g. test vectors, patterns or sequences ; with adaptation of the tested hardware for testability with external testers
Abstract
The invention discloses a kind of bus failure injected system based on DSP and FPGA, including DSP primary processors, FPGA, host computer, ethernet interface module, D/A module, RS422 interface modules, RS485 interface modules, relay network, resistor network and memory module；Required fault mode configuration is carried out by being serially connected in bus system, RS422/RS485 interface modules are used for receiving the serial signal in bus, parallel signal is converted into by FPGA, after DSP is processed, the signal after FPGA controls D/A module and relay network output injection failure.The present invention is using hardware fault injection, it is possible to achieve physical layer, electrical layer, protocol hierarchy direct fault location function, the failure that more real analog hardware occurs in actual moving process add various failures in real time in bus apparatus proper communication.
Description
Technical field
The present invention relates to Failure Injection Technique, particularly a kind of bus failure injected system based on DSP and FPGA.
Background technology
It is near several next, RS-422, RS-485 bus, because its high real-time and high flexibility are widely adopted, but in reality
In, it is ensured that the high reliability of bus system, bus test is essential.
Existing method of testing using the pattern of positive test, for the excitation of input, tests the response of output mostly；I.e.
Make the more existing method of testing for taking direct fault location, be also only the fault simulation for carrying out physical level and protocol hierarchy,
The numerical portion failures such as short-circuit, breaking, serial/parallel impedance, signal replacement, signal lag are injected to signal, to the simulation part of signal
The direct fault location covering for dividing is not comprehensive, and can face various states and environmental change in actual bus operation.
The content of the invention
It is an object of the invention to provide a kind of bus failure injected system based on DSP and FPGA, being capable of emulation bus
The failure that hardware occurs in actual moving process during communication.
The technical solution for realizing the object of the invention is：A kind of bus failure injected system based on DSP and FPGA, bag
Include DSP primary processors, FPGA, host computer, ethernet interface module, D/A module, RS422 interface modules, RS485 interface modules,
Relay network, resistor network and memory module；
The RS422 interface modules and RS485 interface modules are arranged between serial bus and FPGA, for receiving serial ports
Data in bus, and it is sent to FPGA；
The FPGA is connected by data/address bus, address bus with DSP primary processors, and the data is activation that will be received is to DSP
Primary processor；
The DSP primary processors are connected by ethernet interface module with host computer, and the failure for receiving host computer transmission refers to
The data for receiving are carried out direct fault location, the data after generation direct fault location by order according to corresponding faulting instruction；
The FPGA is connected by D/A module with equipment end, and D/A module is used to for the data after direct fault location to be converted to simulation
Amount output；
The relay network and resistor network are arranged between D/A module and equipment end, disconnected by FPGA control relays
Open and connect, the resistor network is used to simulate series impedance or parallel impedance.
Compared with prior art, its remarkable advantage is the present invention：1) present invention sets in the test for not changing offer driving source
It is standby with equipment under test signal on the premise of, matching somebody with somebody for required failure is carried out by the direct fault location unit being serially connected in bus system
Put, change signal of communication, realization adds the function of various failures in bus apparatus proper communication；2) present invention is using hardware event
Barrier method for implanting, by the signal after analog output direct fault location, the failure that analog hardware occurs in actual moving process；3)
The present invention can set serial received baud rate according to the baud rate of agreement by host computer human-computer interaction interface in the application,
Different baud rate communication systems can be flexibly applied to directly as a module, with very strong flexibility；4) present invention
With good visualization interface, by ethernet communication, can be injected with transmission fault and ordered, can in real time inject failure；
5) present invention directly controls modules by FPGA, reduces system cost, circuit design is simplified, with sexual valence higher
Than.
Brief description of the drawings
Fig. 1 is bus failure injected system overall structure figure of the present invention based on DSP and FPGA.
Fig. 2 is the hardware structure diagram of bus failure injected system of the present invention based on DSP and FPGA.
Fig. 3 is the RS422 interface module schematic diagrams of bus failure injected system of the present invention based on DSP and FPGA.
Fig. 4 is the relay output principle figure of bus failure injected system of the present invention based on DSP and FPGA.
Fig. 5 is relay, the resistor network schematic diagram of bus failure injected system of the present invention based on DSP and FPGA.
Fig. 6 is the D/A module schematic diagram of bus failure injected system of the present invention based on DSP and FPGA.
Fig. 7 is the upper and lower machine flow chart of bus failure injected system of the present invention based on DSP and FPGA.
Specific embodiment
With reference to Fig. 1, Fig. 2, a kind of bus failure injected system based on DSP and FPGA of the invention, including DSP main process tasks
Device, FPGA, host computer, ethernet interface module, D/A module, RS422 interface modules, RS485 interface modules, relay network,
Resistor network and memory module；
The RS422 interface modules and RS485 interface modules are arranged between serial bus and FPGA, for receiving serial ports
Data in bus, and it is sent to FPGA；
The FPGA is connected by data/address bus, address bus with DSP primary processors, and the data is activation that will be received is to DSP
Primary processor；
The DSP primary processors are connected by ethernet interface module with host computer, and the failure for receiving host computer transmission refers to
The data for receiving are carried out direct fault location, the data after generation direct fault location by order according to corresponding faulting instruction；
The FPGA is connected by D/A module with equipment end, and D/A module is used to for the data after direct fault location to be converted to simulation
Amount output；
The relay network and resistor network are arranged between D/A module and equipment end, disconnected by FPGA control relays
Open and connect, the resistor network is used to simulate series impedance or parallel impedance.
Further, ethernet interface module uses W5300 chips, and DSP embeded processors are ADSP-BF532 chips.
Further, RS422 interface modules, RS485 interface modules include 65LBC184 interface chips and opto-coupler chip
6N137,65LBC184 interface chip are used for RS422 level to be changed with Transistor-Transistor Logic level, and opto-coupler chip 6N137 is used for the letter with FPGA
Number isolation.
Further, D/A module includes the AD5544 conversion chips and OP2177 operational amplifiers of 4 passages, 4 passages
AD5544 conversion chips are used for digital-to-analogue conversion, and OP2177 operational amplifiers are used for voltage amplitude regulation, common-mode voltage regulation.
Further, relay network realizes parallel output by TPIC6B595 chip drives relays；Controlled by FPGA
The break-make of relay processed, realizes the direct fault location of short-circuit, breaking, the serial/parallel row impedance of physical level.
Further, FPGA directly controls RS422/RS485 modules, D/A module, relay network, realizes RS422/
The reception of RS485 serial signals, and convert thereof into parallel signal and meet at DSP treatment；FPGA is controlled using three line serial modes
Output state, output serial data change over clock, the chip selection signal and SOD serial output data of TPIC6B595, passes through
TPIC6B595 chips realize parallel output；FPGA using four line serial modes control D/A module, output serial data clock,
The chip selection signal of AD5544, SOD serial output data and serial data loading signal.
The present invention carries out the configuration of required failure in the bus by concatenation, is received by RS422/RS485 interface modules
Signal in bus, by after DSP treatment, the signal after FPGA controls D/A module output injection failure is realized in bus
Various failures are added in equipment proper communication in real time.
In order that the objects, technical solutions and advantages of the present invention are more explicit, in conjunction with the accompanying drawings and embodiments to this hair
It is bright to describe in detail.
Embodiment
As shown in figure 1, the bus failure injected system based on DSP and FPGA, sets in the test for not changing offer driving source
It is standby with equipment under test signal on the premise of, required fault mode is carried out by the direct fault location unit being articulated in bus system
Configuration, change signal of communication, realization adds the function of various failures in real time in bus apparatus proper communication.
Such as Fig. 2 and Fig. 7, the bus failure injected system based on DSP and FPGA includes two parts of host computer and slave computer,
Host computer provides human-computer interaction interface using KingView design, for receiving the failure order that operating personnel assign, and by failure
Order is sent to slave computer.DSP, FPGA, W5300 etc. are initialized first after electricity on slave computer, then according to reality
Communication baud rate sets serial signal and receives baud rate, waits host computer direct fault location order, after receiving failure order, according to
Failure requirements are by controlling D/A module, relay network, the signal after output direct fault location.
As shown in Fig. 2 a kind of RS422/RS485 bus failure injected systems based on DSP and FPGA, including the main places of DSP
Reason device, FPGA coprocessors, host computer, ethernet interface module, D/A module, RS422 interface modules, RS485 interface modules, after
Appliance network and resistor network.DSP primary processors are connected by ethernet interface module with host computer, receive what host computer sent
Failure order, is connected with FPGA by data/address bus, address bus；RS422 interface modules, RS485 interface modules are used as serial ports
Communication module, is connected between FPGA and universal serial bus；RS422 interface modules, RS485 interface modules and FPGA are turned by level
Chip LVC4245A connections are changed, 5V and 3.3V level conversions is realized；Relay network, resistor network and D/A module and FPGA connect
Connect, by FPGA controlled outputs.
With reference to Fig. 2, Fig. 3 and Fig. 6, RS422/RS485 interface modules use 65LBC184 interface chips, complete RS422 electricity
It is flat to be changed with TTL, and the signal isolation with FPGA is realized by opto-coupler chip 6N137；D/A module is turned using the AD5544 of 4 passages
Chip is changed, digital-to-analogue conversion is completed, OP2177 operational amplifiers are selected, voltage amplitude regulation, common-mode voltage regulation is completed, so that real
The existing direct fault location of electric level；Relay network realizes parallel output by TPIC6B595 chip drives relays, passes through
The break-make of FPGA control relays, realizes the direct fault location of short-circuit, breaking, the serial/parallel row impedance of physical level.
With reference to Fig. 2-Fig. 4, FPGA inside RS422/RS485 module software designs, including serial baud rate generation unit, string
Row receiving unit and serial transmitting element, realize serial transceiver module function, receive serial signal baud rate, can be according to reality
The baud rate of signal is received, is set by host computer man-machine interface, realized by being divided to clock signal.Serial received unit is used
Multistage d type flip flop concatenation, after the input serial data circulation that will be received is changed to parallel data, carries out follow-up treatment；FPGA
Internal output module uses three line serial mode controlled output states, output serial data change over clock, the piece choosing of TPIC6B595
Signal and SOD serial output data, by TPIC6B595 chip drives relay parallel outputs；Different relays are controlled by FPGA
The break-make of device, can connect resistance between circuit different parts, so as to realize RS422/RS485 bus short circuits, open circuit, serial/parallel
The direct fault location of the physical levels such as row impedance.
D/A module is controlled using four line serial modes with reference to Fig. 2 and Fig. 5, FPGA inside D/A module, during output serial data
Clock, the chip selection signal of AD5544, SOD serial output data and serial data loading signal, control two passages difference of AD5544
The different magnitude of voltage of output can flexibly carry out the setting of magnitude of voltage, so as to realize RS422/RS485 as Difference signal pair
The direct fault location of the electric levels such as bus voltage amplitude adjusted, common-mode voltage regulation, the regulation of input voltage threshold value.Pass through simultaneously
The data of reception are stored in its fifo module and realize delay fault by FPGA；The data of reception are substituted for different data, such as the
A data bit flipping, then exported by DA, realize that data are replaced；Or change the tune that D/A module output speed realizes transmission rate
Section, carries out the direct fault location of protocol hierarchy.
Claims (5)
1. a kind of bus failure injected system based on DSP and FPGA, it is characterised in that：Including DSP primary processors, FPGA, on
Position machine, ethernet interface module, D/A module, RS422 interface modules, RS485 interface modules, relay network, resistor network and
Memory module；
The RS422 interface modules and RS485 interface modules are arranged between serial bus and FPGA, for receiving serial bus
On data, and be sent to FPGA；
The FPGA is connected by data/address bus, address bus with DSP primary processors, gives DSP main places the data is activation for receiving
Reason device；
The DSP primary processors are connected by ethernet interface module with host computer, receive the faulting instruction that host computer sends, root
The data for receiving are carried out with direct fault location, the data after generation direct fault location according to corresponding faulting instruction；
The FPGA is connected by D/A module with equipment end, and D/A module is defeated for the data after direct fault location to be converted into analog quantity
Go out；
The relay network and resistor network are arranged between D/A module and equipment end, by FPGA control relays disconnect and
Connection, the resistor network is used to simulate series impedance or parallel impedance.
2. the bus failure injected system based on DSP and FPGA according to claim 1, it is characterised in that Ethernet connects
Mouth mold block uses W5300 chips, and DSP embeded processors are ADSP-BF532 chips.
3. the bus failure injected system based on DSP and FPGA according to claim 1, it is characterised in that RS422 interfaces
Module, RS485 interface modules include that 65LBC184 interface chips and opto-coupler chip 6N137,65LBC184 interface chip are used for
RS422 level is changed with Transistor-Transistor Logic level, and opto-coupler chip 6N137 is used for the signal isolation with FPGA.
4. the bus failure injected system based on DSP and FPGA according to claim 1, it is characterised in that D/A module bag
The AD5544 conversion chips and OP2177 operational amplifiers of 4 passages are included, the AD5544 conversion chips of 4 passages are used for digital-to-analogue conversion,
OP2177 operational amplifiers are used for voltage amplitude regulation, common-mode voltage regulation.
5. RS422/RS485 bus failure injected systems based on DSP and FPGA according to claim 1, its feature exists
In relay network realizes parallel output by TPIC6B595 chip drives relays；By the break-make of FPGA control relays,
Realize the direct fault location of short-circuit, breaking, the serial/parallel row impedance of physical level.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611260831.8A CN106776188B (en) | 2016-12-30 | 2016-12-30 | Bus fault injection system based on DSP and FPGA |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201611260831.8A CN106776188B (en) | 2016-12-30 | 2016-12-30 | Bus fault injection system based on DSP and FPGA |
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| CN106776188A true CN106776188A (en) | 2017-05-31 |
| CN106776188B CN106776188B (en) | 2020-07-31 |
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| CN201611260831.8A Expired - Fee Related CN106776188B (en) | 2016-12-30 | 2016-12-30 | Bus fault injection system based on DSP and FPGA |
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Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN108334060A (en) * | 2018-03-15 | 2018-07-27 | 北京润科通用技术有限公司 | A kind of bus failure injection device |
| CN108469807A (en) * | 2018-03-29 | 2018-08-31 | 北京润科通用技术有限公司 | A kind of MVB bus fault injection system and method |
| CN108508295A (en) * | 2018-03-29 | 2018-09-07 | 北京润科通用技术有限公司 | A kind of switching value fault injection system and method |
| CN108958997A (en) * | 2018-05-23 | 2018-12-07 | 哈尔滨工业大学 | Universal serial bus fault simulation system and analogy method |
| CN109062740A (en) * | 2018-06-05 | 2018-12-21 | 北京电子工程总体研究所 | A kind of auxiliary Check System and method based on direct fault location |
| CN109696899A (en) * | 2017-10-20 | 2019-04-30 | 中国商用飞机有限责任公司 | A kind of dedicated quality synthesis evaluation system of aircraft ARINC429 bus |
| CN109947078A (en) * | 2019-03-20 | 2019-06-28 | 广州小鹏汽车科技有限公司 | Direct fault location unit and its board, real time fail method for implanting, device and equipment |
| CN110188053A (en) * | 2019-05-30 | 2019-08-30 | 北京润科通用技术有限公司 | Airborne databus delay fault injection device and method |
| CN110347537A (en) * | 2018-04-02 | 2019-10-18 | 北京振兴计量测试研究所 | Protocol layer bus failure injected system |
| CN111948472A (en) * | 2020-07-02 | 2020-11-17 | 中国航空无线电电子研究所 | Testability verification device for civil aircraft avionics product |
| CN113297108A (en) * | 2021-05-26 | 2021-08-24 | 上海创景信息科技有限公司 | Circuit structure suitable for half-duplex bus signal direction control and control method |
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| CN205301911U (en) * | 2016-01-04 | 2016-06-08 | 北京航空工程技术研究中心 | Embedded fault injection control system |
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| CN102622323A (en) * | 2012-03-27 | 2012-08-01 | 首都师范大学 | Data transmission management method based on switch matrix in dynamic configurable serial bus |
| CN205263644U (en) * | 2015-12-24 | 2016-05-25 | 珠海诺华科技有限公司 | Multibus fault injection system |
| CN205301911U (en) * | 2016-01-04 | 2016-06-08 | 北京航空工程技术研究中心 | Embedded fault injection control system |
Cited By (15)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN109696899B (en) * | 2017-10-20 | 2022-02-18 | 中国商用飞机有限责任公司 | Special quality comprehensive evaluation system for aircraft ARINC429 bus |
| CN109696899A (en) * | 2017-10-20 | 2019-04-30 | 中国商用飞机有限责任公司 | A kind of dedicated quality synthesis evaluation system of aircraft ARINC429 bus |
| CN108334060A (en) * | 2018-03-15 | 2018-07-27 | 北京润科通用技术有限公司 | A kind of bus failure injection device |
| CN108469807A (en) * | 2018-03-29 | 2018-08-31 | 北京润科通用技术有限公司 | A kind of MVB bus fault injection system and method |
| CN108508295A (en) * | 2018-03-29 | 2018-09-07 | 北京润科通用技术有限公司 | A kind of switching value fault injection system and method |
| CN110347537A (en) * | 2018-04-02 | 2019-10-18 | 北京振兴计量测试研究所 | Protocol layer bus failure injected system |
| CN108958997A (en) * | 2018-05-23 | 2018-12-07 | 哈尔滨工业大学 | Universal serial bus fault simulation system and analogy method |
| CN108958997B (en) * | 2018-05-23 | 2022-03-04 | 哈尔滨工业大学 | Serial bus fault simulation system and simulation method |
| CN109062740A (en) * | 2018-06-05 | 2018-12-21 | 北京电子工程总体研究所 | A kind of auxiliary Check System and method based on direct fault location |
| CN109947078A (en) * | 2019-03-20 | 2019-06-28 | 广州小鹏汽车科技有限公司 | Direct fault location unit and its board, real time fail method for implanting, device and equipment |
| CN110188053B (en) * | 2019-05-30 | 2020-12-01 | 北京润科通用技术有限公司 | Airborne data bus delay fault injection equipment and method |
| CN110188053A (en) * | 2019-05-30 | 2019-08-30 | 北京润科通用技术有限公司 | Airborne databus delay fault injection device and method |
| CN111948472A (en) * | 2020-07-02 | 2020-11-17 | 中国航空无线电电子研究所 | Testability verification device for civil aircraft avionics product |
| CN113297108A (en) * | 2021-05-26 | 2021-08-24 | 上海创景信息科技有限公司 | Circuit structure suitable for half-duplex bus signal direction control and control method |
| CN113297108B (en) * | 2021-05-26 | 2023-11-10 | 上海创景信息科技有限公司 | Circuit structure and control method suitable for half-duplex bus signal direction control |
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