CN113297108B - Circuit structure and control method suitable for half-duplex bus signal direction control - Google Patents
Circuit structure and control method suitable for half-duplex bus signal direction control Download PDFInfo
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- CN113297108B CN113297108B CN202110578178.4A CN202110578178A CN113297108B CN 113297108 B CN113297108 B CN 113297108B CN 202110578178 A CN202110578178 A CN 202110578178A CN 113297108 B CN113297108 B CN 113297108B
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- 238000004891 communication Methods 0.000 claims abstract description 14
- 238000002347 injection Methods 0.000 claims description 14
- 239000007924 injection Substances 0.000 claims description 14
- 230000008054 signal transmission Effects 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 description 4
- 230000005856 abnormality Effects 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 238000010223 real-time analysis Methods 0.000 description 1
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/10—Program control for peripheral devices
- G06F13/105—Program control for peripheral devices where the programme performs an input/output emulation function
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4221—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being an input/output bus, e.g. ISA bus, EISA bus, PCI bus, SCSI bus
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Abstract
The application provides a circuit structure suitable for half duplex bus signal direction control, comprising: the device comprises a control module, an ADC module, a bus PHY module and a high-speed analog switch module; the control module receives the PHY signal of the bus PHY module, analyzes the bus signal according to the PHY signal, and judges the communication direction of the bus signal according to a bus protocol; the control module sends a switch command to control the high-speed analog switch module; the ADC module receives an electrical signal of the bus; the control module is connected with the ADC module through a bus. The application also provides a control method suitable for half-duplex bus signal direction control. The application realizes the timely switching of the signal direction by adopting the high-speed analog switch module, and avoids the system communication error caused by the fact that the ACK signal and the like do not return in time.
Description
Technical Field
The application relates to the technical field of half-duplex data transmission, in particular to a circuit structure and a control method suitable for half-duplex bus signal direction control.
Background
Half Duplex (Half Duplex) data transmission means that data can be transmitted in both directions of one signal carrier, but cannot be transmitted simultaneously. For example, using a technique with half duplex transmission on a local area network, a workstation may send data on the line and then immediately receive data on the line, the data coming from the direction in which the data was just transmitted. Half duplex can transfer information from a to B or B to a at any time during the communication process, but only one direction of transmission exists. When half duplex mode is adopted, the transmitter and the receiver at each end of the communication system are switched to the communication line through the transmit/receive switch to switch the direction, so that time delay is generated.
The existing circuit mostly adopts a relay, and the switching speed of the relay is far lower than that of a high-speed analog switch, so that the communication direction of a high-speed bus with the communication speed of more than 1M like CAN and 1553B CAN not be switched in time. Particularly, for the ACK signal, the CAN bus has a high requirement for real-time performance of the ACK signal, and if the ACK signal cannot be returned, an abnormality of the communication system occurs. In the prior art, when the main control chip is used for judging that the bus signal is in the ACK section, the main control chip autonomously generates an ACK signal and returns the ACK signal to the transmitting end, so that if the receiving end of the bus does not send the ACK signal due to data receiving errors, the transmitting end of the bus receives the ACK signal, and system communication abnormality can be caused.
Through retrieval, patent document CN211042350U discloses an ultrasonic flowmeter receiving and transmitting channel switching circuit, which comprises a signal direction switching circuit and a channel selection circuit; the signal direction switching circuit realizes the switching of ultrasonic signal receiving and sending through the double-pole double-throw contact of the relay K1; the channel selection circuit realizes that the two transducers alternately transmit and receive ultrasonic signals through two normally open contacts of the relay K1; the double-pole double-throw contact in the signal direction selection circuit is correspondingly connected in series with the two normally open contacts in the channel selection circuit respectively. The prior art adopts a relay to switch the signal direction, but has the defect that the real-time switching of the signal direction of a high-speed signal line cannot be realized.
Therefore, there is a need to develop a control circuit structure and a control method for switching the signal direction of the half-duplex bus in real time.
Disclosure of Invention
Aiming at the defects in the prior art, the application aims to provide a circuit structure and a control method suitable for half-duplex bus signal direction control, and solves the problem of real-time accurate control of the bus signal direction.
According to the present application, there is provided a circuit structure suitable for half duplex bus signal direction control, comprising: the device comprises a control module, an ADC module, a bus PHY module and a high-speed analog switch module;
the control module receives the PHY signal of the bus PHY module, analyzes the bus signal according to the PHY signal, and judges the communication direction of the bus signal according to a bus protocol; the control module sends a switch command to control the high-speed analog switch module; the ADC module receives an electrical signal of the bus; the control module is connected with the ADC module through a bus.
Preferably, the method further comprises fault injection or other bus physical layer application modules, wherein the fault injection or other bus physical layer application modules are arranged in a single direction of the bus physical layer.
Preferably, the fault injection or other bus physical layer application module inputs signals from an input port, outputs signals from an output port, and performs fault injection or other physical layer application.
Preferably, the bus further comprises an input port and an output port, and the input port and the output port are cascaded on a physical line of the bus.
Preferably, the high-speed analog switch module is provided with four high-speed analog switches S1, S2, S3 and S4, and the minimum on and off times of the high-speed analog switches are selected according to the baud rate of the bus.
Preferably, the bus protocol includes an RS485 protocol, a CAN protocol, or an IIC protocol.
Preferably, the bus PHY module includes an input PHY and an output PHY, the input PHY being disposed on the same bus as the input port, the output PHY and the output port being disposed on yet another same bus.
According to the control method suitable for half-duplex bus signal direction control provided by the application, the circuit structure suitable for half-duplex bus signal direction control is utilized to control the signal direction of the half-duplex bus, and the method comprises the following steps:
step 1: when the circuit structure suitable for half-duplex bus signal direction control is in an initial state, the high-speed analog switches S1 and S2 are turned on, the high-speed analog switches S3 and S4 are turned off, at this time, the input PHY is communicated with the input port, and the output PHY is communicated with the output port.
Preferably, the method further comprises the step 2: when the control module receives a bus start bit signal input into the PHY, the control module conducts the high-speed analog switch S3 and disconnects the high-speed analog switch S2; when the control module receives the bus end bit of the input PHY, the high-speed analog switch is restored to the initial state.
Preferably, the method further comprises the step 3: when the control module detects that the bus is about to be in an ACK section, the high-speed analog switch S4 is turned on, and the high-speed analog switch S3 is turned off; when the control module judges that the ACK section is about to end, the high-speed analog switch S3 is turned on, and the high-speed analog switch S4 is turned off until the bus signal transmission is completed.
Compared with the prior art, the application has the following beneficial effects:
1. the application realizes the timely switching of the signal direction by adopting the high-speed analog switch module, and avoids the system communication error caused by the fact that the ACK signal and the like do not return in time.
2. The application analyzes the bus signals formed by the control module and the bus PHY module, thereby realizing real-time analysis of multiple paths of signals and real-time control of signal directions by utilizing the advantages of a large number of IO ports in the control module and parallel high-speed processing.
3. The application can realize the signal direction switching of the multi-path half-duplex bus by utilizing the high-speed analog switch, the bus PHY module and the ADC module, thereby realizing the application of data monitoring, electric signal acquisition, fault injection and the like on the multi-path half-duplex bus.
Drawings
Other features, objects and advantages of the present application will become more apparent upon reading of the detailed description of non-limiting embodiments, given with reference to the accompanying drawings in which:
fig. 1 is an overall schematic diagram of a circuit structure suitable for half-duplex bus signal direction control in the present application.
Detailed Description
The present application will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the present application, but are not intended to limit the application in any way. It should be noted that variations and modifications could be made by those skilled in the art without departing from the inventive concept. These are all within the scope of the present application.
As shown in fig. 1, the present application provides a circuit structure suitable for half duplex bus signal direction control, comprising: the system comprises a control module, an ADC module, a bus PHY module, a high-speed analog switch module and a fault injection or other bus physical layer application module.
The control module receives the PHY signal of the bus PHY module, analyzes the bus signal according to the PHY signal, judges the communication direction of the bus signal according to a bus protocol, wherein the bus protocol comprises an RS485 protocol, a CAN protocol or an IIC protocol, and the control module is an FPGA.
The high-speed analog switch module is provided with four high-speed analog switches S1, S2, S3 and S4, the minimum on and off time of the high-speed analog switch is selected according to the baud rate of the bus, and the control module sends a switch command to control the high-speed analog switch module.
The ADC module receives an electrical signal of the bus; the control module is connected with the ADC module through a bus.
The bus PHY module is a bus PHY chip for converting physical electrical signals on the bus into level signals acceptable by the control module.
The fault injection or other bus physical layer application module is arranged in a single direction of the bus physical layer, inputs signals through an input port, outputs signals through an output port and performs fault injection or other physical layer application.
If the circuit is used for a multipath bus, the circuit parts except the control module in the figure are only required to be duplicated in multipath.
The application also provides a control method suitable for half-duplex bus signal direction control, which uses the circuit structure suitable for half-duplex bus signal direction control to control the signal direction of the half-duplex bus, and comprises the following steps:
step 1: when the circuit structure suitable for half-duplex bus signal direction control is in an initial state, the high-speed analog switches S1 and S2 are turned on, the high-speed analog switches S3 and S4 are turned off, at this time, the input PHY is communicated with the input port, and the output PHY is communicated with the output port.
Step 2: when the control module receives a bus start bit signal input into the PHY, the control module conducts the high-speed analog switch S3 and disconnects the high-speed analog switch S2; when the control module receives the bus end bit of the input PHY, the high-speed analog switch is restored to the initial state. That is, when the signal is in the communication direction of the input port and the output port, the high-speed analog switches S1 and S3 are turned on, the high-speed analog switches S2 and S4 are turned off, and the forward signal can be used for fault injection or other physical layer applications.
Step 3: when the control module detects that the bus is about to be in an ACK section, the high-speed analog switch S4 is turned on, and the high-speed analog switch S3 is turned off; when the control module judges that the ACK section is about to end, the high-speed analog switch S3 is turned on, and the high-speed analog switch S4 is turned off until the bus signal transmission is completed.
Otherwise, when the control module receives the bus start bit signal of the output PHY, step 2 is to turn on the high-speed analog switch S4 and turn off the high-speed analog switch S1. When the control module receives the bus end bit of the output PHY, the switch is restored to the initial state. That is, when the signal is in the communication direction input from the output port and output from the input port, the high-speed analog switches S2 and S4 are turned on, the high-speed analog switches S1 and S3 are turned off, and the reverse signal is not subjected to fault injection or other physical layer application.
The application adopts a half-duplex bus signal direction control circuit composed of the high-speed analog switch module and the control module, and can timely return the ACK response of the bus receiving end to the transmitting end, thereby truly realizing the real-time accurate control of the bus signal direction.
Those skilled in the art will appreciate that the application provides a system and its individual devices, modules, units, etc. that can be implemented entirely by logic programming of method steps, in addition to being implemented as pure computer readable program code, in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers, etc. Therefore, the system and various devices, modules and units thereof provided by the application can be regarded as a hardware component, and the devices, modules and units for realizing various functions included in the system can also be regarded as structures in the hardware component; means, modules, and units for implementing the various functions may also be considered as either software modules for implementing the methods or structures within hardware components.
The foregoing describes specific embodiments of the present application. It is to be understood that the application is not limited to the particular embodiments described above, and that various changes or modifications may be made by those skilled in the art within the scope of the appended claims without affecting the spirit of the application. The embodiments of the application and the features of the embodiments may be combined with each other arbitrarily without conflict.
Claims (6)
1. A circuit structure suitable for half-duplex bus signal direction control, comprising: the device comprises a control module, an ADC module, a bus PHY module and a high-speed analog switch module;
the control module receives the PHY signal of the bus PHY module, analyzes the bus signal according to the PHY signal, and judges the communication direction of the bus signal according to a bus protocol;
the control module sends a switch command to control the high-speed analog switch module;
the ADC module receives an electrical signal of a bus;
the control module is connected with the ADC module through the bus;
the high-speed analog switch module is provided with four high-speed analog switches S1, S2, S3 and S4, and the minimum on-off time of the high-speed analog switches is selected according to the baud rate of the bus;
the signal direction control method of the half-duplex bus is carried out according to the circuit structure, and comprises the following steps:
step 1: when the circuit structure suitable for half-duplex bus signal direction control is in an initial state, the high-speed analog switches S1 and S2 are turned on, the high-speed analog switches S3 and S4 are turned off, and at the moment, the input PHY is communicated with the input port, and the output PHY is communicated with the output port;
further comprising the step 2:
when the control module receives a bus start bit signal input into the PHY, the control module conducts the high-speed analog switch S3 and disconnects the high-speed analog switch S2;
when the control module receives the bus end bit of the input PHY, the high-speed analog switch is restored to the initial state again;
further comprising the step 3:
when the control module detects that the bus is about to be in an ACK section, the high-speed analog switch S4 is turned on, and the high-speed analog switch S3 is turned off;
when the control module judges that the ACK section is about to end, the high-speed analog switch S3 is turned on, and the high-speed analog switch S4 is turned off until the bus signal transmission is completed.
2. The circuit structure of claim 1, further comprising a fault injection or other bus physical layer application module, the fault injection or other bus physical layer application module being disposed in a single direction of the bus physical layer.
3. The circuit structure of claim 2, wherein the fault injection or other bus physical layer application module inputs signals from an input port and outputs signals from an output port for fault injection or other physical layer application.
4. The circuit configuration for half duplex bus signal direction control according to claim 1, further comprising an input port and an output port, the input port and the output port being cascaded on a physical line of a bus.
5. The circuit structure of claim 1, wherein the bus protocol comprises RS485 protocol, CAN protocol, or IIC protocol.
6. The circuit structure of claim 4, wherein the bus PHY module includes an input PHY and an output PHY, the input PHY and the input port being disposed on a same bus, the output PHY and the output port being disposed on yet another same bus.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110578178.4A CN113297108B (en) | 2021-05-26 | 2021-05-26 | Circuit structure and control method suitable for half-duplex bus signal direction control |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202110578178.4A CN113297108B (en) | 2021-05-26 | 2021-05-26 | Circuit structure and control method suitable for half-duplex bus signal direction control |
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| CN113297108A CN113297108A (en) | 2021-08-24 |
| CN113297108B true CN113297108B (en) | 2023-11-10 |
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| CN106776188A (en) * | 2016-12-30 | 2017-05-31 | 南京理工大学 | Bus failure injected system based on DSP and FPGA |
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