CN106771612B - A kind of fusible resistance break verifying system and method based on ideal resistance - Google Patents
A kind of fusible resistance break verifying system and method based on ideal resistance Download PDFInfo
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- CN106771612B CN106771612B CN201611037379.9A CN201611037379A CN106771612B CN 106771612 B CN106771612 B CN 106771612B CN 201611037379 A CN201611037379 A CN 201611037379A CN 106771612 B CN106771612 B CN 106771612B
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
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Abstract
The invention discloses a kind of, and the fusible resistance break based on ideal resistance verifies system and method, this method comprises the following steps: verifying whether fusible resistance break itself can fuse according to the breakdown voltage of standard, and measures the standard requirements whether resistance after fusing meets reading circuit；Fusible resistance break is replaced with into ideal resistance to verify the fusible resistance break and be blown whether rear reading circuit can work normally and export corresponding data in verifying circuit, the deviation that the verifying of fusing resistor and the verifying of reading circuit and processing procedure deviate from can be carried out individual authentication it is possible to prevente effectively from away from caused read functions mistake due to caused by processing procedure by the present invention.
Description
Technical field
The present invention relates to fusible resistive arrangement fields, test more particularly to a kind of fusible resistance break based on ideal resistance
Demonstrate,prove system and method.
Background technique
As semiconductor dimensions are smaller and smaller, the integrated level of System on Chip/SoC is higher and higher, and EFUSE is fusible resistance break IP's answers
It is more and more extensive with range, it is lower and lower for the breakdown voltage requirement of fusing resistor EFUSE-LINK, for fusing resistor
The speed and performance requirement of reading circuit are also got higher therewith, therefore, the functional verification of EFUSE IP are required also to increase accordingly.
Simultaneously as having differences between PROCESS processing procedure and practical devices model, IP internal mass is fusible resistance break is in flow
The otherness occurred in journey increases, and the difficulty of fusing performance verifying and the functional verification of reading circuit of IP is increased therewith,
By the replacement of ideal resistance, guarantees the reliability of resistance value to verify the function of reading circuit, make the system of fusible resistance break
The design that the manufacturing process of technique and reading circuit is separately verified is made to be of practical significance and benefit
The verifying of existing EFUSE IP product is divided into 2 stages, and the first stage is whether to verify EFUSE-link itself
It can fuse according to the breakdown voltage of standard, and whether the resistance for needing to measure after fusing meets reading circuit
Standard requirements are being surveyed since this test verification process needs the continuous scanning in high-precision tester table and certain time
Time cost is tried, is a kind of very big consumption in tester table utilization rate and allowance for depreciation cost, second stage is to verify
EFUSE-link is blown whether rear reading circuit can work normally and export corresponding data, if melted in fusing process
The resistance value of resistance break deviates from since the influence appearance of processing procedure is biggish, then may cause reading circuit and do not work.
Summary of the invention
In order to overcome the deficiencies of the above existing technologies, what purpose of the present invention is to provide a kind of based on ideal resistance can
Fusing resistor verifies system and method, is ideal resistance RES_PPOSAB by replacing fusible resistance break, it is possible to prevente effectively from
Deviate from caused read functions mistake due to caused by processing procedure, it can be by the verifying of fusing resistor and the verifying of reading circuit and system
The deviation that journey deviates from carries out individual authentication.
In view of the above and other objects, the present invention proposes a kind of fusible resistance break verifying system based on ideal resistance,
Former fusible resistance break in the verifying circuit of Yu Kerong resistance break, is replaced with ideal resistance by the second stage of verifying.
Further, by adjusting the size of the ideal resistance, meet the resistance value of equivalent fusible resistance fusing front and back.
Further, which is the fusible resistance break of EFUSE.
Further, which is RES_PPOSAB ideal resistance.
Further, whether in the first stage of verifying, verifying fusible resistance break itself can be according to the fusing electricity of standard
Pressure fuses, and measures the standard requirements whether resistance after fusing meets reading circuit.
In order to achieve the above objectives, the present invention also provides a kind of fusible resistance break verification method based on ideal resistance, including
Following steps:
Step 1, verifies whether fusible resistance break itself can fuse according to the breakdown voltage of standard, and measures molten
Whether the resistance having no progeny meets the standard requirements of reading circuit；
Fusible resistance break is replaced with ideal resistance in verifying circuit to verify the fusible resistance break and be blown by step 2
Whether reading circuit can work normally and export corresponding data afterwards.
Further, in step 2, by adjusting the size of the ideal resistance, before meeting equivalent fusible resistance fusing
Resistance value afterwards.
Further, which is the fusible resistance break of EFUSE.
Further, which is RES_PPOSAB ideal resistance.
Further, in step 2, by replacement fusible resistance device be ideal resistance and with programmed circuit and reading
Sense circuit is connected.
Compared with prior art, a kind of fusible resistance break verifying system and method based on ideal resistance of the present invention is by replacing
Change the fusible resistance break of EFUSE-LINK be ideal resistance, by adjust RES_PPOSAB ideal resistance size, meet it is equivalent can
The resistance value of fusing resistor fusing front and back, it is possible to prevente effectively from as blowout current in fusing process caused by resistance value it is unstable
It is qualitative, the function of EFUSE IP reading circuit is verified with this.
Detailed description of the invention
Fig. 1-Fig. 3 is the extraneous measurement result variation schematic diagram that may cause that do not fused completely due to efuse；
Fig. 4 is the schematic diagram of EFUSE IP normal mode of operation in the specific embodiment of the invention；
Fig. 5 is the schematic diagram of EFUSE IP test job mode in the specific embodiment of the invention；
Fig. 6 is a kind of step flow chart of the fusible resistance break verification method based on ideal resistance of the present invention.
Specific embodiment
Below by way of specific specific example and embodiments of the present invention are described with reference to the drawings, those skilled in the art can
Understand further advantage and effect of the invention easily by content disclosed in the present specification.The present invention can also pass through other differences
Specific example implemented or applied, details in this specification can also be based on different perspectives and applications, without departing substantially from
Various modifications and change are carried out under spirit of the invention.
Fig. 1-Fig. 3 is the extraneous measurement result variation schematic diagram that may cause that do not fused completely due to efuse.As it can be seen that such as
Fruit occur fusing incomplete phenomenon is possible to will cause resistance value after fusing and is unsatisfactory for standard and causes reading circuit operating voltage
Not enough, the phenomenon that output error is read.
To solve the problems, such as that fusible resistance break verifies reading circuit read error in second stage, the present invention is in fusible power-off
In the verifying circuit of resistance, fusible resistance break is replaced with into RES_PPOSAB ideal resistance, by adjusting RES_PPOSAB desired electrical
The size of resistance meets the resistance value of equivalent fusible resistance fusing front and back, it is possible to prevente effectively from since blowout current was fusing
Resistance value unstability caused by journey verifies the function of EFUSE IP reading circuit with this.
Fig. 4 is the schematic diagram of EFUSE IP normal mode of operation in the specific embodiment of the invention.Fig. 5 is that the present invention is specific real
Apply the schematic diagram of EFUSE IP test job mode in example.Fuse indicates fusible resistance device in Fig. 4, will receive processing procedure and deviates from
Phenomena such as not exclusively fusing is generated, Rfuse is equivalent resistance RES_PPOSAB (for resistance device a kind of in technology library) device in Fig. 5
Part, hardly by processing procedure away from generating resistance deviation and not needing to fuse, 10 indicate reading circuit, and 20 indicate programming electricity
Road, resistance value after size Control when passing through design can achieve the unblown resistance value of requirement and fuse, will reason in circuit design
Think that resistance Rfuse is replaced fusible resistance break fuse.It is desired electrical by replacement EFUSE-LINK fusible resistance device
It hinders and is connected the working principle reached as prototype part with programming transistor and reading transistor, but greatly reduce device
Deviation caused by part is deviated from due to processing procedure.
Fig. 6 is a kind of step flow chart of the fusible resistance break verification method based on ideal resistance of the present invention.Such as Fig. 6 institute
Show, a kind of fusible resistance break verification method based on ideal resistance of the present invention includes the following steps:
Step 601, whether the verifying fusible resistance break of EFUSE-link itself can be melted according to the breakdown voltage of standard
It is disconnected, and measure the standard requirements whether resistance after fusing meets reading circuit；
Step 602, fusible resistance break is replaced with into RES_PPOSAB ideal resistance to verify EFUSE- in verifying circuit
Link is blown whether rear reading circuit can work normally and export corresponding data, is ideal resistance by replacing fusible resistance break
RES_PPOSAB, to avoid caused read functions mistake is deviated from due to caused by processing procedure, by the verifying of fusible resistance break and
The deviation that the verifying of reading circuit and processing procedure deviate from carries out individual authentication.
As it can be seen that the present invention is based on the verifyings of the fusible resistance break of ideal resistance to design, it is ideal by replacing fusible resistance break
Resistance RES_PPOSAB, it is possible to prevente effectively from deviate from caused read functions mistake due to caused by processing procedure, it can be by fusing electricity
The deviation that the verifying of resistance and the verifying of reading circuit and processing procedure deviate from carries out individual authentication.
In emulation experiment of the present invention, during verifying on silicon wafer, the resistance value of ideal resistance can be correspondingly placed into execute
Read operation measures the standard for whether meeting electric current and output valve respectively, as shown in table 1 and table 2.
Table 1
Table 2
Wherein, table 1 and table 2 are the one group of reference current standard value obtained using the present invention, by carrying out with test result
Compare, it is known that whether efuse resistance value test result is credible.
In conclusion a kind of fusible resistance break verifying system and method based on ideal resistance of the present invention passes through replacement
EFUSE-LINK is fusible, and resistance break is that ideal resistance is met equivalent fusible by adjusting the size of RES_PPOSAB ideal resistance
Resistance break fusing front and back resistance value, it is possible to prevente effectively from as blowout current in fusing process caused by resistance value it is unstable
Property, the function of EFUSE IP reading circuit is verified with this.
The above-described embodiments merely illustrate the principles and effects of the present invention, and is not intended to limit the present invention.Any
Without departing from the spirit and scope of the present invention, modifications and changes are made to the above embodiments by field technical staff.Therefore,
The scope of the present invention, should be as listed in the claims.
Claims (9)
1. a kind of fusible resistance break based on ideal resistance verifies system, it is characterised in that: in the first stage of verifying, verifying can
Whether fusing resistor itself can fuse according to the breakdown voltage of standard, and whether the resistance measured after fusing meets
The standard requirements of reading circuit；In the second stage of verifying, the verifying circuit of Yu Kerong resistance break, former fusible resistance break is replaced
It is changed to ideal resistance.
2. a kind of fusible resistance break based on ideal resistance as described in claim 1 verifies system, it is characterised in that: pass through tune
The size for saving the ideal resistance meets the resistance value of equivalent fusible resistance fusing front and back.
3. a kind of fusible resistance break based on ideal resistance as described in claim 1 verifies system, it is characterised in that: this is fusible
Resistance break is the fusible resistance break of EFUSE.
4. a kind of fusible resistance break based on ideal resistance as described in claim 1 verifies system, it is characterised in that: the ideal
Resistance is RES_PPOSAB ideal resistance.
5. a kind of fusible resistance break verification method based on ideal resistance, includes the following steps:
Step 1, verifies whether fusible resistance break itself can fuse according to the breakdown voltage of standard, and after measuring fusing
Resistance whether meet the standard requirements of reading circuit；
Fusible resistance break is replaced with ideal resistance in verifying circuit to verify after the fusible resistance break is blown and read by step 2
Whether sense circuit can work normally and export corresponding data.
6. a kind of fusible resistance break verification method based on ideal resistance as claimed in claim 5, it is characterised in that: in step
In two, by adjusting the size of the ideal resistance, meet the resistance value of equivalent fusible resistance fusing front and back.
7. a kind of fusible resistance break verification method based on ideal resistance as claimed in claim 6, it is characterised in that: this is fusible
Resistance break is the fusible resistance break of EFUSE.
8. a kind of fusible resistance break verification method based on ideal resistance as claimed in claim 6, it is characterised in that: the ideal
Resistance is RES_PPOSAB ideal resistance.
9. a kind of fusible resistance break verification method based on ideal resistance as claimed in claim 6, it is characterised in that: in step
In two, it is ideal resistance by replacement fusible resistance device and is connected with programmed circuit and reading circuit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201611037379.9A CN106771612B (en) | 2016-11-23 | 2016-11-23 | A kind of fusible resistance break verifying system and method based on ideal resistance |
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| CN201611037379.9A CN106771612B (en) | 2016-11-23 | 2016-11-23 | A kind of fusible resistance break verifying system and method based on ideal resistance |
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| CN106771612A CN106771612A (en) | 2017-05-31 |
| CN106771612B true CN106771612B (en) | 2019-07-23 |
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Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050254189A1 (en) * | 2004-05-07 | 2005-11-17 | Taiwan Semiconductor Manufacturing Co., Ltd. | ESD protection circuit with low parasitic capacitance |
| US8143902B2 (en) * | 2010-01-06 | 2012-03-27 | Mediatek Inc. | eFuse macro |
| CN102749575B (en) * | 2011-04-18 | 2015-10-07 | 安凯(广州)微电子技术有限公司 | Electronic fuse state reader |
| CN105336373B (en) * | 2014-07-23 | 2019-08-27 | 中芯国际集成电路制造(上海)有限公司 | The calibration system and calibration method of Efuse module and its blowout current |
| CN204214930U (en) * | 2014-09-22 | 2015-03-18 | 中芯国际集成电路制造(北京)有限公司 | The test structure of programmable electronic fuse |
| CN104882167A (en) * | 2015-06-03 | 2015-09-02 | 武汉新芯集成电路制造有限公司 | Reference unit for reading electronic fuse |
| CN105261392A (en) * | 2015-11-16 | 2016-01-20 | 西安华芯半导体有限公司 | Memorizing unit and method based on resistive random access memory (RRAM) |
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