CN106771518B

CN106771518B - Cascade trigger type current comparison circuit capable of reducing power consumption

Info

Publication number: CN106771518B
Application number: CN201611125730.XA
Authority: CN
Inventors: 林毅竟; 满雪成; 王虎; 张波
Original assignee: SG Micro Beijing Co Ltd
Current assignee: SG Micro Beijing Co Ltd
Priority date: 2016-12-09
Filing date: 2016-12-09
Publication date: 2020-01-17
Anticipated expiration: 2036-12-09
Also published as: CN106771518A

Abstract

A cascade trigger type current comparison circuit capable of reducing power consumption is characterized in that a front-stage comparator detects that a detected signal exceeds a front-stage threshold voltage, then a control logic circuit triggers a rear-stage comparator to detect the detected signal, and the rear-stage comparator detects the detected signal with higher precision than the front-stage comparator according to the comparison result of output current whether the detected signal exceeds the rear-stage threshold voltage or not; the power consumption reduction means that the rear-stage comparator is in a dormant state before being triggered, and the detection of the detected signal in the dormant state takes over the rear-stage comparator with higher power consumption by the front-stage comparator with lower power consumption, so that the detection precision is maintained, the power consumption is reduced, and the low-power consumption realization of the precision current comparison circuit is facilitated.

Description

Cascade trigger type current comparison circuit capable of reducing power consumption

Technical Field

The invention relates to a current comparison circuit, in particular to a cascade trigger type current comparison circuit for reducing power consumption, wherein the cascade trigger means that a front-stage comparator triggers a rear-stage comparator to detect a detected signal through a control logic circuit after detecting that the detected signal exceeds a front-stage threshold voltage, and the detection precision of the rear-stage comparator on the detected signal is higher than that of the front-stage comparator according to the comparison result of output current if the detected signal exceeds the rear-stage threshold voltage; the power consumption reduction means that the rear-stage comparator is in a dormant state before being triggered, and the detection of the detected signal in the dormant state takes over the rear-stage comparator with higher power consumption by the front-stage comparator with lower power consumption, so that the detection precision is maintained, the power consumption is reduced, and the low-power consumption realization of the precision current comparison circuit is facilitated.

Background

The current comparison circuit is widely applied to overcurrent detection of loads. In many applications, overcurrent detection of current is a critical link for system safety protection. Since the current is not easy to be compared directly, it is common practice to convert the current into voltage by a sensor (current sensor) and then perform detection and comparison. The medium-low current sensor often uses a resistive sensor, such as a precision resistor or the on-resistance of a MOS transistor. Sensors for high currents often use magnetoelectric sensors, for example, hall effect devices or transformers. For resistive sensors, because it is desirable to minimize power consumption, the voltage drop across the sense resistor from the measured current is typically small, which requires a high precision comparator to ensure sensing accuracy. The inventors have found that the power consumption of a high-precision comparator is high, which affects or does not facilitate the low-power implementation of a precision current comparison circuit.

Disclosure of Invention

Aiming at the defects or shortcomings in the prior art, the invention provides a cascade trigger type current comparison circuit capable of reducing power consumption, wherein cascade trigger refers to that a front-stage comparator detects that a detected signal exceeds a front-stage threshold voltage and then triggers a rear-stage comparator to detect the detected signal through a control logic circuit, and the detection precision of the rear-stage comparator on the detected signal is higher than that of the front-stage comparator according to the comparison result of output current whether the detected signal exceeds the rear-stage threshold voltage or not; the power consumption reduction means that the rear-stage comparator is in a dormant state before being triggered, and the detection of the detected signal in the dormant state takes over the rear-stage comparator with higher power consumption by the front-stage comparator with lower power consumption, so that the detection precision is maintained, the power consumption is reduced, and the low-power consumption realization of the precision current comparison circuit is facilitated.

The technical scheme of the invention is as follows:

the utility model provides a cascade trigger formula current comparison circuit of reduction power consumption which characterized in that includes preceding stage comparator and the back stage comparator that connects through control logic circuit, the back stage comparator has the enable end, the enable end is connected control logic circuit's enable signal output port, the preceding stage comparison result output of preceding stage comparator is connected control logic circuit's preceding stage comparison result input port, first input voltage node is all connected to the positive input of preceding stage comparator and back stage comparator, the second input voltage node is all connected to the negative sense input of preceding stage comparator and back stage comparator.

And a rear-stage comparison result output end of the rear-stage comparator outputs a comparison result of comparing the first input voltage with the second input voltage, namely a corresponding current comparison result.

The detection precision of the rear-stage comparator to the detected signal is higher than that of the front-stage comparator.

The front-stage comparator is provided with a front-stage threshold voltage, the rear-stage comparator is provided with a rear-stage threshold voltage, and the front-stage threshold voltage is smaller than the rear-stage threshold voltage.

When the voltage difference between the first input voltage and the second input voltage obtained by the front-stage comparator exceeds the front-stage threshold voltage, the control logic circuit triggers the enabling of the rear-stage comparator through an enabling signal.

The rear-stage comparator is in a sleep mode before the enabling signal is triggered, the rear-stage comparator compares the first input voltage with the second input voltage in the enabling state, and the rear-stage comparator returns to the sleep mode after one round of comparison is completed until the enabling end of the rear-stage comparator is triggered again by the control logic circuit.

The invention has the following technical effects: the cascade trigger type current comparison circuit capable of reducing power consumption can realize the hierarchical comparison by adopting the cascade trigger technology of the two-stage comparator, for example, the low-precision comparator is adopted in the non-alert area to continuously carry out the low-precision comparison, and the high-precision comparator is converted in the alert area to carry out the high-precision comparison, so that the final comparison result is given by the high-precision comparator, and the high precision of the comparison is effectively ensured on the whole.

The invention has the characteristics that: the cascade trigger type current comparison circuit capable of reducing power consumption can achieve lower power consumption while maintaining comparison precision through the combination of high-precision high power consumption and low-precision low power consumption. For example, the preceding comparator is low-precision and low-power (relatively speaking) and is used for continuously detecting or monitoring a signal to be measured, when the signal to be measured exceeds the preceding threshold value, i.e. enters an alarm region, the succeeding comparator is in a dormant state, the succeeding comparator is high-precision and high-power (relatively speaking), and the output end of the succeeding comparator outputs a final comparison result, i.e. a comparison result of the whole current comparison circuit, and the comparison result is high-precision. After the comparison of the later-stage comparator is completed, the control logic circuit enables the enable signal of the enable end of the later-stage comparator to return from 1 to 0, and the later-stage comparator enters a sleep mode.

Drawings

Fig. 1 is a schematic diagram of a structure of a cascaded triggered current comparison circuit for reducing power consumption according to the present invention.

The reference numbers are listed below: 1-a first input voltage node; 2-a second input voltage node; 4-preceding stage comparison result input port; 5-enable signal output port; 6-control logic circuit; vin1 — first input voltage; vin 2-second input voltage; COMP 1-later stage comparator; out 1-the post comparison result output; en-enable terminal; COMP 2-pre-stage comparator; out 2-preceding stage comparison result output.

Detailed Description

The invention is described below with reference to the accompanying drawing (fig. 1).

Fig. 1 is a schematic diagram of a structure of a cascaded triggered current comparison circuit for reducing power consumption according to the present invention. As shown in fig. 1, a cascaded trigger type current comparison circuit for reducing power consumption includes a front-stage comparator COMP2 and a rear-stage comparator COMP1 connected through a control logic circuit 6, where the rear-stage comparator COMP1 has an enable terminal en connected to an enable signal output port 5 of the control logic circuit 6, a front-stage comparison result output terminal out2 of the front-stage comparator COMP2 is connected to a front-stage comparison result input port 4 of the control logic circuit 6, positive direction input terminals (+) of the front-stage comparator COMP2 and the rear-stage comparator COMP1 are both connected to a first input voltage node 1, and negative direction input terminals (-) of the front-stage comparator COMP2 and the rear-stage comparator COMP1 are both connected to a second input voltage node 2. A post comparison result output end 1 of the post comparator COMP1 outputs a comparison result of the first input voltage Vin1 and the second input voltage Vin2, i.e., a corresponding current comparison result. The detection precision of the rear-stage comparator COMP1 on the detected signal is higher than that of the front-stage comparator COMP 2. The front-stage comparator COMP2 is provided with a front-stage threshold voltage (Vth1), the rear-stage comparator COMP1 is provided with a rear-stage threshold voltage (Vth2), and the front-stage threshold voltage Vth1 is smaller than the rear-stage threshold voltage Vth 2. When the front-stage comparator COMP2 obtains that the voltage difference between the first input voltage Vin1 and the second input voltage Vin2 exceeds the front-stage threshold voltage Vth1, the control logic circuit 6 triggers the enable of the rear-stage comparator COMP1 through an enable signal. The post comparator COMP1 is in sleep mode before the enable signal is triggered, the post comparator COMP1 compares the first input voltage Vin1 with the second input voltage Vin2 in the enabled state, and the post comparator COMP1 returns to sleep mode after completing one round of comparison until its enable terminal is triggered again by the control logic circuit 6. The first input voltage Vin1 and the second input voltage Vin2 are both collected by a sensor or a current sensor. The sensor or the current sensor collects voltage and the voltage is processed by the amplifier to become a first input voltage Vin1 and a second input voltage Vin 2.

The implementation scheme of the invention consists of a high-power-consumption precision comparator, a low-power-consumption low-precision comparator and a logic control circuit. The invention reduces the average power consumption while maintaining the precision by using the cascade triggering technology, so that the detection precision reaches or approaches the precision reached by using a precision resistance sensor, and simultaneously avoids the extra power consumption and the PCB area caused by using a precision measurement resistor.

The voltage at the input node 1, i.e. the first input voltage node 1, the voltage at the input node 2, i.e. the second input voltage node 2, are input by the sensor, and the positive and negative inputs of the following comparator COMP1 and the preceding comparator COMP2 are respectively connected to the nodes 1 and 2. The output out2 of the preceding comparator COMP2 is connected to the input port of the control logic (control logic circuit 6), i.e. the preceding comparison result input port 4, and the output port thereof, i.e. the enable signal output port 5, is connected to the enable terminal en of the following comparator COMP 2. The output out1 of the pre-stage comparator COMP1 is the final comparison result.

The post-stage comparator COMP1 and the pre-stage comparator COMP2 have threshold voltages Vth2 and Vth1, respectively. Pre-comparator COMP2 is always in an enabled state. When the voltage difference on the 1, 2 nodes exceeds Vth1, the output out2 of the preceding stage comparator COMP2 transitions from 0 to 1, causing the output of the control logic circuit 6, i.e., the enable signal, to transition from 0 to 1, so that the succeeding stage comparator COMP1 is enabled. If the voltage difference on the 1, 2 nodes exceeds Vth2, the post-stage comparison result output (out1) transitions from 0 to 1.

Because the accuracy of the front-stage comparator COMP2 is low, the power consumption of the front-stage comparator COMP2 is much lower than that of the high-accuracy rear-stage comparator COMP 1. COMP1 is only enabled when the input is greater than Vth1, saving power consumption. Meanwhile, the final comparison result is given by a high-precision comparator COMP2, so that the comparison precision is guaranteed.

As shown in fig. 1, the enabling of the post comparator COMP1 is triggered by a low power consumption, lower accuracy pre-comparator COMP2 which continuously detects the signal under test; the output out1 of the post comparator COMP1 as the final comparison result; the control logic enables the post comparator COMP1 to be set to 0 after the comparison of the post comparator COMP1 is completed, and the post comparator COMP1 enters the sleep mode. The invention can achieve lower power consumption while maintaining the comparison precision.

It is pointed out here that the above description is helpful for the person skilled in the art to understand the invention, but does not limit the scope of protection of the invention. Any such equivalents, modifications and/or omissions as may be made without departing from the spirit and scope of the invention may be resorted to.

Claims

1. A cascade trigger type current comparison circuit capable of reducing power consumption is characterized by comprising a front-stage comparator and a rear-stage comparator which are connected through a control logic circuit, wherein the rear-stage comparator is provided with an enabling end, the enabling end is connected with an enabling signal output port of the control logic circuit, a front-stage comparison result output end of the front-stage comparator is connected with a front-stage comparison result input port of the control logic circuit, positive input ends of the front-stage comparator and the rear-stage comparator are both connected with a first input voltage node, and negative input ends of the front-stage comparator and the rear-stage comparator are both connected with a second input voltage node;

the detection precision of the post comparator to the detected signal is higher than that of the pre comparator;

2. The cascade trigger type current comparison circuit with reduced power consumption as claimed in claim 1, wherein the output terminal of the post comparison result of the post comparator outputs the comparison result of the first input voltage compared with the second input voltage, i.e. the corresponding current comparison result.

3. The cascade trigger current comparator circuit for reducing power consumption of claim 1, wherein the pre-comparator is configured to have a pre-threshold voltage and the post-comparator is configured to have a post-threshold voltage, the pre-threshold voltage being less than the post-threshold voltage.

4. The cascade triggered current comparator circuit with reduced power consumption as claimed in claim 3, wherein said control logic circuit triggers said post comparator to enable by an enable signal when said pre-comparator obtains a voltage difference between a first input voltage and a second input voltage exceeding said pre-threshold voltage.