CN106740985B - Track axle counting type circuit shunting system - Google Patents
Track axle counting type circuit shunting system Download PDFInfo
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- CN106740985B CN106740985B CN201611009335.5A CN201611009335A CN106740985B CN 106740985 B CN106740985 B CN 106740985B CN 201611009335 A CN201611009335 A CN 201611009335A CN 106740985 B CN106740985 B CN 106740985B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B61—RAILWAYS
- B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
- B61L1/00—Devices along the route controlled by interaction with the vehicle or train
- B61L1/16—Devices for counting axles; Devices for counting vehicles
- B61L1/162—Devices for counting axles; Devices for counting vehicles characterised by the error correction
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B61—RAILWAYS
- B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
- B61L1/00—Devices along the route controlled by interaction with the vehicle or train
- B61L1/16—Devices for counting axles; Devices for counting vehicles
- B61L1/167—Circuit details
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B61—RAILWAYS
- B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
- B61L1/00—Devices along the route controlled by interaction with the vehicle or train
- B61L1/16—Devices for counting axles; Devices for counting vehicles
- B61L1/169—Diagnosis
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Abstract
A track axle counting type circuit shunting system is characterized in that four axle counting pulse signals generated by wheel sensors arranged at two ends of a track blocking section are used for automatically judging the four axle counting pulse signals, axles entering and exiting the track blocking section are counted, and when the number of the axles entering and exiting the track blocking section is the same or smaller than an error value, an occupation signal of the track blocking section is automatically invalidated. The pulse interference elimination unit filters narrow pulse interference and jitter interference of signal edges of the axle counting pulse signals, and the anti-interference capability is further improved. The maximum width of the filtered positive narrow pulse filtered by the pulse interference filtering unit can be adjusted by changing the magnitude of the outflow driving current of the forward current driver or the magnitude of the forward anti-interference capacitor; the maximum width of the filtered negative narrow pulse can be adjusted by changing the size of the outflow driving current of the reverse current driver or the size of the reverse anti-interference capacitor. The system is used to replace existing track shunt circuits.
Description
Technical Field
The invention relates to the technical field of track axle counting equipment, in particular to a track axle counting type circuit shunting system.
Background
The track circuit is badly shunted due to the influence of bad conducting objects on the track surface of the track circuit, and the track relay for controlling the track section can not normally act when a train or a locomotive occupies the track, so that the signal interlocking fails. When the axle counting sensor scheme is adopted, the mechanical sensor generates a signal when a train arrives by controlling the on-off of an electrode contact through a spring, and poor contact of a contact point and signal jitter interference are easily generated; the infrared ray of the infrared sensor is easily shielded by dust and sundries and is easily interfered by other illumination to generate interference pulses; the ultrasonic piezoelectric transducer cannot be effectively protected because the ultrasonic piezoelectric transducer is exposed outside, and is also easily influenced by interference of construction workers and other obstacles to generate interference pulses; the eddy current coil induction and the magnetic head sensor induction are easily affected by metal impurities, for example, when a railway constructor holds a shovel to slide over the magnetic head sensor, the magnetic head is easily interfered to judge, and an interference pulse is output. When a wheel enters or exits a detection interval, the various sensors also cause the edges of sensing signals to generate shaking pulses due to sensor vibration caused by the passing of a vehicle, self vibration of the wheel, shaking of contacts of the sensors and the like.
Disclosure of Invention
In order to solve the problem of poor shunting of the conventional track circuit, the invention provides a track axle counting type circuit shunting system which comprises a first wheel sensor, a second wheel sensor, a third wheel sensor, a fourth wheel sensor and an axle counting shunting unit.
The first wheel sensor, the second wheel sensor, the third wheel sensor and the fourth wheel sensor respectively output a first axle counting pulse signal, a second axle counting pulse signal, a third axle counting pulse signal and a fourth axle counting pulse signal; and the first axle counting pulse signal, the second axle counting pulse signal, the third axle counting pulse signal and the fourth axle counting pulse signal are sent to an axle counting shunt unit, and the axle counting shunt unit outputs a track block interval occupation signal.
The axle counting and shunting unit comprises a counting pulse generation module, a counter module, a comparison module and a zero clearing signal generation module.
The function of the counting pulse generation module is as follows: when the first axle counting pulse signal and the second axle counting pulse signal meet the entering logic state of the axle, or the third axle counting pulse signal and the fourth axle counting pulse signal meet the entering logic state of the axle, the counting pulse output end outputs a counting pulse; when the first axle counting pulse signal and the second axle counting pulse signal meet the outgoing logic state of the axle, or the third axle counting pulse signal and the fourth axle counting pulse signal meet the outgoing logic state of the axle, the countdown pulse output end outputs a countdown pulse.
The counter module functions to: the counting pulse generating module outputs an up counting pulse and the output thereof increases by 1, and the counting pulse generating module outputs a down counting pulse and the output thereof decreases by 1.
The function of the comparison module is: when the output of the counter module is greater than X, the output track block interval occupation signal is valid, otherwise, the output track block interval occupation signal is invalid; and X is an integer greater than or equal to 1.
The function of the zero clearing signal generation module is as follows: when the track block interval occupation signal is changed from effective to ineffective, a zero clearing pulse is generated in a delayed mode to enable the output of the counter module to be 0.
The track axle counting type circuit shunt system further comprises a first pulse interference filtering unit, a second pulse interference filtering unit, a third pulse interference filtering unit and a fourth pulse interference filtering unit.
The first axle counting pulse signal, the second axle counting pulse signal, the third axle counting pulse signal and the fourth axle counting pulse signal are respectively transmitted to the axle counting shunt unit after being filtered by the first pulse interference filtering unit, the second pulse interference filtering unit, the third pulse interference filtering unit and the fourth pulse interference filtering unit to filter interference waveforms.
The first pulse interference filtering unit, the second pulse interference filtering unit, the third pulse interference filtering unit and the fourth pulse interference filtering unit are pulse interference filtering units with the same structural parameters; the pulse interference filtering unit comprises a forward charging and discharging circuit, a reverse charging and discharging circuit and a data selector.
And the input signals of the forward charge and discharge circuit and the reverse charge and discharge circuit are input pulses of the pulse interference filtering unit.
The data selector is an alternative data selector; two data input ends of the data selector are respectively connected to the output ends of the forward charge-discharge circuit and the reverse charge-discharge circuit; the data output end of the data selector is an output pulse end of the pulse interference filtering unit; the data selector performs data selection control by the output pulse.
The forward charge-discharge circuit comprises a forward current driver, a forward anti-interference capacitor and a forward anti-interference Schmitt circuit; the input end of the forward current driver is the input end of a forward charging and discharging circuit, and the output of the forward current driver is connected to the input end of a forward anti-interference Schmitt circuit; one end of the forward anti-interference capacitor is connected to the input end of the forward anti-interference Schmitt circuit, and the other end of the forward anti-interference capacitor is connected to the public ground of the pulse interference filtering unit or a power supply.
The reverse charging and discharging circuit comprises a reverse current driver, a reverse anti-interference capacitor and a reverse anti-interference Schmitt circuit; the input end of the reverse current driver is the input end of the reverse charge-discharge circuit, and the output end of the reverse current driver is connected to the input end of the reverse anti-interference Schmitt circuit; one end of the reverse anti-interference capacitor is connected to the input end of the reverse anti-interference Schmitt circuit, and the other end of the reverse anti-interference capacitor is connected to the public ground of the pulse interference filtering unit or a power supply.
The output end of the forward anti-interference Schmitt circuit is the output end of the forward charging and discharging circuit, and the output end of the reverse anti-interference Schmitt circuit is the output end of the reverse charging and discharging circuit.
When the input of the forward current driver is at a high level, the output end of the forward current driver is driven by current and outputs driving current; when the input of the forward current driver is at a low level, the output end is driven by voltage and outputs a low level; when the input of the reverse current driver is at a low level, the output end of the reverse current driver is driven by current and outputs driving current; when the input of the reverse current driver is at a high level, the output end is driven by voltage and outputs a low level.
When the input of the forward current driver is at a high level, the output end of the forward current driver is driven by current and outputs constant current driving current; when the input of the reverse current driver is at a low level, the output end of the reverse current driver is driven by current and outputs constant current driving current.
When the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in the same phase relation, the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an anti-correlation system; when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in an anti-correlation system, the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an in-phase relationship.
The specific method that the data selector carries out data selection control by the output pulse is that when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in an in-phase relation and the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an anti-correlation relation, the low-level control data selector of the output pulse selects the output signal of the forward anti-interference Schmitt circuit to be sent to the output end of the data selector, and the high-level control data selector selects the output signal of the reverse anti-interference Schmitt circuit to be sent to the output end of the data selector; when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in an anti-correlation system and the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an in-phase relationship, the low-level control data selector of the output pulse selects the output signal of the reverse anti-interference Schmitt circuit to be sent to the output end of the data selector, and the high-level control data selector selects the output signal of the forward anti-interference Schmitt circuit to be sent to the output end of the data selector.
The positive narrow pulse width that the pulse interference filtering unit can filter controls through the size that changes the outflow drive current size of forward current driver or the size of forward anti-interference electric capacity, and the negative narrow pulse width that can filter controls through the size that changes the outflow drive current size of reverse current driver or the size of reverse anti-interference electric capacity.
The invention has the beneficial effects that: the track axle counting type circuit shunting system automatically judges 4 paths of axle counting pulse signals, counts axles entering and exiting a track block interval, and automatically invalidates an occupied signal of the track block interval when the number of the axles entering and exiting the track block interval is the same or smaller than an error value; the counting shaft pulse signal is filtered by the pulse interference filtering unit to remove narrow pulse interference and jitter interference of the signal edge, so that the anti-interference capability of the system is further improved, and the maximum width of a positive narrow pulse filtered by the pulse interference filtering unit can be adjusted by changing the size of an outflow driving current of the forward current driver or the size of a forward anti-interference capacitor; the maximum width of the filtered negative narrow pulse can be adjusted by changing the size of the outflow driving current of the reverse current driver or the size of the reverse anti-interference capacitor.
Drawings
FIG. 1 is an embodiment of a wheel sensor mounting location;
FIG. 2 is a block diagram of an embodiment of a track axle counting type circuit shunting system;
FIG. 3 is a block diagram of an embodiment of an axle counting and branching unit;
FIG. 4 is an exemplary waveform of the first axle counting pulse signal and the second axle counting pulse signal satisfying the entry logic state of the axle;
FIG. 5 is an exemplary waveform of the first axle counting pulse signal and the second axle counting pulse signal satisfying the exit logic state of the axle;
fig. 6 is an example waveform in which the third axle counting pulse signal and the fourth axle counting pulse signal satisfy the exit logic state of the axle;
FIG. 7 is an exemplary waveform of the entry logic state where the third axle counting pulse signal and the fourth axle counting pulse signal satisfy the axle;
FIG. 8 is an embodiment of an up-count pulse or down-count pulse generation circuit;
FIG. 9 shows an embodiment of an interference rejection unit;
FIG. 10 is a waveform of an embodiment of an impulse interference rejection unit;
FIG. 11 is a circuit of embodiment 1 of a forward current driver and a reverse current driver;
FIG. 12 is a forward current driver and reverse current driver embodiment 2 circuit;
FIG. 13 is a forward current driver and reverse current driver embodiment 3 circuit;
FIG. 14 is an embodiment of a counter module, a comparison module, and a clear signal generation module;
fig. 15 is an embodiment of a schmitt circuit having a high input impedance characteristic.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Fig. 1 shows an embodiment of a wheel sensor mounting position. In the embodiment of fig. 1, the first wheel sensor 201 is mounted on the inside of the right rail 102 on the vehicle axis B1. During the travel of the locomotive or train, when the wheel axle travels to the position of the car axis B1, the first wheel sensor 201 senses the wheel and outputs a valid first axle counting pulse signal. The first wheel sensor 201 may be installed on the outer side or the inner side of the right rail, or may be installed on the outer side or the inner side of the left rail at a symmetrical position, i.e., must be located on the same vehicle axis B1.
In the embodiment of FIG. 1, the second wheel sensor 202 is mounted inboard of the right rail 102 on the vehicle axis B2. During locomotive, train travel, when the wheel axle travels to the position of the car axis B2, the second wheel sensor 202 senses the wheel and outputs a valid second axle counting pulse signal. The second wheel sensor 202 may be mounted on the outside or inside of the right rail, or on the outside or inside of the left rail at a symmetrical position, i.e., must be on the same vehicle axis B2.
In the embodiment of fig. 1, the third wheel sensor 203 is mounted on the inside of the right rail 102 on the vehicle axis B3. During the travel of the locomotive or train, when the wheel axle travels to the position of the train axis B3, the third wheel sensor 203 senses the wheel and outputs a valid third axle pulse signal. The third wheel sensor 203 may be installed on the outer side or the inner side of the right rail, or on the outer side or the inner side of the left rail at a symmetrical position, i.e., must be located on the same vehicle axis B3.
In the embodiment of FIG. 1, the fourth wheel sensor 204 is mounted inboard of the right rail 102 on the vehicle axis B4. During locomotive, train travel, when the wheel axle travels to the position of the car axis B4, the fourth wheel sensor 204 senses the wheel and outputs a valid fourth axle counting pulse signal. The fourth wheel sensor 204 may be mounted on the right rail on the outer side or the inner side, or on the left rail on the outer side or the inner side symmetrically, i.e. necessarily on the same vehicle axis B4.
The wheel sensors may be the same type of sensor or different types of sensors among various axle counting sensors such as a mechanical sensor, an infrared sensor, an ultrasonic piezoelectric transducer, an eddy current coil sensor, and a magnetic head sensor. It is preferable that the same type of sensor be used as the first wheel sensor 201, the second wheel sensor 202, the third wheel sensor 203, and the fourth wheel sensor 204 at the same time.
Fig. 2 is a block diagram of an embodiment of a track axle counting type circuit shunting system. In the embodiment of the system shown in fig. 2, the first axle counting pulse signal M1, the second axle counting pulse signal M2, the third axle counting pulse signal M3 and the fourth axle counting pulse signal M4 output by the first wheel sensor 201, the second wheel sensor 202, the third wheel sensor 203 and the fourth wheel sensor 204 are sent to the axle counting and shunting unit 500, and the axle counting and shunting unit 500 outputs the track blocking interval occupation signal J1.
Fig. 3 is a block diagram of an embodiment of the axle counting and splitting unit, which includes a count pulse generating module 501, a counter module 502, a comparing module 503, and a clear signal generating module 504.
The first wheel sensor 201 and the second wheel sensor 202 are installed at one end of the track block section to detect whether the locomotive (train) enters or exits from the end, and the third wheel sensor 203 and the fourth wheel sensor 204 are installed at the other end of the track block section to detect whether the locomotive (train) enters or exits from the end.
Fig. 4 shows exemplary waveforms showing that the first axle counting pulse signal and the second axle counting pulse signal satisfy an entry logic state of the axle, and fig. 5 shows exemplary waveforms showing that the first axle counting pulse signal and the second axle counting pulse signal satisfy an exit logic state of the axle.
In the embodiment of fig. 1, when a locomotive (train) enters a track block section from the installation ends of the first wheel sensor 201 and the second wheel sensor 202, the first axle counting pulse signal M1 is firstly provided, and the second axle counting pulse signal M2 is provided later, and the distance between the axle line B1 and the axle line B2 of the installation position of the wheel sensor is smaller than the wheel diameter of the locomotive (train), so that M2 starts to be effective before the M1 effective signal disappears. The conditions for judging that the first axle counting pulse signal M1 and the second axle counting pulse signal M2 meet the entry logic state of the axle are as follows: while the second axle counting pulse signal M2 is active, the first axle counting pulse signal M1 changes from active to inactive. In fig. 4, in the embodiment, the signals M1 and M2 are both active low, and during the low period of the signal M2, the signal M1 changes from low to high to satisfy the logic state of the axle, the up-count pulse output terminal H1 outputs an up-count pulse, and the down-count pulse output terminal L1 outputs no pulse.
When the locomotive (train) exits the track block section from the first wheel sensor 201 and the second wheel sensor 202, the second axle counting pulse signal M2 is first followed by the first axle counting pulse signal M1, and the M1 is activated before the M2 active signal disappears. The conditions for judging that the first axle counting pulse signal M1 and the second axle counting pulse signal M2 satisfy the driving-out logic state of the axle are as follows: while the first axle counting pulse signal M1 is active, the second axle counting pulse signal M2 changes from active to inactive. In fig. 5, in the embodiment, the signals M1 and M2 are both active low, and during the low period of the signal M1, the signal M2 changes from low to high to satisfy the logic state of the axle, the down-count pulse output terminal L1 outputs a down-count pulse, and the up-count pulse output terminal H1 outputs no pulse.
Fig. 6 shows exemplary waveforms of the third axle counting pulse signal and the fourth axle counting pulse signal satisfying the exit logic state of the axle, and fig. 7 shows exemplary waveforms of the third axle counting pulse signal and the fourth axle counting pulse signal satisfying the entry logic state of the axle.
In the embodiment of fig. 1, when the locomotive (train) exits from the track block section from the mounting ends of the third wheel sensor 203 and the fourth wheel sensor 204, the third axle pulse signal M3 is firstly followed by the fourth axle pulse signal M4, and the distance between the axle line B3 and the axle line B4 of the mounting positions of the wheel sensors is smaller than the wheel diameter of the locomotive (train), so that the M4 starts to be effective before the M3 effective signal disappears. The conditions for judging that the third axle counting pulse signal M3 and the fourth axle counting pulse signal M4 satisfy the output logic state of the axle are as follows: while the fourth axle pulse signal M4 is active, the third axle pulse signal M3 changes from active to inactive. In fig. 6, in the embodiment, the signals M3 and M4 are both active low, and during the low period of the signal M4, the signal M3 changes from low to high to satisfy the logic state of the axle, the down-count pulse output terminal L1 outputs a down-count pulse, and the up-count pulse output terminal H1 outputs no pulse.
When a locomotive (train) enters a track block section from the mounting ends of the third wheel sensor 203 and the fourth wheel sensor 204, the fourth axle counting pulse signal M4 is firstly sent, the third axle counting pulse signal M3 is sent later, and the M3 is started to be effective before the effective signal M4 disappears. The conditions for judging that the third axle counting pulse signal M3 and the fourth axle counting pulse signal M4 satisfy the outgoing logical state of the axle are as follows: while the third axle pulse signal M3 is active, the fourth axle pulse signal M4 changes from active to inactive. In fig. 7, in the embodiment, the signals M3 and M4 are both active low, and during the low period of the signal M3, the signal M4 changes from low to high to satisfy the logic state of the axle, the up-count pulse output terminal H1 outputs an up-count pulse, and the down-count pulse output terminal L1 outputs no pulse.
Fig. 8 shows an up-count pulse or down-count pulse generation circuit embodiment. In fig. 8, the differentiating circuit consisting of C51, R51, and D51 can convert the rising edge in the K2 signal into a positive pulse; inverter F51 converts the negative count pulse signal to a positive count pulse signal. If K1 is M2 and K2 is M1 in fig. 8, the output of the nand gate F52 is the up-counting pulse H11; if K1 is M3 and K2 is M4 in fig. 8, the output of the nand gate F52 is the up-counting pulse H12; the counting pulse H11 and the counting pulse H12 are both negative pulses; in the count pulse generation block 501, when a negative pulse is output from either the count-up pulse H11 or the count-up pulse H12, the count-up pulse H1 outputs a negative pulse.
If K1 is M1 and K2 is M2 in fig. 8, the output of the nand gate F52 is the down-counting pulse L11; if K1 is M4 and K2 is M3 in fig. 8, the output of the nand gate F52 is the down-counting pulse L12; the count-down pulse L11 and the count-down pulse L12 are both negative pulses; in the count pulse generation block 501, when a negative pulse is output in either one of the count-down pulse L11 and the count-down pulse L12, the count-down pulse L1 outputs a negative pulse.
The counter module 502 is an up-down counter, and CP + is an up-counting pulse input terminal and CP-is a down-counting pulse input terminal. The output Q of the counter block 502 is provided to a comparison block 503. Let X in FIG. 3 equal 1; when the output Q of the counter module 502 is greater than 1, the output track block section occupation signal J1 is valid, which indicates that there is a locomotive (train) in the track block section; when the J1 is effective, the coil of the track relay is controlled to lose power, a red light circuit is switched on or the annunciator displays dangerous resistance to disable. When the output Q of the counter module 502 is less than or equal to 1, the output track block section occupation signal J1 is invalid, which indicates that there is no locomotive (train) in the track block section; when J1 is invalid, the coil of track relay is controlled to be electrified, so that a green light circuit is switched on or the signal machine displays safe traffic. X is used to allow the track block occupation signal J1 to be sent out normally when the axle counting signal has accidental errors (accidental interference pulses or pulse loss). The greater X, the greater the tolerance of the axle counting signal to accidental errors. R in the counter module 502 is a clear input. The comparison module 503 compares the 2 input data, and when the input data DA is greater than the input data DB, the output track block interval occupation signal J1 is valid; when the input data DA is equal to or less than the input data DB, the output track-closed section occupation signal J1 is invalidated.
The clear signal generation module 504 delays to generate a clear pulse to change the output of the counter module 502 to 0 when the track block interval occupancy signal changes from active to inactive. Taking X equal to 1 as an example, when the output of the counter module 502 changes from 2 to 1, the track block section occupancy signal changes from active to inactive, and the clear signal generation module 504 delays to generate a clear pulse to change the output of the counter module 502 to 0. Normally, when a locomotive (train) passes through a track block section, the output of the counter module 502 will count up to the number of axles of the locomotive (train) from 0, and then count down to 0. The effect of generating a zero clearing pulse by time delay is as follows: under normal conditions, if the output of the counter module 502 changes from 2 to 1 and the track blocking interval occupancy signal changes from active to inactive, the locomotive still has an axle in the track blocking interval, at this time, the clear signal generation module 504 immediately generates a clear pulse to change the output of the counter module 502 to 0, and after the remaining axles of the locomotive (train) are driven out of the track blocking interval, the output of the counter module 502 subtracts 1 from 0, an erroneous axle counting result occurs, and the comparison module 503 may output an erroneous determination result. If the zero clearing pulse is output to the counter module 502 after a certain time delay, the counter module 502 is cleared to 0 after the time delay, and as long as the time of the time delay is longer than the time required for the rest axles of the locomotive (train) to exit the track blocking section, the output of the counter module 502 is 0 after all the axles of the locomotive (train) exit the track blocking section, so that the system is ensured to count the axles of the next locomotive (train) normally. When the axle counting signal has accidental errors (accidental interference pulses or pulse loss), after all axles of the locomotive (train) are driven out of the track blocking interval, the output of the counter module 502 is less than or equal to X, and the zero clearing signal generating module 504 generates a zero clearing pulse in a delayed mode to enable the output of the counter module 502 to be changed from a value less than or equal to X to 0 when the occupied signal of the track blocking interval is changed from effective to invalid, so that the normal axle counting of the system for the next locomotive (train) can be guaranteed.
The function of the axle counting and shunting unit can be realized by various medium-scale logic circuits, and can also be realized by devices such as CPLD, FPGA, PAL, GAL and the like.
Fig. 9 shows an embodiment of the pulse interference filtering unit, which includes a forward charging/discharging circuit, a reverse charging/discharging circuit, and a data selector. In the embodiment of fig. 9, the forward current driver, the forward anti-interference capacitor, and the forward anti-interference schmitt circuit are respectively a current driver U11, a capacitor C11, and a schmitt circuit F11, and form a forward charging and discharging circuit; the reverse current driver, the reverse anti-interference capacitor and the reverse anti-interference Schmitt circuit are respectively a current driver U21, a capacitor C21 and a Schmitt circuit F21, and form a reverse charging and discharging circuit. One end of the capacitor C11 is connected with the input end of the Schmitt circuit F11, and the other end is connected to the common ground; one end of the capacitor C21 is connected to the input end of the Schmitt circuit F21, and the other end is connected to the common ground. P1 is the input pulse end, P2 is the output pulse end.
In the embodiment of fig. 9, the data selector T11 is an alternative data selector, the two data input signals and the output signal are in-phase, and the schmitt circuit F11 and the schmitt circuit F21 are in-phase and reverse-phase schmitt circuits, respectively, so that the output of the data selector T11 and the input signal of the schmitt circuit F11 are in-phase, and the output of the data selector T11 and the input signal of the schmitt circuit F21 are in reverse correlation. The function of the data selector T11 is: when the control terminal A is selected to be 0, outputting Y to be D1; when the control terminal a is selected to be 1, the output Y is D2. The output terminal Y (i.e. the pulse output terminal P2) of the data selector T11 is directly connected to the selection control terminal a of the data selector T11, and when the output pulse P2 is low, the data selector T11 is controlled to select the output signal a3 of the schmitt circuit F11 to be sent to the output terminal Y of the data selector; when the output pulse P2 is at a high level, the data selector T11 is controlled to select the output signal a4 of the schmitt circuit F21 to be supplied to the output terminal Y of the data selector.
Fig. 10 shows waveforms of an embodiment of the glitch filtering unit, which includes waveforms of an input pulse P1, an output A3 of the schmitt circuit F11, an output a4 of the schmitt circuit F21, and an output pulse P2. In fig. 9, when the input pulse P1 is kept at the low level for a long time, the point a1 is at the low level, and the output A3 of the schmitt circuit F11 is at the low level; when the input pulse P1 remains high for a long time, the point a1 is high, and the point A3 is high. When the input pulse P1 changes from high level to low level, the output a1 of the current driver U11 immediately changes to low level potential, and the output A3 immediately changes from high level to low level. When the input pulse P1 changes from low level to high level, the potential of a1 rises due to the charging of the capacitor C11 by the driving current output by the current driver U11, and when the charging time reaches T1 and the potential of a1 rises to reach and exceed the upper limit threshold voltage of the schmitt circuit F11, the potential of A3 changes from low level to high level; when the positive pulse width of the P1 is less than T1, the charging time is less than T1, the P1 becomes low level when the potential of the A1 does not reach the upper limit threshold voltage of the Schmitt circuit F11, the potential of the A1 immediately becomes low level potential, and the A3 maintains the low level state. In fig. 10, the initial states of P1 and A3 are low. The widths of the positive narrow pulse 11, the positive narrow pulse 12 and the positive narrow pulse 13 are all smaller than T1, the potential of A1 cannot reach or exceed the upper limit threshold voltage of a Schmitt circuit F11 through charging, and the state of A3 is not influenced; the width of the positive pulse 14 of P1 is greater than T1, so A3 changes from low to high after the rising edge of the positive pulse 14 of P1 by time T1. The falling edge of the positive pulse 14 of P1 changes A3 from high to low, the width of the positive pulse 15 of P1 is greater than T1, and A3 changes from low to high after the rising edge of the positive pulse 15 is over time T1. The falling edge of the P1 positive pulse 15 changes A3 from high to low, and the widths of the positive pulse 16, the positive pulse 17, and the positive pulse 18 of P1 are all smaller than T1, so that the positive pulse 16, the positive pulse 17, and the positive pulse 18 have no effect on A3, and A3 remains in a low state. The width of the positive pulse 19 of P1 is greater than T1, and A3 goes from low to high after the rising edge of the positive pulse 19 is over a time T1.
In fig. 9, when the input pulse P1 is kept at the low level for a long time, the point a2 is at the high level, and the output a4 of the schmitt circuit F21 is at the low level; when the input pulse P1 remains high for a long time, the point a2 is low and the point a4 is high. When the input pulse P1 changes from low level to high level, the output a2 of the current driver U21 immediately changes to low level potential, and the output a4 immediately changes from low level to high level. When the input pulse P1 changes from high level to low level, the potential of a2 rises due to the charging of the capacitor C21 by the driving current output by the current driver U21, and when the charging time reaches T2 and the potential of a2 rises to reach the upper limit threshold voltage of the schmitt circuit F21, the potential of a4 changes from high level to low level; when the negative pulse width of the P1 is less than T2, the charging time is less than T2, and the A2 potential does not rise to the upper threshold voltage of the Schmitt circuit F21, the P1 becomes high, the A2 immediately becomes low, and the A4 maintains high. In fig. 10, the initial states of P1 and a4 are low. The rising edge of the positive pulse 11 of P1 changes a4 from low to high, the negative pulse 20 of P1 has a width greater than T2, and a4 changes from high to low after the falling edge of the negative pulse 20 for a time T2. The rising edge of the positive pulse 12 of P1 changes a4 from low to high, and the widths of the negative pulse 20 and the negative pulse 21 of P1 are both smaller than T2, so that the negative pulse 20 and the negative pulse 21 have no effect on a4, and a4 maintains a low state. The widths of the negative pulse 23, the negative pulse 24, the negative pulse 25 and the negative pulse 26 are all smaller than T2, the potential of A2 cannot reach or be higher than the upper limit threshold voltage of the Schmitt circuit F21 through charging, and the state of A4 is not influenced; the negative pulse 27 of P1 has a width greater than T2, and therefore a4 changes from high to low after the falling edge of the negative pulse 27 of P1 for a time T2. At the rising edge of the negative pulse 27 of P1, a4 changes from low to high.
The output A3 of the schmitt circuit F11 remains low when the input pulse P1 is low, and becomes high after a time T1 after the input pulse P1 changes from low to high. The output a4 of the schmitt circuit F21 remains high when the input pulse P1 is high, and becomes low after the input pulse P1 changes from high to low for a time T2. Alternatively, when A3 is high, a4 must be high; when a4 is low, A3 is necessarily low.
In fig. 10, the initial states of A3 and a4 are both low, the output Y of the data selector T11 is low, and the data selector T11 selects A3 as the output Y and maintains it while A3 is low. When A3 changes from low to high at edge 30, output Y changes to high, and data selector T11 selects a4 as output Y, at which time a4 is necessarily high, maintaining the high state of output Y. When a4 changes from high to low at edge 31, the output Y changes to low, and the data selector T11 selects A3 as the output Y, at which time A3 is necessarily low, maintaining the low state of the output Y. When A3 changes from low to high on edge 32, output Y changes to high, and data selector T11 selects a4 as output Y, at which time a4 is necessarily high, maintaining the high state of output Y.
The pulse interference filtering unit filters out narrow pulses 11, 12, 13, 23, 24, 25 and 26 in the P1 signal, while positive wide pulses 14 (including positive pulses 14, 15, 16, 17 and 18, negative pulses 23, 24, 25 and 26 are interference pulses) and negative wide pulses 27 enable corresponding positive wide pulses 28 and negative wide pulses 29 to appear in the P2 signal. The output pulse P2 is in phase with the input pulse P1, and the rising edge of the output wide pulse 28 lags behind the rising edge of the input positive wide pulse 14 by a time T1 and the falling edge lags by a time T2.
The positive pulse 11, the positive pulse 12 and the positive pulse 13 are positive narrow pulses, wherein the positive pulse 11 is an interference pulse, and the positive pulse 12 and the positive pulse 13 are continuous shaking pulses. Time T1 is the maximum positive narrow pulse width that the pulse interference rejection unit can filter. T1 is the forward charging time. T1 is affected by the magnitude of the drive current flowing out of the current driver U11, the low level potential of the current driver U11, the magnitude of the capacitor C11, and the upper threshold voltage of the schmitt circuit F11. In general, adjusting the value of T1 can be done by varying the magnitude of the outgoing drive current of current driver U11 and the magnitude of capacitor C11.
In fig. 9, the end of the capacitor C11 connected to the common ground may be connected to the power supply terminal of the glitch filtering unit; similarly, the end of the capacitor C21 connected to the common ground can be connected to the power supply terminal of the glitch filtering unit alone or together with the capacitor C11.
In fig. 9, the schmitt circuit F11 and the schmitt circuit F21 may also simultaneously or individually select an inverted schmitt circuit, and the inputs D1 and D2 and the output Y of the data selector T11 may also simultaneously or individually have an inverted correlation. When the schmitt circuit F11 and the schmitt circuit F21 simultaneously or individually select the inverse schmitt circuit, and the inputs D1 and D2 and the output Y of the data selector T11 simultaneously or individually have the inverse phase relationship, the following conditions need to be satisfied, that is: when the Y output by the data selector T11 is in-phase relation with the input signal of the Schmitt circuit F11 forward charging and discharging circuit, the Y output by the data selector T11 is in anti-correlation with the input signal of the Schmitt circuit F21; at this time, the output of the Y low-level control selection schmitt circuit F11 is supplied to the output terminal of the data selector T11, and the output of the Y high-level control selection schmitt circuit F21 is supplied to the output terminal of the data selector T11. When the Y output by the data selector T11 is in an inverse correlation with the input signal of the Schmitt circuit F11, the Y output by the data selector T11 is in an in-phase relationship with the input signal of the Schmitt circuit F21; at this time, the output of the Y low-level control selection schmitt circuit F21 is supplied to the output terminal of the data selector T11, and the output of the Y high-level control selection schmitt circuit F11 is supplied to the output terminal of the data selector T11.
Fig. 11 shows a forward current driver and a reverse current driver circuit of embodiment 1. The open-drain output in-phase driver F12 and the resistor R11 form a forward current driver. When P1 is low, the in-phase driver F12 outputs a1 that is low; when P1 is high, the in-phase driver F12 is an open-drain output, and power + VCC flows a driving current through the resistor R11.
The open-drain output inverting driver F22 and the resistor R21 form an inverting current driver. When P1 is high, the output a2 of inverting driver F22 is low; when P1 is low, inverting driver F22 is an open-drain output, and power + VCC flows the driving current through resistor R21.
The non-inverting driver F12 and the inverting driver F22 can be selected from various open collector and open drain integrated circuits.
Fig. 12 shows a forward current driver and a reverse current driver circuit of embodiment 2. The triode V21, the resistor R22 and the resistor R23 form a reverse current driver, when the P1 is at a high level, the triode V21 is in saturated conduction, and the output A2 of the reverse current driver is at a low level; when P1 is low, transistor V21 is turned off, and power + VCC draws driving current through resistor R22.
A forward current driver is composed of the triode V11, the triode V12, the resistor R12, the resistor R13 and the resistor R14, when the P1 is at a low level, the triode V12 is cut off, the triode V11 is in saturated conduction, and the output A1 of the forward current driver is at a low level; when P1 is at a high level, transistor V12 is in saturation conduction, transistor V11 is turned off, and power + VCC flows out a driving current through resistor R12. The inverting circuit formed by the transistor V12 and the resistor R14 in fig. 12 can be replaced by another inverter.
In fig. 12, the forward current driver and the reverse current driver do not provide the outgoing drive current with a constant magnitude.
Fig. 13 shows a forward current driver and a reverse current driver embodiment 3 circuit. The triode V25, the triode V26, the voltage regulator tube D25, the resistor R25 and the resistor R26 form a reverse current driver, wherein the triode V26, the voltage regulator tube D25 and the resistor R25 form a reverse constant current circuit. When the P1 is at a high level, the triode V25 is in saturation conduction, and the reverse current driver output a2 is at a low level; when P1 is low, transistor V25 is turned off, and power supply + VCC draws a constant current drive current through transistor V26.
The triode V15, the triode V16, the triode V17, the voltage regulator tube D15, the resistor R15, the resistor R16 and the resistor R17 form a forward current driver, wherein the triode V16, the voltage regulator tube D15 and the resistor R15 form a forward constant current circuit. When the P1 is at a low level, the transistor V17 is turned off, the transistor V15 is turned on in saturation, and the forward current driver output a1 is at a low level; when the P1 is at a high level, the transistor V17 is in saturation conduction, the transistor V15 is cut off, and the power supply + VCC flows out a constant current driving current through the transistor V16. The inverting circuit formed by the transistor V17 and the resistor R17 in fig. 13 can be replaced by another inverter.
FIG. 14 illustrates an embodiment of a counter module, a comparison module, and a clear signal generation module. In fig. 14, F81 and F82 are both 4-bit binary synchronous up-down counters 74HC193, which together constitute a counter module. In F81 and F82, the CPU is an up-count input terminal, the CPD is a down-count input terminal, the TCU is an up-pulse output terminal, the TCD is a down-pulse output terminal, the CR is a high-level effective zero-clearing input terminal, the LD is a low-level effective data preset control input terminal, the D3, D2, D1 and D0 are preset data input terminals, and the Q3, Q2, Q1 and Q0 are count output terminals. TCU and TCD of F81 are respectively connected to CPU and CPD of F82, F81 and F82 jointly form an 8-bit binary synchronous reversible counter in a cascade mode, the counting range reaches 255 to the maximum, wherein counting outputs Q3, Q2, Q1 and Q0 of F81 are the lower 4 bits of 8-bit counting output, counting outputs Q3, Q2, Q1 and Q0 of F82 are the upper 4 bits of 8-bit counting output, and the counting outputs Q3, Q2, Q1 and Q0 jointly form the output Q of the counter module 502 in the embodiment of FIG. 3. The LD terminals of F81 and F82 are both directly inputted with high level, that is, the LDs are all in an inactive state, at this time, D3, D2, D1, and D0 of F81 and F82 can be connected with any level, and in the embodiment of fig. 14, D3, D2, D1, and D0 of F81 and F82 are all connected with low level. The CPU and CPD of F81 are respectively CP + and CP-signal terminals of the counter module. The CR ends of F81 and F82 are connected together to form a zero clearing input end R of the counter module.
In fig. 14, F83 and F84 are both 4-bit binary comparators 74HC85, which together constitute a comparison module. In F83 and F84, a3, a2, a1 and a0 are input of a 4-bit binary comparison number A, and B3, B2, B1 and B0 are input of a 4-bit binary comparison number B; y isA<B、YA＝B、YA>BIs output as a result of the comparison of A, B, IA<B、IA＝B、IA>BThe low-order comparison result is input in cascade connection. In fig. 14, output Y of F83A<B、YA＝B、YA>BAre respectively connected to corresponding input ends I of F84A<B、 IA＝B、IA>BForming an 8-bit binary comparator, wherein F83 is a low 4 bit, and F84 is a high 4 bit; the comparator A input terminals a3, a2, a1 and a0 of F83 and F84 jointly form the input data DA of the comparison module 503 in FIG. 3, and are connected to the 8-bit binary output of the counter module; the inputs B3, B2, B1, B0 of the comparators 83, F84 collectively form the input data DB of the comparator module 503 in fig. 3, the input data X, in fig. 14, the 8-bit binary data X is equal to 1; output Y of F84A>BA track block interval occupation signal J1 output by the comparison module. When the output of the counter module is greater than X, the track block interval occupation signal J1 output by the comparison module is effective, and the effective state of J1 is high level; when the output of the counter module is less than or equal to X, the track block occupation signal J1 output by the comparison module is invalid, and the invalid state of J1 is low level.
In fig. 14, a not gate F85, a resistor R81, a resistor R82, a capacitor C81, a capacitor C82, a diode D81, and a diode D82 form a clear signal generation module, and the not gate F85 selects the inverter 74HC 06. The not gate F85 may also select the CMOS schmitt inverter 74HC 14. A resistor R81, a capacitor C81 and a diode D81 form a falling edge delay circuit, the falling edge of the input of the NOT gate F85 is delayed from J1, and the delay time is determined by the product of a resistor R81 and a capacitor C81; the resistor R82, the capacitor C82 and the diode D82 form a differential circuit, and the rising edge output by the NOT gate F85 is converted into a positive pulse; the not gate F85 performs shaping and phase conversion functions. When the track blocking interval occupation signal J1 changes from active to inactive, i.e., after the falling edge of J1, the clear signal generation module in fig. 14 delays to generate a positive clear pulse at J2, so that the outputs of F81 and F82 in the counter module become 0.
The forward anti-interference Schmitt circuit and the reverse anti-interference Schmitt circuit are both Schmitt circuits, and the input signal is voltage on a capacitor, so that the Schmitt circuit is required to have high input impedance characteristic. The schmitt circuit can select CMOS schmitt inverters CD40106, 74HC14 with high input impedance characteristics, or select CMOS schmitt nand gates CD4093, 74HC24 with high input impedance characteristics. The upper threshold voltage of a CMOS schmitt inverter or CMOS schmitt nand gate is a fixed value associated with the device. A Schmitt inverter or a Schmitt NAND gate is used for forming the same-phase Schmitt circuit, and a stage of inverter is required to be added behind the Schmitt inverter or the Schmitt NAND gate.
Fig. 15 shows an embodiment of a schmitt circuit having a high input impedance characteristic, in which fig. 15(a) is an in-phase schmitt circuit and fig. 15(b) is a reverse-phase schmitt circuit. F91, F93 select the CMOS schmitt inverter 74HC14 having a high input impedance characteristic, and F92 select the inverter 74HC 06.
The Schmitt circuit can be formed by an operational amplifier, and the upper limit threshold voltage and the lower limit threshold voltage can be flexibly changed by forming the Schmitt circuit by the operational amplifier. Similarly, when the schmitt circuit is configured by using an operational amplifier, it is necessary to use a structure and a circuit having high input impedance characteristics.
The data selector may be an alternative data selector formed by devices such as 74HC151, 74HC152, 74HC153, CD4512, and CD4539, or may be a gate circuit.
The Schmitt circuit and the data selector can also adopt a CPLD and an FPGA together with the axle counting and branching unit to realize the functions.
Claims (7)
1. A track axle counting type circuit shunting system is characterized in that:
the system comprises a first wheel sensor, a second wheel sensor, a third wheel sensor, a fourth wheel sensor and an axle counting and shunting unit;
the first wheel sensor, the second wheel sensor, the third wheel sensor and the fourth wheel sensor respectively output a first axle counting pulse signal, a second axle counting pulse signal, a third axle counting pulse signal and a fourth axle counting pulse signal;
the first axle counting pulse signal, the second axle counting pulse signal, the third axle counting pulse signal and the fourth axle counting pulse signal are sent to an axle counting shunt unit, and the axle counting shunt unit outputs a track block interval occupation signal;
the system also comprises a first pulse interference filtering unit, a second pulse interference filtering unit, a third pulse interference filtering unit and a fourth pulse interference filtering unit;
the first axle counting pulse signal, the second axle counting pulse signal, the third axle counting pulse signal and the fourth axle counting pulse signal are respectively transmitted to the axle counting shunt unit after being filtered by a first pulse interference filtering unit, a second pulse interference filtering unit, a third pulse interference filtering unit and a fourth pulse interference filtering unit to filter interference waveforms;
the first pulse interference filtering unit, the second pulse interference filtering unit, the third pulse interference filtering unit and the fourth pulse interference filtering unit are pulse interference filtering units with the same structural parameters;
the pulse interference filtering unit comprises a forward charging and discharging circuit, a reverse charging and discharging circuit and a data selector;
the input signals of the forward charge-discharge circuit and the reverse charge-discharge circuit are input pulses of the pulse interference filtering unit;
the data selector is an alternative data selector; two data input ends of the data selector are respectively connected to the output ends of the forward charge-discharge circuit and the reverse charge-discharge circuit;
the data output end of the data selector is an output pulse end of the pulse interference filtering unit; the data selector performs data selection control by the output pulse;
the forward charge-discharge circuit comprises a forward current driver, a forward anti-interference capacitor and a forward anti-interference Schmitt circuit; the input end of the forward current driver is the input end of a forward charging and discharging circuit, and the output of the forward current driver is connected to the input end of a forward anti-interference Schmitt circuit; one end of the forward anti-interference capacitor is connected to the input end of the forward anti-interference Schmitt circuit, and the other end of the forward anti-interference capacitor is connected to the public ground of the pulse interference filtering unit or a power supply;
the reverse charging and discharging circuit comprises a reverse current driver, a reverse anti-interference capacitor and a reverse anti-interference Schmitt circuit; the input end of the reverse current driver is the input end of the reverse charge-discharge circuit, and the output end of the reverse current driver is connected to the input end of the reverse anti-interference Schmitt circuit; one end of the reverse anti-interference capacitor is connected to the input end of the reverse anti-interference Schmitt circuit, and the other end of the reverse anti-interference capacitor is connected to the public ground or the power supply of the pulse interference filtering unit;
the output end of the forward anti-interference Schmitt circuit is the output end of the forward charging and discharging circuit, and the output end of the reverse anti-interference Schmitt circuit is the output end of the reverse charging and discharging circuit.
2. The track counting axial circuit shunt system according to claim 1, wherein:
the axle counting and shunting unit comprises a counting pulse generating module, a counter module, a comparison module and a zero clearing signal generating module;
the function of the counting pulse generation module is as follows: when the first axle counting pulse signal and the second axle counting pulse signal meet the entering logic state of the axle, or the third axle counting pulse signal and the fourth axle counting pulse signal meet the entering logic state of the axle, the counting pulse output end outputs a counting pulse; when the first axle counting pulse signal and the second axle counting pulse signal meet the outgoing logic state of the axle, or the third axle counting pulse signal and the fourth axle counting pulse signal meet the outgoing logic state of the axle, the countdown pulse output end outputs a countdown pulse;
the counter module functions to: the counting pulse generating module outputs an up-counting pulse and the output thereof increases 1, and the counting pulse generating module outputs a down-counting pulse and the output thereof decreases 1;
the function of the comparison module is: when the output of the counter module is greater than X, the output track block interval occupation signal is valid, otherwise, the output track block interval occupation signal is invalid; x is an integer greater than or equal to 1;
the function of the zero clearing signal generation module is as follows: when the track block interval occupation signal is changed from effective to ineffective, a zero clearing pulse is generated in a delayed mode to enable the output of the counter module to be 0.
3. The track counting axial circuit shunt system according to claim 2, wherein: when the input of the forward current driver is at a high level, the output end of the forward current driver is driven by current and outputs driving current; when the input of the forward current driver is at a low level, the output end is driven by voltage and outputs a low level; when the input of the reverse current driver is at a low level, the output end of the reverse current driver is driven by current and outputs driving current; when the input of the reverse current driver is at a high level, the output end is driven by voltage and outputs a low level.
4. The track counting axial circuit shunt system according to claim 3, wherein: when the input of the forward current driver is at a high level, the output end of the forward current driver is driven by current and outputs constant current driving current; when the input of the reverse current driver is at a low level, the output end of the reverse current driver is driven by current and outputs constant current driving current.
5. The track counting axial circuit shunt system according to claim 3, wherein: when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in the same phase relation, the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an anti-correlation system; when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in an anti-correlation system, the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an in-phase relationship.
6. The track counting axial circuit shunt system according to claim 5, wherein: the specific method that the data selector carries out data selection control by the output pulse is that when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in an in-phase relation and the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an anti-correlation relation, the low-level control data selector of the output pulse selects the output signal of the forward anti-interference Schmitt circuit to be sent to the output end of the data selector, and the high-level control data selector selects the output signal of the reverse anti-interference Schmitt circuit to be sent to the output end of the data selector; when the output signal of the data selector and the input signal of the forward anti-interference Schmitt circuit are in an anti-correlation system and the output signal of the data selector and the input signal of the reverse anti-interference Schmitt circuit are in an in-phase relationship, the low-level control data selector of the output pulse selects the output signal of the reverse anti-interference Schmitt circuit to be sent to the output end of the data selector, and the high-level control data selector selects the output signal of the forward anti-interference Schmitt circuit to be sent to the output end of the data selector.
7. The track counting axial circuit shunt system according to any one of claims 1 or 3 to 6, wherein: the positive narrow pulse width that the pulse interference filtering unit can filter controls through the size that changes the outflow drive current size of forward current driver or the size of forward anti-interference electric capacity, and the negative narrow pulse width that can filter controls through the size that changes the outflow drive current size of reverse current driver or the size of reverse anti-interference electric capacity.
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| CN201610421440.3A CN105966421A (en) | 2016-06-15 | 2016-06-15 | Rail axle counting type circuit shunting system |
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| CN201362265Y (en) * | 2009-03-09 | 2009-12-16 | 河南蓝信科技有限公司 | Train FBG axle counting system |
| CN101934746A (en) * | 2010-09-29 | 2011-01-05 | 许继集团有限公司 | Automatic neutral-section passing device for electric locomotive |
| CN102285362A (en) * | 2011-06-16 | 2011-12-21 | 王国润 | Wheel detecting device with two axle counters and axle count calculating method thereof |
| CN102582659B (en) * | 2012-01-19 | 2016-05-04 | 中国神华能源股份有限公司 | Wheel takies judgment means and determination methods to counting device, track section |
| CN104316858B (en) * | 2014-11-04 | 2017-04-05 | 北京金自天正智能控制股份有限公司 | A kind of AC-AC frequency converter turn on thyristors state monitoring apparatus |
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