CN106740986B - Rail type track circuit shunting system - Google Patents
Rail type track circuit shunting system Download PDFInfo
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- CN106740986B CN106740986B CN201611009703.6A CN201611009703A CN106740986B CN 106740986 B CN106740986 B CN 106740986B CN 201611009703 A CN201611009703 A CN 201611009703A CN 106740986 B CN106740986 B CN 106740986B
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B61—RAILWAYS
- B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
- B61L1/00—Devices along the route controlled by interaction with the vehicle or vehicle train, e.g. pedals
- B61L1/16—Devices for counting axles; Devices for counting vehicles
- B61L1/163—Detection devices
- B61L1/165—Electrical
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- B—PERFORMING OPERATIONS; TRANSPORTING
- B61—RAILWAYS
- B61L—GUIDING RAILWAY TRAFFIC; ENSURING THE SAFETY OF RAILWAY TRAFFIC
- B61L1/00—Devices along the route controlled by interaction with the vehicle or vehicle train, e.g. pedals
- B61L1/16—Devices for counting axles; Devices for counting vehicles
- B61L1/161—Devices for counting axles; Devices for counting vehicles characterised by the counting methods
Abstract
A steel rail type track circuit shunting system is characterized in that four axle counting pulse signals generated by wheel sensors arranged at two ends of a track block section are used, each axle counting pulse signal is used for detecting a wheel by two wheel sensors arranged on a left track and a right track, and the output axle counting pulse signals are enabled to be effective only when the two wheel sensors arranged on the left track and the right track simultaneously detect the wheels and output effective signals. The system automatically judges the four-way axle counting pulse signals, counts the axles entering and exiting the blocked track section, and automatically invalidates the occupied track section signals when the quantity of the axles entering and exiting the blocked track section is the same. The pulse interference elimination unit filters narrow pulse interference and jitter interference of signal edges of the axle counting pulse signals, and the anti-interference capability is further improved. The system is used to replace existing track shunt circuits.
Description
Technical Field
The invention relates to a rail transit track circuit, in particular to a steel rail type track circuit shunting system.
Background
The track circuit is badly shunted due to the influence of bad conducting objects on the track surface of the track circuit, and the track relay for controlling the track section can not normally act when a train or a locomotive occupies the track, so that the signal interlocking fails. When the axle counting sensor scheme is adopted, the mechanical sensor generates a signal when a train arrives by controlling the on-off of an electrode contact through a spring, and poor contact of a contact point and signal jitter interference are easily generated; the infrared ray of the infrared sensor is easily shielded by dust and sundries and is easily interfered by other illumination to generate interference pulses; the ultrasonic piezoelectric transducer cannot be effectively protected because the ultrasonic piezoelectric transducer is exposed outside, and is also easily influenced by interference of construction workers and other obstacles to generate interference pulses; the eddy current coil induction and the magnetic head sensor induction are easily affected by metal impurities, for example, when a railway constructor holds a shovel to slide over the magnetic head sensor, the magnetic head is easily interfered to judge, and an interference pulse is output. When a wheel enters or exits a detection interval, the various sensors also cause the edges of sensing signals to generate shaking pulses due to sensor vibration caused by the passing of a vehicle, self vibration of the wheel, shaking of contacts of the sensors and the like.
Disclosure of Invention
In order to solve the problem of poor shunting of the existing track circuit, the invention provides a steel rail type track circuit shunting system which comprises a left wheel sensor, a right wheel sensor, a left second wheel sensor, a right second wheel sensor, a left third wheel sensor, a right third wheel sensor, a left fourth wheel sensor, a right fourth wheel sensor, a first axle counting pulse unit and a second axle counting pulse unit, wherein the left wheel sensor is connected with the right wheel sensor; a third axle-counting pulse unit, a fourth axle-counting pulse unit and an axle-counting branching unit.
The left wheel sensor, the right wheel sensor, the left two wheel sensor, the right two wheel sensor, the left three wheel sensor, the right three wheel sensor, the left four wheel sensor and the right four wheel sensor respectively output a left wheel sensing signal, a right wheel sensing signal, a left two wheel sensing signal, a right two wheel sensing signal, a left three wheel sensing signal, a right three wheel sensing signal, a left four wheel sensing signal and a right four wheel sensing signal.
The left wheel sensing signal and the right wheel sensing signal are sent to the first axle counting pulse unit, the left second wheel sensing signal and the right second wheel sensing signal are sent to the second axle counting pulse unit, the left third wheel sensing signal and the right third wheel sensing signal are sent to the third axle counting pulse unit, and the left fourth wheel sensing signal and the right fourth wheel sensing signal are sent to the fourth axle counting pulse unit.
The first axle counting pulse unit has the functions of: only when the left wheel sensing signal and the right wheel sensing signal are effective, the output first axle counting pulse signal is effective; the second axle counting pulse unit has the functions of: only when the left second wheel sensing signal and the right second wheel sensing signal are effective, the output second axle counting pulse signal is effective; the third axis pulse unit has the functions of: only when the left three-wheel sensing signal and the right three-wheel sensing signal are effective, the output third axle pulse signal is effective; the fourth axle counting pulse unit has the functions of: and only when the left four wheel sensing signals and the right four wheel sensing signals are effective, the fourth axle counting pulse signals output by the four wheel sensing signals are effective.
And the first axle counting pulse signal, the second axle counting pulse signal, the third axle counting pulse signal and the fourth axle counting pulse signal are sent to an axle counting shunt unit, and the axle counting shunt unit outputs a track block interval occupation signal.
The left wheel sensor is arranged on the outer side or the inner side of the left track, and the right wheel sensor is arranged on the outer side or the inner side of the right track and is positioned on the same axle line; the left two-wheel sensor is arranged on the outer side or the inner side of the left track, and the right two-wheel sensor is arranged on the outer side or the inner side of the right track and is positioned on the same axle line; the left three-wheel sensor is arranged on the outer side or the inner side of the left track, and the right three-wheel sensor is arranged on the outer side or the inner side of the right track and is positioned on the same axle line; the four left wheel sensors are arranged on the outer side or the inner side of the left track, and the four right wheel sensors are arranged on the outer side or the inner side of the right track and are positioned on the same axle line.
The axle counting and shunting unit comprises a counting pulse generation module, a counter module and a judgment module.
The function of the counting pulse generation module is as follows: when the first axle counting pulse signal and the second axle counting pulse signal meet the entering logic state of the axle, or the third axle counting pulse signal and the fourth axle counting pulse signal meet the entering logic state of the axle, outputting an addition counting pulse; when the first axle counting pulse signal and the second axle counting pulse signal meet the output logic state of the axle, or the third axle counting pulse signal and the fourth axle counting pulse signal meet the output logic state of the axle, a countdown pulse is output.
The counter module functions to: the counting pulse generating module outputs an up counting pulse and the output thereof increases by 1, and the counting pulse generating module outputs a down counting pulse and the output thereof decreases by 1.
The function of the discrimination module is as follows: and when the output of the counter module is not equal to 0, the output track blocking interval occupation signal is valid, otherwise, the output track blocking interval occupation signal is invalid.
The steel rail type track circuit shunt system further comprises a first pulse interference filtering unit, a second pulse interference filtering unit, a third pulse interference filtering unit and a fourth pulse interference filtering unit.
The first axle counting pulse signal, the second axle counting pulse signal, the third axle counting pulse signal and the fourth axle counting pulse signal are respectively transmitted to the axle counting shunt unit after being filtered by the first pulse interference filtering unit, the second pulse interference filtering unit, the third pulse interference filtering unit and the fourth pulse interference filtering unit to filter interference waveforms.
The first pulse interference filtering unit, the second pulse interference filtering unit, the third pulse interference filtering unit and the fourth pulse interference filtering unit are pulse interference filtering units with the same structural parameters.
The pulse interference filtering unit comprises a forward anti-interference circuit, a reverse anti-interference circuit and a data selector; the input signals of the forward anti-jamming circuit and the reverse anti-jamming circuit are input pulses of a pulse interference filtering unit; the data selector is an alternative data selector; two data input ends of the data selector are respectively connected to the output ends of the forward anti-jamming circuit and the reverse anti-jamming circuit; the output signal of the data selector is the output pulse of the pulse interference filtering unit; the data selector performs data selection control by the output pulse.
The forward anti-interference circuit comprises a fast discharge diode, a charging resistor, a forward anti-interference capacitor and a forward anti-interference Schmitt circuit; the cathode of the rapid discharge diode is the input end of the forward anti-interference circuit, and the anode of the rapid discharge diode is connected to the input end of the forward anti-interference Schmitt circuit; the charging resistor is connected with the quick discharging diode in parallel; one end of the forward anti-interference capacitor is connected to the input end of the forward anti-interference Schmitt circuit, and the other end of the forward anti-interference capacitor is connected to the public ground of the pulse interference filtering unit or a power supply.
The reverse anti-interference circuit comprises a quick charging diode, a discharging resistor, a reverse anti-interference capacitor and a reverse anti-interference Schmitt circuit; the anode of the rapid charging diode is the input end of the reverse anti-interference circuit, and the cathode of the rapid charging diode is connected to the input end of the reverse anti-interference Schmitt circuit; the discharge resistor is connected with the quick charge diode in parallel; one end of the reverse anti-interference capacitor is connected to the input end of the reverse anti-interference Schmitt circuit, and the other end of the reverse anti-interference capacitor is connected to the public ground of the pulse interference filtering unit or a power supply.
The output end of the forward anti-interference Schmitt circuit is the output end of the forward anti-interference circuit, and the output end of the reverse anti-interference Schmitt circuit is the output end of the reverse anti-interference circuit.
When the output signal of the data selector and the input signal of the forward anti-interference circuit are in-phase relation, the output signal of the data selector and the input signal of the reverse anti-interference circuit are also in-phase relation; when the output signal of the data selector and the input signal of the forward anti-jamming circuit are in an inverse correlation system, the output signal of the data selector and the input signal of the reverse anti-jamming circuit are also in an inverse correlation system.
The specific method that the data selector carries out data selection control by the output pulse is that when the output signal of the data selector and the input signal of the forward anti-interference circuit are in-phase relation and the output signal of the data selector and the input signal of the reverse anti-interference circuit are in-phase relation, the low level of the output pulse controls the data selector to select the output signal of the forward anti-interference circuit to be sent to the output end of the data selector, and the high level controls the data selector to select the output signal of the reverse anti-interference circuit to be sent to the output end of the data selector; when the output signal of the data selector and the input signal of the forward anti-jamming circuit are in an inverse correlation system, and the output signal of the data selector and the input signal of the reverse anti-jamming circuit are in an inverse correlation system, the low level of the output pulse controls the data selector to select the output signal of the reverse anti-jamming circuit to be sent to the output end of the data selector, and the high level controls the data selector to select the output signal of the forward anti-jamming circuit to be sent to the output end of the data selector.
The positive narrow pulse width that the pulse interference filtering unit can filter is controlled by changing the charging time constant, and the negative narrow pulse width that can filter is controlled by changing the discharging time constant.
The charging time constant is the product of a charging resistor and a forward anti-interference capacitor; and the discharge time constant is the product of a discharge resistor and the reverse anti-interference capacitor.
The invention has the beneficial effects that: the system simultaneously detects wheels on the same axle by the left sensor and the right sensor, and only when the left sensor and the right sensor are simultaneously effective, the system outputs an effective axle counting pulse signal, so that various interference signals output by a single sensor can be effectively eliminated; the system automatically judges the 4-path axle counting pulse signals, counts axles entering and exiting the track block section, and automatically invalidates the track block section occupation signals when the quantity of the axles entering and exiting the track block section is the same; the axle counting pulse signal is filtered by the pulse interference filtering unit to remove narrow pulse interference and jitter interference on the signal edge, the anti-interference capability of the system is further improved, and the maximum width of the narrow pulse filtered by the pulse interference filtering unit can be adjusted by changing the charging time constant and the discharging time constant.
Drawings
FIG. 1 is an embodiment of a wheel sensor mounting location;
FIG. 2 is a block diagram of an embodiment of a steel rail track circuit shunting system;
FIG. 3 is a block diagram of an embodiment of an axle counting and branching unit;
FIG. 4 is an exemplary waveform of the first axle counting pulse signal and the second axle counting pulse signal satisfying the entry logic state of the axle;
FIG. 5 is an exemplary waveform of the first axle counting pulse signal and the second axle counting pulse signal satisfying the exit logic state of the axle;
fig. 6 is an example waveform in which the third axle counting pulse signal and the fourth axle counting pulse signal satisfy the exit logic state of the axle;
FIG. 7 is an exemplary waveform of the entry logic state where the third axle counting pulse signal and the fourth axle counting pulse signal satisfy the axle;
FIG. 8 is an embodiment of an up-count pulse or down-count pulse generation circuit;
FIG. 9 shows an embodiment of an interference rejection unit;
FIG. 10 is a waveform of an embodiment of an impulse interference rejection unit;
FIG. 11 is an embodiment of a counter module and a discrimination module;
fig. 12 is an embodiment of a schmitt circuit having a high input impedance characteristic.
Detailed Description
The invention is further described below with reference to the accompanying drawings.
Fig. 1 shows an embodiment of a wheel sensor mounting position. The left wheel sensor 201 and the right wheel sensor 202 are respectively installed on the inner sides of the left track 101 and the right track 102 and are on the same vehicle axis B1. During the running of the locomotive and the train, when the wheel axle runs to the position of the train axis B1, the left wheel sensor 201 and the right wheel sensor 202 respectively sense the left wheel and the right wheel and simultaneously output effective signals. The left wheel sensor 201 and the right wheel sensor 202 need to be installed on the outer side or the inner side of the left track and the right track respectively, and can be installed on the outer side or the inner side of the track simultaneously or respectively, but must be on the same axle line, that is, the left wheel sensor 201 and the right wheel sensor 202 need to sense the left wheel and the right wheel on the same axle simultaneously.
The left wheel sensor 203 and the right wheel sensor 204 are respectively installed on the inner sides of the left rail 101 and the right rail 102 and are on the same vehicle axis B2. During the running of the locomotive and the train, when the wheel axle runs to the position of the train axis B2, the left wheel sensor 203 and the right wheel sensor 204 respectively sense the left wheel and the right wheel and simultaneously output effective signals. The left wheel sensor 203 and the right wheel sensor 204 need to be installed on the outer side or the inner side of the left track and the right track respectively, and can be installed on the outer side or the inner side of the track simultaneously or respectively, but must be on the same axle line, that is, the left wheel sensor 203 and the right wheel sensor 204 need to sense the left wheel and the right wheel on the same axle simultaneously.
The left three-wheel sensor 205 and the right three-wheel sensor 206 are respectively mounted on the inner sides of the left rail 101 and the right rail 102 and are located on the same vehicle axis B3. During the running of the locomotive and the train, when the wheel axle runs to the position of the train axis B3, the left three-wheel sensor 205 and the right three-wheel sensor 206 respectively sense the left wheel and the right wheel and simultaneously output effective signals. The left three-wheel sensor 205 and the right three-wheel sensor 206 need to be installed on the outer side or the inner side of the left track and the right track respectively, and can be installed on the outer side or the inner side of the track simultaneously or respectively, but must be on the same axle line, that is, the left three-wheel sensor 205 and the right three-wheel sensor 206 need to sense the left wheel and the right wheel on the same axle simultaneously.
The left four-wheel sensor 207 and the right four-wheel sensor 208 are respectively mounted on the inner sides of the left rail 101 and the right rail 102 and are on the same vehicle axis B4. During the running of the locomotive and the train, when the wheel axle runs to the position of the train axis B4, the left four-wheel sensor 207 and the right four-wheel sensor 208 respectively sense the left wheel and the right wheel and simultaneously output valid signals. The left four-wheel sensor 207 and the right four-wheel sensor 208 need to be installed on the outer side or the inner side of the left track and the right track respectively, and can be installed on the outer side or the inner side of the track simultaneously or respectively, but must be on the same axle line, that is, the left four-wheel sensor 207 and the right four-wheel sensor 208 need to sense the left wheel and the right wheel on the same axle simultaneously.
The wheel sensors may be the same type of sensor or different types of sensors among various axle counting sensors such as a mechanical sensor, an infrared sensor, an ultrasonic piezoelectric transducer, an eddy current coil sensor, and a magnetic head sensor. It is preferable that the same type of sensor be used as the left wheel sensor 201, the right wheel sensor 202, the left two wheel sensor 203, the right wheel sensor 204, the left three wheel sensor 205, the right three wheel sensor 206, the left four wheel sensor 207, and the right four wheel sensor 208 at the same time.
Fig. 2 is a block diagram of an embodiment of a steel rail track circuit shunting system. The left wheel sensor 201, the right wheel sensor 202, the left wheel sensor 203, the right wheel sensor 204, the left wheel sensor 205, the right wheel sensor 206, the left wheel sensor 207, and the right wheel sensor 208 respectively output a left wheel sensing signal Z1, a right wheel sensing signal Y1, a left wheel sensing signal Z2, a right wheel sensing signal Y2, a left wheel sensing signal Z3, a right wheel sensing signal Y3, a left wheel sensing signal Z4, a right wheel sensing signal Y4, Z1, and Y1 to the input of the first axle pulse unit 301, Z2, Y2 to the input of the second axle pulse unit 302, Z3, Y3 to the input of the third axle pulse unit 303, and Z4, Y4 to the input of the fourth axle pulse unit 304.
In the embodiment of the system shown in fig. 2, the first axle counting pulse unit 301, the second axle counting pulse unit 302, the third axle counting pulse unit 303, and the fourth axle counting pulse unit 304 are axle counting pulse units with the same structure and function, and have 2 input terminals I1, I2, and 1 output terminal O1. The function of the axle counting pulse unit is as follows: the output O1 is only active when both the 2 input I1, I2 signals are active. If the input signal is high level effective, namely when a wheel is detected, the output of the wheel sensor is high level, the axle counting pulse unit is an AND gate circuit; if the input signal is active at a low level, i.e. when a wheel is detected, the output of the wheel sensor is at a low level, the axle counting pulse unit is an OR gate circuit. If one of the 2 wheel sensor signals input to the axle counting pulse unit is active at a high level and the other is active at a low level, the 2 wheel sensor signals can be simultaneously active at the high level or simultaneously active at the low level only by adding an inverter to the output end of one of the wheel sensors.
In the embodiment of the system shown in fig. 2, the first axle counting pulse unit 301, the second axle counting pulse unit 302, the third axle counting pulse unit 303, and the first axle counting pulse signal M1, the second axle counting pulse signal M2, the third axle counting pulse signal M3, and the fourth axle counting pulse signal M4 output by the fourth axle counting pulse unit are sent to the axle counting branching unit 500, and the axle counting branching unit 500 outputs the track blocking interval occupation signal J1.
Fig. 3 is a block diagram of an embodiment of the axle counting and splitting unit, which includes a counting pulse generating module 501, a counter module 502, and a determining module 503.
A left wheel sensor 201, a right wheel sensor 202, a left wheel sensor 203 and a right wheel sensor 204 are installed at one end of the track block section for detecting whether the locomotive (train) enters or exits from the end, and a left three-wheel sensor 205, a right three-wheel sensor 206, a left four-wheel sensor 207 and a right four-wheel sensor 208 are installed at the other end of the track block section for detecting whether the locomotive (train) enters or exits from the end.
Fig. 4 shows exemplary waveforms showing that the first axle counting pulse signal and the second axle counting pulse signal satisfy an entry logic state of the axle, and fig. 5 shows exemplary waveforms showing that the first axle counting pulse signal and the second axle counting pulse signal satisfy an exit logic state of the axle.
In the embodiment of fig. 1, when a locomotive (train) enters a track block section from the installation ends of a left wheel sensor 201, a right wheel sensor 202, a left wheel sensor 203 and a right wheel sensor 204, a first axle counting pulse signal M1 is firstly provided, a second axle counting pulse signal M2 is provided later, and the distance between an axle line B1 and an axle line B2 of the installation positions of the wheel sensors is smaller than the wheel diameter of the locomotive (train), so that M2 starts to be effective before an M1 effective signal disappears. The conditions for judging that the first axle counting pulse signal M1 and the second axle counting pulse signal M2 meet the entry logic state of the axle are as follows: while the second axle counting pulse signal M2 is active, the first axle counting pulse signal M1 changes from active to inactive. In fig. 4, in the embodiment, the signals M1 and M2 are both active low, and during the low period of the signal M2, the signal M1 changes from low to high to satisfy the logic state of the axle, the up-count pulse output terminal H1 outputs an up-count pulse, and the down-count pulse output terminal L1 outputs no pulse.
When a locomotive (train) exits a track block section from the mounting ends of the left wheel sensor 201, the right wheel sensor 202, the left wheel sensor 203 and the right wheel sensor 204, the second axle counting pulse signal M2 is firstly sent, the first axle counting pulse signal M1 is sent later, and M1 is started to be effective before the effective signal M2 disappears. The conditions for judging that the first axle counting pulse signal M1 and the second axle counting pulse signal M2 satisfy the driving-out logic state of the axle are as follows: while the first axle counting pulse signal M1 is active, the second axle counting pulse signal M2 changes from active to inactive. In fig. 5, in the embodiment, the signals M1 and M2 are both active low, and during the low period of the signal M1, the signal M2 changes from low to high to satisfy the logic state of the axle, the down-count pulse output terminal L1 outputs a down-count pulse, and the up-count pulse output terminal H1 outputs no pulse.
Fig. 6 shows exemplary waveforms of the third axle counting pulse signal and the fourth axle counting pulse signal satisfying the exit logic state of the axle, and fig. 7 shows exemplary waveforms of the third axle counting pulse signal and the fourth axle counting pulse signal satisfying the entry logic state of the axle.
In the embodiment of fig. 1, when the locomotive (train) exits from the track block section from the mounting ends of the left three-wheel sensor 205, the right three-wheel sensor 206, the left four-wheel sensor 207 and the right four-wheel sensor 208, the third axle pulse signal M3 is firstly present, the fourth axle pulse signal M4 is subsequently present, and the distance between the axle line B3 and the axle line B4 of the mounting positions of the wheel sensors is smaller than the wheel diameter of the locomotive (train), so that the M4 starts to be effective before the M3 effective signals disappear. The conditions for judging that the third axle counting pulse signal M3 and the fourth axle counting pulse signal M4 satisfy the output logic state of the axle are as follows: while the fourth axle pulse signal M4 is active, the third axle pulse signal M3 changes from active to inactive. In fig. 6, in the embodiment, the signals M3 and M4 are both active low, and during the low period of the signal M4, the signal M3 changes from low to high to satisfy the logic state of the axle, the down-count pulse output terminal L1 outputs a down-count pulse, and the up-count pulse output terminal H1 outputs no pulse.
When a locomotive (train) enters a track blocking section from the mounting ends of the left three-wheel sensor 205, the right three-wheel sensor 206, the left four-wheel sensor 207 and the right four-wheel sensor 208, a fourth axle counting pulse signal M4 is firstly sent, a third axle counting pulse signal M3 is sent later, and M3 is started to be effective before an M4 effective signal disappears. The conditions for judging that the third axle counting pulse signal M3 and the fourth axle counting pulse signal M4 satisfy the outgoing logical state of the axle are as follows: while the third axle pulse signal M3 is active, the fourth axle pulse signal M4 changes from active to inactive. In fig. 7, in the embodiment, the signals M3 and M4 are both active low, and during the low period of the signal M3, the signal M4 changes from low to high to satisfy the logic state of the axle, the up-count pulse output terminal H1 outputs an up-count pulse, and the down-count pulse output terminal L1 outputs no pulse.
Fig. 8 shows an up-count pulse or down-count pulse generation circuit embodiment. In fig. 8, the differentiating circuit consisting of C51, R51, and D51 can convert the rising edge in the K2 signal into a positive pulse; inverter F51 converts the negative count pulse signal to a positive count pulse signal. If K1 is M2 and K2 is M1 in fig. 8, the output of the nand gate F52 is the up-counting pulse H11; if K1 is M3 and K2 is M4 in fig. 8, the output of the nand gate F52 is the up-counting pulse H12; the counting pulse H11 and the counting pulse H12 are both negative pulses; in the count pulse generation block 501, when a negative pulse is output from either the count-up pulse H11 or the count-up pulse H12, the count-up pulse H1 outputs a negative pulse.
If K1 is M1 and K2 is M2 in fig. 8, the output of the nand gate F52 is the down-counting pulse L11; if K1 is M4 and K2 is M3 in fig. 8, the output of the nand gate F52 is the down-counting pulse L12; the count-down pulse L11 and the count-down pulse L12 are both negative pulses; in the count pulse generation block 501, when a negative pulse is output in either one of the count-down pulse L11 and the count-down pulse L12, the count-down pulse L1 outputs a negative pulse.
The counter module 502 is an up-down counter, and CP + is an up-counting pulse input terminal and CP-is a down-counting pulse input terminal. The output Q of the counter block 502 is sent to the decision block 503. When the output Q of the counter module 502 is not equal to 0, the output track block section occupation signal J1 is valid, which indicates that there is a locomotive (train) in the track block section; when the J1 is effective, the coil of the track relay is controlled to lose power, a red light circuit is switched on or the annunciator displays dangerous resistance to disable. When the output Q of the counter module 502 is equal to 0, the output track block section occupation signal J1 is invalid, indicating that there is no locomotive (train) in the track block section; when J1 is invalid, the coil of track relay is controlled to be electrified, so that a green light circuit is switched on or the signal machine displays safe traffic. MR is a remote clear input for remote unified clearing of the counter module 502.
The functions of the first axle counting pulse unit, the second axle counting pulse unit, the third axle counting pulse unit, the fourth axle counting pulse unit and the axle counting shunt unit can be realized by various medium-scale logic circuits, and can also be realized by devices such as CPLD, FPGA, PAL, GAL and the like.
Fig. 9 shows an embodiment of the impulse interference filtering unit, which includes a forward interference rejection circuit, a reverse interference rejection circuit, and a data selector. In the embodiment, the fast discharging diode, the charging resistor, the forward anti-interference capacitor and the forward anti-interference Schmitt circuit are respectively a diode D11, a resistor R11, a capacitor C11 and a Schmitt circuit F11, and form a forward anti-interference circuit; the fast charging diode, the discharging resistor, the reverse anti-interference capacitor and the reverse anti-interference Schmitt circuit are respectively a diode D21, a resistor R21, a capacitor C21 and a Schmitt circuit F21, and the reverse anti-interference circuit is formed. One end of the capacitor C11 is connected with the input end of the Schmitt circuit F11, and the other end is connected to the common ground; one end of the capacitor C21 is connected to the input end of the Schmitt circuit F21, and the other end is connected to the common ground. P1 is the input pulse end, P2 is the output pulse end.
In the embodiment of fig. 9, the data selector T11 is an alternative data selector, the two data input signals and the output signal are in-phase, and both the schmitt circuit F11 and the schmitt circuit F21 are in-phase schmitt circuits, so that the output of the data selector T11 and the input of the forward anti-jamming circuit are in-phase, and the output of the data selector T11 and the input of the reverse anti-jamming circuit are in-phase. The function of the data selector T11 is: when the control terminal A is selected to be 0, outputting Y to be D1; when the control terminal a is selected to be 1, the output Y is D2. The output terminal Y (i.e. the pulse output terminal P2) of the data selector T11 is directly connected to the selection control terminal a of the data selector T11, and when the output pulse P2 is low, the data selector T11 is controlled to select the output signal a3 of the schmitt circuit F11 to be sent to the output terminal Y of the data selector; when the output pulse P2 is at a high level, the data selector T11 is controlled to select the output signal a4 of the schmitt circuit F21 to be supplied to the output terminal Y of the data selector.
Fig. 10 shows waveforms of an embodiment of the glitch filtering unit, which includes waveforms of an input pulse P1, an output A3 of the schmitt circuit F11, an output a4 of the schmitt circuit F21, and an output pulse P2. In fig. 9, a diode D11, a resistor R11, and a capacitor C11 form an asymmetric charge/discharge circuit, a schmitt circuit F11 is an in-phase schmitt circuit, and when an input pulse P1 is maintained at a low level for a long time, an output a3 of the schmitt circuit F11 is at a low level; when the input pulse P1 is maintained at the high level for a long time, A3 is at the high level. The P1 signal discharges quickly into the capacitor C11, and when the input pulse P1 changes from high to low, the a1 potential immediately changes to low, and the A3 immediately changes from high to low. The P1 signal charges the capacitor C11 slowly, when the input pulse P1 changes from low level to high level, the A1 potential is charged from the P1 high level signal to the capacitor C11 through the resistor R11 and rises, when the charging time reaches T1, the A1 potential rises to reach and exceed the upper limit threshold voltage of the Schmitt circuit F11, the A3 changes from low level to high level; when the positive pulse width of the P1 is less than T1, the charging time is less than T1, the P1 becomes low level when the potential of the A1 does not reach the upper limit threshold voltage of the Schmitt circuit F11, the potential of the A1 immediately becomes low level potential, and the A3 maintains the low level state. In fig. 10, the initial states of P1 and A3 are low. The widths of the positive narrow pulse 11, the positive narrow pulse 12 and the positive narrow pulse 13 are all smaller than T1, the potential of A1 cannot reach or exceed the upper limit threshold voltage of a Schmitt circuit F11 through charging, and the state of A3 is not influenced; the width of the positive pulse 14 of P1 is greater than T1, so A3 changes from low to high after the rising edge of the positive pulse 14 of P1 by time T1. The falling edge of the positive pulse 14 of P1 changes A3 from high to low, the width of the positive pulse 15 of P1 is greater than T1, and A3 changes from low to high after the rising edge of the positive pulse 15 is over time T1. The falling edge of the positive pulse 15 of P1 changes A3 from high level to low level, and the widths of the positive pulse 16, the positive pulse 17, and the positive pulse 18 of P1 are all smaller than T1, so that the positive pulse 16, the positive pulse 17, and the positive pulse 18 have no effect on A3, and A3 maintains a low level state. The width of the positive pulse 19 of P1 is greater than T1, and A3 goes from low to high after the rising edge of the positive pulse 19 is over a time T1.
In fig. 9, the diode D21, the resistor R21, and the capacitor C21 similarly form an asymmetric charge/discharge circuit, the schmitt circuit F21 is an in-phase schmitt circuit, and when the input pulse P1 is maintained at a low level for a long time, the output a4 of the schmitt circuit F21 is at a low level; when the input pulse P1 is maintained at the high level for a long time, a4 is at the high level. The P1 signal charges the capacitor C21 quickly, and when the input pulse P1 changes from low to high, the a2 potential immediately changes to high and the a4 immediately changes from low to high. The P1 signal discharges slowly to the capacitor C21, when the input pulse P1 changes from high level to low level, the A2 potential discharges to the capacitor C21 through the resistor R21 by the P1 low level signal, when the discharging time reaches T2, the A2 potential drops to be lower than the lower limit threshold voltage of the Schmitt circuit F21, the A4 changes from high level to low level; when the negative pulse width of the P1 is less than T2, the discharge time is less than T2, and the A2 potential does not drop to reach the lower threshold voltage of the Schmitt circuit F21, the P1 becomes high, the A2 potential immediately becomes high, and the A4 maintains high. In fig. 10, the initial states of P1 and a4 are low. The rising edge of the positive pulse 11 of P1 changes a4 from low to high, the negative pulse 20 of P1 has a width greater than T2, and a4 changes from high to low after the falling edge of the negative pulse 20 for a time T2. The rising edge of the positive pulse 12 of P1 changes a4 from low to high, and the widths of the negative pulse 20 and the negative pulse 21 of P1 are both smaller than T2, so that the negative pulse 20 and the negative pulse 21 have no effect on a4, and a4 maintains a low state. The widths of the negative pulse 23, the negative pulse 24, the negative pulse 25 and the negative pulse 26 are all smaller than T2, the potential of A2 can not reach or be lower than the lower limit threshold voltage of the Schmitt circuit F21 through discharging, and the state of A4 is not influenced; the negative pulse 27 of P1 has a width greater than T2, and therefore a4 changes from high to low after the falling edge of the negative pulse 27 of P1 for a time T2. At the rising edge of the negative pulse 27 of P1, a4 changes from low to high.
The output A3 of the schmitt circuit F11 remains low when the input pulse P1 is low, and becomes high after a time T1 after the input pulse P1 changes from low to high. The output a4 of the schmitt circuit F21 remains high when the input pulse P1 is high, and becomes low after the input pulse P1 changes from high to low for a time T2. Alternatively, when A3 is high, a4 must be high; when a4 is low, A3 is necessarily low.
In fig. 10, the initial states of A3 and a4 are both low, the output Y of the data selector T11 is low, and the data selector T11 selects A3 as the output Y and maintains it while A3 is low. When A3 changes from low to high at edge 30, output Y changes to high, and data selector T11 selects a4 as output Y, at which time a4 is necessarily high, maintaining the high state of output Y. When a4 changes from high to low at edge 31, the output Y changes to low, and the data selector T11 selects A3 as the output Y, at which time A3 is necessarily low, maintaining the low state of the output Y. When A3 changes from low to high on edge 32, output Y changes to high, and data selector T11 selects a4 as output Y, at which time a4 is necessarily high, maintaining the high state of output Y.
The pulse interference filtering unit filters out narrow pulses 11, 12, 13, 23, 24, 25 and 26 in the P1 signal, while positive wide pulses 14 (including positive pulses 14, 15, 16, 17 and 18, negative pulses 23, 24, 25 and 26 are interference pulses) and negative wide pulses 27 enable corresponding positive wide pulses 28 and negative wide pulses 29 to appear in the P2 signal. The output pulse P2 is in phase with the input pulse P1, and the rising edge of the output wide pulse 28 lags behind the rising edge of the input positive wide pulse 14 by a time T1 and the falling edge lags by a time T2.
The positive pulse 11, the positive pulse 12 and the positive pulse 13 are positive narrow pulses, wherein the positive pulse 11 is a single interference pulse, and the positive pulse 12 and the positive pulse 13 are continuous shaking pulses. Time T1 is the maximum positive narrow pulse width that the pulse interference rejection unit can filter. T1 is affected by the charging time constant, the high level potential and the low level potential of the input pulse P1, and the upper limit threshold voltage of the schmitt circuit F11. In general, since the high-level potential and the low-level potential of the input pulse P1 are constant values, the value of T1 can be adjusted by changing the charging time constant or the upper-limit threshold voltage of the schmitt circuit F11. In fig. 9, the charging time constant is the product of the charging resistor R11 and the capacitor C11. The pulse interference filtering unit allows positive pulse signals with the width larger than T1 to pass through.
The negative pulse 23, the negative pulse 24, the negative pulse 25 and the negative pulse 26 are negative narrow pulses, wherein the negative pulse 23 is a single interference pulse, and the negative pulse 24, the negative pulse 25 and the negative pulse 26 are continuous shaking pulses. The time T2 is the maximum negative narrow pulse width that the pulse interference filtering unit can filter. T2 is affected by the discharge time constant, the high level potential and the low level potential of the input pulse P1, and the lower limit threshold voltage of the schmitt circuit F21. In general, since the high-level potential and the low-level potential of the input pulse P1 are constant values, the value of T2 can be adjusted by changing the discharge time constant or the lower threshold voltage of the schmitt circuit F21. In fig. 9, the discharge time constant is the product of the discharge resistor R21 and the capacitor C21. The pulse interference filtering unit allows negative pulse signals with the width larger than T2 to pass through.
In fig. 9, the end of the capacitor C11 connected to the common ground may be connected to the power supply terminal of the glitch filtering unit; similarly, the end of the capacitor C21 connected to the common ground can be connected to the power supply terminal of the glitch filtering unit alone or together with the capacitor C11.
In fig. 9, the schmitt circuit F11 and the schmitt circuit F21 may also simultaneously or individually select an inverted schmitt circuit, and the inputs D1 and D2 and the output Y of the data selector T11 may also simultaneously or individually have an inverted correlation. When the schmitt circuit F11 and the schmitt circuit F21 simultaneously or individually select the inverse schmitt circuit, and the inputs D1 and D2 and the output Y of the data selector T11 simultaneously or individually have the inverse phase relationship, the following conditions need to be satisfied, that is: when the output signal Y of the data selector T11 is in-phase relation with the input signal of the forward anti-jamming circuit, the output signal Y of the data selector T11 is also in-phase relation with the input signal of the reverse anti-jamming circuit; the low level of Y controls the output of the select schmitt circuit F11 to be supplied to the output terminal of the data selector T11, and the high level of Y controls the output of the select schmitt circuit F21 to be supplied to the output terminal of the data selector T11. When the output signal Y of the data selector T11 and the input signal of the forward anti-jamming circuit are in an inverse correlation system, the output signal Y of the data selector T11 and the input signal of the reverse anti-jamming circuit are also in an inverse correlation system; the low level of Y controls the output of the select schmitt circuit F21 to be supplied to the output terminal of the data selector T11, and the high level of Y controls the output of the select schmitt circuit F11 to be supplied to the output terminal of the data selector T11.
FIG. 11 illustrates an embodiment of a counter module and a discrimination module. In fig. 11, F81 and F82 are both 4-bit binary synchronous up-down counters 74HC193, which together constitute a counter module. In F81 and F82, the CPU is an up-count input terminal, the CPD is a down-count input terminal, the TCU is an up-pulse output terminal, the TCD is a down-pulse output terminal, the CR is a high-level effective zero-clearing input terminal, the LD is a low-level effective data preset control input terminal, the D3, D2, D1 and D0 are preset data input terminals, and the Q3, Q2, Q1 and Q0 are count output terminals. TCU and TCD of F81 are respectively connected to CPU and CPD of F82, F81 and F82 jointly form an 8-bit binary synchronous reversible counter in a cascade mode, the counting range reaches 255 to the maximum, wherein counting outputs Q3, Q2, Q1 and Q0 of F81 are the lower 4 bits of 8-bit counting output, counting outputs Q3, Q2, Q1 and Q0 of F82 are the upper 4 bits of 8-bit counting output, and the counting outputs Q3, Q2, Q1 and Q0 jointly form the output Q of the counter module 502 in the embodiment of FIG. 3. The LD terminals of F81 and F82 are both directly inputted with high level, that is, the LDs are all in an inactive state, at this time, D3, D2, D1, and D0 of F81 and F82 can be connected with any level, and in the embodiment of fig. 11, D3, D2, D1, and D0 of F81 and F82 are all connected with low level. The CPU and CPD of F81 are respectively CP + and CP-signal terminals of the counter module. The resistor R81 and the capacitor C81 form a power-on reset circuit, the output of the power-on reset circuit is connected to CR ends of F81 and F82 and used for clearing outputs Q3, Q2, Q1 and Q0 of F81 and F82 during power-on; MR is the remote zero clearing input. And + VDD is the power supply of the counter module.
In fig. 11, F83 is an 8-input nor gate, model 74HC4078, and constitutes a determination block. The 8 inputs of F83 are the inputs DA of the decision module 503 in the embodiment of fig. 3, and are connected to the count outputs of F81 and F82. The output of F83 is a track block occupation signal J1. When the count outputs of F81 and F82 are not all 0, the output track-closed section occupation signal J1 is at low level and is in an active state; when the count outputs of F81 and F82 are all 0, the output track-closed section occupation signal J1 is at a high level and is in an inactive state.
The forward anti-interference Schmitt circuit and the reverse anti-interference Schmitt circuit are both Schmitt circuits, and the input signal is voltage on a capacitor, so that the Schmitt circuit is required to have high input impedance characteristic. The schmitt circuit can select CMOS schmitt inverters CD40106, 74HC14 with high input impedance characteristics, or select CMOS schmitt nand gates CD4093, 74HC24 with high input impedance characteristics. The upper threshold voltage and the lower threshold voltage of the CMOS Schmitt inverter or the CMOS Schmitt NAND gate are fixed values related to the device. A Schmitt inverter or a Schmitt NAND gate is used for forming the same-phase Schmitt circuit, and a stage of inverter is required to be added behind the Schmitt inverter or the Schmitt NAND gate.
Fig. 12 shows an embodiment of a schmitt circuit having a high input impedance characteristic, in which fig. 12(a) is an in-phase schmitt circuit and fig. 12(b) is a reverse-phase schmitt circuit. F91, F93 select the CMOS schmitt inverter 74HC14 having a high input impedance characteristic, and F92 select the inverter 74HC 06.
The Schmitt circuit can be formed by an operational amplifier, and the upper limit threshold voltage and the lower limit threshold voltage can be flexibly changed by forming the Schmitt circuit by the operational amplifier. Similarly, when the schmitt circuit is configured by using an operational amplifier, it is necessary to use a structure and a circuit having high input impedance characteristics.
The data selector may be an alternative data selector formed by devices such as 74HC151, 74HC152, 74HC153, CD4512, and CD4539, or may be a gate circuit.
The Schmitt circuit and the data selector can also realize the functions of the Schmitt circuit, the first axle counting pulse unit, the second axle counting pulse unit, the third axle counting pulse unit, the fourth axle counting pulse unit and the axle counting shunt unit by adopting a CPLD and an FPGA.
Claims (7)
1. A rail-mounted track circuit shunting system is characterized in that:
the device comprises a left wheel sensor, a right wheel sensor, a left second wheel sensor, a right second wheel sensor, a left third wheel sensor, a right third wheel sensor, a left fourth wheel sensor, a right fourth wheel sensor, a first axle counting pulse unit and a second axle counting pulse unit; the third axle counting pulse unit, the fourth axle counting pulse unit and the axle counting shunt unit;
the left wheel sensor, the right wheel sensor, the left two wheel sensor, the right two wheel sensor, the left three wheel sensor, the right three wheel sensor, the left four wheel sensor and the right four wheel sensor respectively output a left wheel sensing signal, a right wheel sensing signal, a left two wheel sensing signal, a right two wheel sensing signal, a left three wheel sensing signal, a right three wheel sensing signal, a left four wheel sensing signal and a right four wheel sensing signal;
the left wheel sensing signal and the right wheel sensing signal are sent to a first axle counting pulse unit, the left second wheel sensing signal and the right second wheel sensing signal are sent to a second axle counting pulse unit, the left third wheel sensing signal and the right third wheel sensing signal are sent to a third axle counting pulse unit, and the left fourth wheel sensing signal and the right fourth wheel sensing signal are sent to a fourth axle counting pulse unit;
the first axle counting pulse unit has the functions of: only when the left wheel sensing signal and the right wheel sensing signal are effective, the output first axle counting pulse signal is effective;
the second axle counting pulse unit has the functions of: only when the left second wheel sensing signal and the right second wheel sensing signal are effective, the output second axle counting pulse signal is effective;
the third axis pulse unit has the functions of: only when the left three-wheel sensing signal and the right three-wheel sensing signal are effective, the output third axle pulse signal is effective;
the fourth axle counting pulse unit has the functions of: only when the left four-wheel sensing signal and the right four-wheel sensing signal are effective, the fourth axle counting pulse signal output by the four-wheel sensing signal is effective;
the first axle counting pulse signal, the second axle counting pulse signal, the third axle counting pulse signal and the fourth axle counting pulse signal are sent to an axle counting shunt unit, and the axle counting shunt unit outputs a track block interval occupation signal;
the system also comprises a first pulse interference filtering unit, a second pulse interference filtering unit, a third pulse interference filtering unit and a fourth pulse interference filtering unit;
the first axle counting pulse signal, the second axle counting pulse signal, the third axle counting pulse signal and the fourth axle counting pulse signal are respectively transmitted to the axle counting shunt unit after being filtered by a first pulse interference filtering unit, a second pulse interference filtering unit, a third pulse interference filtering unit and a fourth pulse interference filtering unit to filter interference waveforms;
the first pulse interference filtering unit, the second pulse interference filtering unit, the third pulse interference filtering unit and the fourth pulse interference filtering unit are pulse interference filtering units with the same structural parameters;
the pulse interference filtering unit comprises a forward anti-interference circuit, a reverse anti-interference circuit and a data selector;
the input signals of the forward anti-jamming circuit and the reverse anti-jamming circuit are input pulses of a pulse interference filtering unit; the data selector is an alternative data selector; two data input ends of the data selector are respectively connected to the output ends of the forward anti-jamming circuit and the reverse anti-jamming circuit;
the output signal of the data selector is the output pulse of the pulse interference filtering unit; the data selector performs data selection control by the output pulse;
the forward anti-interference circuit comprises a fast discharge diode, a charging resistor, a forward anti-interference capacitor and a forward anti-interference Schmitt circuit; the cathode of the rapid discharge diode is the input end of the forward anti-interference circuit, and the anode of the rapid discharge diode is connected to the input end of the forward anti-interference Schmitt circuit; the charging resistor is connected with the quick discharging diode in parallel; one end of the forward anti-interference capacitor is connected to the input end of the forward anti-interference Schmitt circuit, and the other end of the forward anti-interference capacitor is connected to the public ground of the pulse interference filtering unit or a power supply;
the reverse anti-interference circuit comprises a quick charging diode, a discharging resistor, a reverse anti-interference capacitor and a reverse anti-interference Schmitt circuit; the anode of the rapid charging diode is the input end of the reverse anti-interference circuit, and the cathode of the rapid charging diode is connected to the input end of the reverse anti-interference Schmitt circuit; the discharge resistor is connected with the quick charge diode in parallel; one end of the reverse anti-interference capacitor is connected to the input end of the reverse anti-interference Schmitt circuit, and the other end of the reverse anti-interference capacitor is connected to the public ground or the power supply of the pulse interference filtering unit;
the output end of the forward anti-interference Schmitt circuit is the output end of the forward anti-interference circuit, and the output end of the reverse anti-interference Schmitt circuit is the output end of the reverse anti-interference circuit.
2. A rail track circuit shunt system as claimed in claim 1, wherein:
the left wheel sensor is arranged on the outer side or the inner side of the left track, and the right wheel sensor is arranged on the outer side or the inner side of the right track and is positioned on the same axle line;
the left two-wheel sensor is arranged on the outer side or the inner side of the left track, and the right two-wheel sensor is arranged on the outer side or the inner side of the right track and is positioned on the same axle line;
the left three-wheel sensor is arranged on the outer side or the inner side of the left track, and the right three-wheel sensor is arranged on the outer side or the inner side of the right track and is positioned on the same axle line;
the four left wheel sensors are arranged on the outer side or the inner side of the left track, and the four right wheel sensors are arranged on the outer side or the inner side of the right track and are positioned on the same axle line.
3. A rail track circuit shunt system as claimed in claim 2, wherein:
the axle counting and shunting unit comprises a counting pulse generation module, a counter module and a judgment module;
the function of the counting pulse generation module is as follows: when the first axle counting pulse signal and the second axle counting pulse signal meet the entering logic state of the axle, or the third axle counting pulse signal and the fourth axle counting pulse signal meet the entering logic state of the axle, the counting pulse output end outputs a counting pulse; when the first axle counting pulse signal and the second axle counting pulse signal meet the outgoing logic state of the axle, or the third axle counting pulse signal and the fourth axle counting pulse signal meet the outgoing logic state of the axle, the countdown pulse output end outputs a countdown pulse;
the counter module functions to: the counting pulse generating module outputs an up-counting pulse and the output thereof increases 1, and the counting pulse generating module outputs a down-counting pulse and the output thereof decreases 1;
the function of the discrimination module is as follows: and when the output of the counter module is not equal to 0, the output track blocking interval occupation signal is valid, otherwise, the output track blocking interval occupation signal is invalid.
4. A rail track circuit branching system as claimed in any one of claims 2 to 3, wherein: when the output signal of the data selector and the input signal of the forward anti-interference circuit are in-phase relation, the output signal of the data selector and the input signal of the reverse anti-interference circuit are also in-phase relation; when the output signal of the data selector and the input signal of the forward anti-jamming circuit are in an inverse correlation system, the output signal of the data selector and the input signal of the reverse anti-jamming circuit are also in an inverse correlation system.
5. A rail track circuit branching system as claimed in claim 4, wherein: the specific method that the data selector carries out data selection control by the output pulse is that when the output signal of the data selector and the input signal of the forward anti-interference circuit are in-phase relation and the output signal of the data selector and the input signal of the reverse anti-interference circuit are in-phase relation, the low level of the output pulse controls the data selector to select the output signal of the forward anti-interference circuit to be sent to the output end of the data selector, and the high level controls the data selector to select the output signal of the reverse anti-interference circuit to be sent to the output end of the data selector; when the output signal of the data selector and the input signal of the forward anti-jamming circuit are in an inverse correlation system, and the output signal of the data selector and the input signal of the reverse anti-jamming circuit are in an inverse correlation system, the low level of the output pulse controls the data selector to select the output signal of the reverse anti-jamming circuit to be sent to the output end of the data selector, and the high level controls the data selector to select the output signal of the forward anti-jamming circuit to be sent to the output end of the data selector.
6. A rail track circuit branching system as claimed in claim 5, wherein: the positive narrow pulse width that the pulse interference filtering unit can filter is controlled by changing the charging time constant, and the negative narrow pulse width that can filter is controlled by changing the discharging time constant.
7. A rail track circuit branching system as claimed in claim 6, wherein: the charging time constant is the product of a charging resistor and a forward anti-interference capacitor; and the discharge time constant is the product of a discharge resistor and the reverse anti-interference capacitor.
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| CN2016104151866 | 2016-06-15 | ||
| CN201610415186.6A CN105835903A (en) | 2016-06-15 | 2016-06-15 | Steel rail type track circuit shunting system |
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| CN108116447B (en) * | 2017-12-12 | 2020-05-08 | 交控科技股份有限公司 | Method for processing poor shunting of track circuit |
| CN107953899B (en) * | 2017-12-21 | 2024-02-23 | 通号(西安)轨道交通工业集团有限公司北京分公司 | Electronic interface device for axle counting |
| CN108183942B (en) * | 2017-12-21 | 2021-01-22 | 通号（北京）轨道工业集团有限公司 | Test system of axle counting electronic interface device |
| CN110304109B (en) * | 2019-06-17 | 2022-02-18 | 深圳科安达电子科技股份有限公司 | Axle counting method capable of preventing axle from being lost |
| CN110293996B (en) * | 2019-06-17 | 2021-08-24 | 深圳科安达电子科技股份有限公司 | Tramcar track anti-interference axle counting method |
| CN112298275A (en) * | 2019-07-26 | 2021-02-02 | 比亚迪股份有限公司 | Train section occupation detection method, device and system |
| CN112849226B (en) * | 2019-11-27 | 2022-03-18 | 比亚迪股份有限公司 | Speed measuring method of rail vehicle, storage medium and electronic equipment |
| CN113212494A (en) * | 2021-05-13 | 2021-08-06 | 神华新朔铁路有限责任公司 | Track circuit microcomputer shunting method, system and storage medium |
| CN116534091B (en) * | 2023-07-06 | 2023-10-27 | 北京和利时系统工程有限公司 | Method for realizing adjacent line interference analysis, computer storage medium and terminal |
| CN117208034A (en) * | 2023-10-07 | 2023-12-12 | 温州市铁路与轨道交通投资集团有限公司 | Two-out-of-two architecture axle counting equipment data processing method and device and axle counting equipment |
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| CN201012690Y (en) * | 2007-02-06 | 2008-01-30 | 河南辉煌科技股份有限公司 | Rail wheel transducer |
| CN201362265Y (en) * | 2009-03-09 | 2009-12-16 | 河南蓝信科技有限公司 | Train FBG axle counting system |
| CN101934746A (en) * | 2010-09-29 | 2011-01-05 | 许继集团有限公司 | Automatic neutral-section passing device for electric locomotive |
| CN102285362A (en) * | 2011-06-16 | 2011-12-21 | 王国润 | Wheel detecting device with two axle counters and axle count calculating method thereof |
| CN102582659B (en) * | 2012-01-19 | 2016-05-04 | 中国神华能源股份有限公司 | Wheel takies judgment means and determination methods to counting device, track section |
| CN104316858B (en) * | 2014-11-04 | 2017-04-05 | 北京金自天正智能控制股份有限公司 | A kind of AC-AC frequency converter turn on thyristors state monitoring apparatus |
| CN105438220B (en) * | 2015-12-24 | 2017-04-12 | 北京安润通电子技术开发有限公司 | Redundant fault-tolerant axle counting processing device and processing method thereof |
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Effective date of registration: 20201125 Address after: 233000 603, 6th floor, investment building, 1757 Tushan East Road, Bengbu Economic Development Zone, Anhui Province Patentee after: Bengbu LU-03 Technology Consulting Co., Ltd Address before: 412007 science and Technology Department, Hunan University of Technology, 88 West Taishan Road, Zhuzhou, Hunan Patentee before: HUNAN University OF TECHNOLOGY |