CN106712729A - CMOS power amplifier with high linearity - Google Patents
CMOS power amplifier with high linearity Download PDFInfo
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- CN106712729A CN106712729A CN201611191553.5A CN201611191553A CN106712729A CN 106712729 A CN106712729 A CN 106712729A CN 201611191553 A CN201611191553 A CN 201611191553A CN 106712729 A CN106712729 A CN 106712729A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3205—Modifications of amplifiers to reduce non-linear distortion in field-effect transistor amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
- H03F1/0205—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers
- H03F1/0211—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation in transistor amplifiers with control of the supply voltage or current
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3211—Modifications of amplifiers to reduce non-linear distortion in differential amplifiers
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/45—Differential amplifiers
- H03F3/45071—Differential amplifiers with semiconductor devices only
- H03F3/45076—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier
- H03F3/45376—Differential amplifiers with semiconductor devices only characterised by the way of implementation of the active amplifying circuit in the differential amplifier using junction FET transistors as the active amplifying circuit
- H03F3/45394—Pl types
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/45—Indexing scheme relating to differential amplifiers
- H03F2203/45024—Indexing scheme relating to differential amplifiers the differential amplifier amplifying transistors are cascode coupled transistors
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- Power Engineering (AREA)
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- Nonlinear Science (AREA)
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Abstract
The invention discloses a CMOS power amplifier with high linearity. The CMOS power amplifier comprises an amplifier unit and an envelope detection unit. The amplifier unit comprises one or more power transistors used for performing power amplification on input signals to obtain output signals. The envelope detection unit detects the input signals of the power transistors and generates envelope signals to serve as substrate bias voltages of the corresponding power transistors. According to the CMOS power amplifier disclosed by the invention, as the substrate voltages of the power transistors are adjusted by the envelope signals of the input signals of the power transistors, the linearity of the power amplifier can be effectively improved, and compared with the prior art of adjusting the grid voltages or supply voltages of the power transistors by adopting the envelope signals, the linearity is improved more effectively. The CMOS power amplifier further has a certain effect of improving the efficiency of the power amplifier.
Description
Technical field
The application is related to a kind of CMOS power amplifier, more particularly to a kind of CMOS power amplifier of substrate bias.
Background technology
Faced the challenge in many performance indications using standard CMOS process design power amplifier, wherein in order to be lifted
Existing some schemes of the linearity of CMOS power amplifier are suggested.
In December, 2013《IEEE microwave theory and technique transactions》(IEEE TRANSACTIONS ON MICROWAVE
THEORY AND TECHNIQUES) there is an article on the 12nd phase of volume 61《It is total to by the CMOS of adaptive-biased control realization
The linearisation of the common grid power amplifier in source》(Linearization of CMOS Cascode Power Amplifiers
Through Adaptive Bias Control), this article is described and uses the cascade power of adaptive bias circuit
The linearization technique of amplifier, as shown in Figure 1.It is made up of a common-source amplifier M1 and a cathode-input amplifier M2 cascade first
Common source and common grid amplifier all the way, then differential configuration is formed by two-way common source and common grid amplifier, then by envelope detector Env_
Detection, altogether common source biasing circuit CS_Bias, the part one adaptive-biased electricity of composition of gate bias circuit CG_Bias tri-
Road.Envelope detector Env_detection obtains the envelope signal of radio-frequency input signals RFin, and the envelope signal is sent to common source
The grid of biasing circuit CS_Bias and the altogether grid of gate bias circuit CG_Bias.Common source biasing circuit CS_Bias is put for common source
Big device M1 provides drain bias voltage Vcs, and common gate bias circuit CG_Bias provides gate bias voltage for cathode-input amplifier M2
Vcg, the biasing that they are provided all changes with the change of envelope signal.When the input power is increased, common gate bias circuit
The gate bias voltage Vcg of CG_Bias outputs reduces, and vice versa.The program is to change to be supplied to common source and common grid amplifier
Gate bias voltage Vcg improves the linearity of power amplifier, although reduce radio-frequency input signals RFin common into common source
The time of grid amplifier cut-off region, but cause that the gain of common source and common grid amplifier changes simultaneously, non-linear factor is introduced, so
It is limited to linearity improvement.In addition Dynamic Gate Bias are carried out common source and common grid amplifier to be only used for improving the linear of circuit
Degree, limits otherwise application, such as gain-adjusted.Use similar scheme also have application publication number for
CN105917579A, Shen Qing Publication day are in August, 2016 Chinese invention patent application of 31 days《Amplifier system and method》, lack
Point is also similar.
2 months 2013《IEEE microwave theory and technique transactions》There is an article on the 2nd phase of volume 61《Multistage common source is total to
The cascade feedback biasing technology of the Linear CMOS power amplifier of grid topology》(A Cascode Feedback Bias
Technique for Linear CMOS Power Amplifiers in a Multistage Cascode Topology),
This article describes cascade feedback biasing linearization technique, as shown in Figure 2.Power amplifier includes driving stage and power
Level, they are all cascode structures.Radio-frequency input signals RFin passes sequentially through the common source crystal of input matching network, driving stage
Pipe M1, the common gate transistor M2 of driving stage, inter-stage matching network, the common source transistors M3 of power stage, the common grid crystal of power stage
Become radio frequency output signal RFout after pipe M4, output matching network.Also there is feedback biasing net between power stage and driving stage
Network, for the radio frequency leakage signal of the gate location of the common gate transistor M4 of power stage to be fed back to the common gate transistor of driving stage
The grid of M2.This common gate transistor M2, the M4 that can change driving stage and power stage in unit period enter cut-off region and linear
The time in area, so as to improve the linearity of power amplifier.But the program does not account for driving stage and the common source of power stage is brilliant
Body pipe M1, M3 is on nonlinear influence, and the improvement to the linearity is limited.And the power that the program is only used for multilevel hierarchy is put
Big device, limits its scope of application.
The content of the invention
Technical problems to be solved in this application are to provide a kind of CMOS power amplifier of high linearity, can overcome by
The nonlinear problem caused by input power is excessive, moreover it is possible to overcome the efficiency (PAE) because output power controlling circuit brings to ask
Topic.
In order to solve the above technical problems, this application provides a kind of CMOS power amplifier of high linearity, including amplify
Device unit and envelope detected unit.Amplifier unit includes one or more power transistors, and power is carried out to input signal
Output signal is obtained after amplification.Envelope detected unit detects the input signal of each power transistor and produces envelope signal conduct
The Substrate bias voltage of corresponding power transistor.
In embodiment one, the amplifier unit is common-source amplifier one, and common-source amplifier a pair of input signals is carried out
Output signal is obtained after power amplification.The envelope detected unit is envelope detector one, the detection input letter of envelope detector one
Number envelope produce envelope signal one, the envelope signal one as common-source amplifier one Substrate bias voltage.
In embodiment two, the amplifier unit is cathode-input amplifier one, and cathode-input amplifier a pair of input signals is carried out
Output signal is obtained after power amplification.The envelope detected unit is envelope detector one, the detection input letter of envelope detector one
Number envelope produce envelope signal one, the envelope signal one as cathode-input amplifier one Substrate bias voltage.
In embodiment three, the amplifier unit is common source and common grid amplifier, by common-source amplifier one and grid amplification altogether
The cascaded series of device one into.Common-source amplifier a pair of input signals obtains M signal after carrying out power amplification；A pair of cathode-input amplifier
M signal obtains output signal after carrying out power amplification.The envelope detected unit includes envelope detector one and envelope detected
Device two.The envelope of the detection input signal of envelope detector one produces envelope signal one, and the envelope signal one is used as common-source amplifier
One Substrate bias voltage.The envelope of the detection M signal of envelope detector two produces envelope signal two, the envelope signal two to make
It is the Substrate bias voltage of cathode-input amplifier one.
More than amplifier unit in each embodiment or be single ended input, the single-ended structure of Single-end output, Huo Zhewei
The differential configuration of Differential Input, difference output.
The application is the Substrate bias that power transistor is adjusted using the envelope signal of the input signal of power transistor
Voltage, can effectively improve the linearity of power amplifier, than the grid electricity that power transistor is adjusted using envelope signal
It is more effective to the improvement of the linearity in the prior art of pressure and/or supply voltage.The application is also to the efficiency of raising power amplifier
With certain effect.
Brief description of the drawings
Fig. 1 is a kind of schematic diagram of the cascade power amplifier of existing use adaptive bias circuit.
Fig. 2 is a kind of schematic diagram of the cascade power amplifier of existing use feedback biasing linearization technique.
Fig. 3 is the signal of the embodiment one (common-source amplifier) of the CMOS power amplifier of the high linearity that the application is provided
Figure.
Fig. 4 is the schematic diagram that embodiments herein one is changed to differential configuration.
Fig. 5 is the signal of the embodiment two (cathode-input amplifier) of the CMOS power amplifier of the high linearity that the application is provided
Figure.
Fig. 6 is the schematic diagram that embodiments herein two is changed to differential configuration.
Fig. 7 is the embodiment three (common source and common grid amplifier) of the CMOS power amplifier of the high linearity that the application is provided
Schematic diagram.
Fig. 8 is the schematic diagram that embodiments herein three is changed to differential configuration.
Fig. 9 be the application provide CMOS power amplifier with traditional CMOS power amplifier in linearity index
Emulation schematic diagram.
Description of reference numerals in figure：M1, M3, CS1, CS2 are common-source amplifier；M2, M4, CG1, CG2 are cathode-input amplifier；
Env_detection, EvDt1, EvDt2 are envelope detector；CS_Bias is common source biasing circuit；CG_Bias is common gate bias
Circuit；R is resistance；C is electric capacity；L is inductance；Z is impedance；T is transformer；RFin is radio-frequency input signals；RFout is radio frequency
Output signal；In is input signal；Mid is M signal；Out is output signal；VDD is supply voltage；Vcs amplifies for common source
The drain bias voltage of device；Vg1 is the gate bias voltage of common-source amplifier；Vcg, Vg2 are the gate bias of cathode-input amplifier
Voltage；Ev1 is envelope signal one (the Substrate bias voltage of common-source amplifier)；Ev2 is the (lining of cathode-input amplifier of envelope signal two
Bottom bias voltage).
Specific embodiment
The CMOS power amplifier of the high linearity that the application is provided is used for carrying out power amplification to input signal in, obtains
Output signal out.The input signal in of the power amplifier can be radiofrequency signal or baseband signal etc..
Fig. 3 is referred to, this is the embodiment one of the CMOS power amplifier of the high linearity that the application is provided.The embodiment
One includes the CS1 of the common-source amplifier one and EvDt1 of envelope detector one.The CS1 of common-source amplifier one receives input signal in, to it
Carry out output signal output out after power amplification.On the one hand the grid of the CS1 of common-source amplifier one connects power by the C1 of electric capacity one
The input of amplifier, on the other hand receives the Vg1 of gate bias voltage one by the R1 of resistance one.The leakage of the CS1 of common-source amplifier one
On the one hand pole connect the output end of power amplifier by the C2 of electric capacity two, on the other hand receives supply voltage by the L1 of inductance one
VDD.The source ground of the CS1 of common-source amplifier one.The C1 of electric capacity one and the C2 of electric capacity two play a part of blocking and impedance matching.Resistance
One R1 is big resistance, and it is the power loss for preventing AC signal to provide gate bias by the R1 of resistance one.The L1 of inductance one rises
To the effect of impedance matching.The envelope of the input signal in of the EvDt1 of envelope detector one detection power amplifiers produces an electricity
Pressure signal is referred to as the Ev1 of envelope signal one, as the substrate bias of the CS1 of common-source amplifier one after the envelope signal one Ev1 outputs.
In the embodiment one, when the amplitude increase of the input signal in of power amplifier is that power increases, envelope signal
One Ev1 also increases therewith, and the underlayer voltage of the CS1 of common-source amplifier one is also increased.For MOS transistor, when substrate electricity
Pressure is raised and source voltage when being held essentially constant, and the magnitude of voltage of source electrode to substrate is reduced, and threshold voltage is also decreased.MOS
After the threshold voltage reduction of transistor, the time that input signal is operated in the cut-off region of MOS transistor within unit period subtracts
Small, the time for being correspondingly operated in the linear zone of MOS transistor increased, and being exaggerated the non-linear of signal will reduce, from
And improve the linearity of power amplifier.
The threshold voltage V of MOS transistorTHCan be formulated as
Wherein VTH0Threshold voltage of the underlayer voltage with source voltage when identical is represented, γ represents bulk effect constant, ΦFRepresent Fermi's energy
Level, VSBRepresent source electrode to the magnitude of voltage of substrate.
In the embodiment one, when the amplitude increase of the input signal in of power amplifier is that power increases, envelope signal
One Ev1 also increases therewith, and the underlayer voltage of the CS1 of common-source amplifier one is also increased.For MOS transistor, when substrate electricity
Pressure is raised and source voltage when being held essentially constant, and the magnitude of voltage of source electrode to substrate is reduced, and threshold voltage is also decreased.MOS
After the threshold voltage reduction of transistor, overdrive voltage is raised so that the gain of MOS transistor becomes big, improves power amplification
The efficiency of device.When the amplitude reduction of the input signal in of power amplifier is power reduction, the Ev1 of envelope signal one also subtracts therewith
Small, the underlayer voltage of the CS1 of common-source amplifier one is also decreased.For MOS transistor, when underlayer voltage reduction, source electrode is electric
When pressure is held essentially constant, the magnitude of voltage of source electrode to substrate is raised, and threshold voltage is also increased.The threshold value electricity of MOS transistor
After pressure is raised, overdrive voltage reduction so that the conducting electric current of MOS transistor reduces, so as to improve the effect of power amplifier
Rate.
In embodiment one shown in Fig. 3, the CS1 of common-source amplifier one is the single-ended structure of single ended input, Single-end output, also may be used
The differential configuration of Differential Input, difference output is changed to, as shown in Figure 4.CMOS power amplifier shown in Fig. 4 includes that input is matched
Network, difference common-source amplifier, output matching network and the EvDt1 of envelope detector one.
The input matching network is, for example, the Tin of transformer one, and the input for realizing power amplifier is total to difference
Impedance matching between the input of source amplifier, while single-ended signal is converted into differential signal.The primary of the Tin of transformer one
The input signal in of one end receiving power amplifier of coil, other end ground connection.The secondary coil of the Tin of transformer one has center
Tap, the two ends of the secondary coil export a pair of differential input signal in1 to the two-way input of difference common-source amplifier respectively
And in2, the centre cap of the secondary coil meets the gate bias voltage Vg1 of common-source amplifier.
The difference common-source amplifier includes two-way, and a pair of differential input signals in1 and in2 are carried out into power amplification respectively
After export a pair of differential output signals out1 and out2.The first via of difference common-source amplifier is the CS1 of common-source amplifier one, second
Road is the CS2 of common-source amplifier two.
The output matching network is, for example, the Tout of transformer two, for realizing the output end and work(of difference common-source amplifier
Impedance matching between the output end of rate amplifier, while differential signal is converted into single-ended signal.The Tout's of transformer two is first
Level coil has centre cap, and the two ends of the primary coil receive the one of the two-way output end output of difference common-source amplifier respectively
To differential output signal out1 and out2, the centre cap of the primary coil connects the drain voltage of common-source amplifier CS1 and CS2 i.e.
Supply voltage VDD.The output signal out of one end output power amplifier of the secondary coil of the Tout of transformer two, another termination
Ground.
The EvDt1 of the envelope detector one can using a pair of differential input signal in1 of the Tin of transformer one outputs and
Any one of in2 exemplarily uses in1 as input, in Fig. 4 as the input of the EvDt1 of envelope detector one.Envelope is examined
The envelope for surveying the EvDt1 of device one detection radio-frequency input signals produces a voltage signal to be referred to as the Ev1 of envelope signal one, the envelope signal
One Ev1 output after as difference common-source amplifier two-way common-source amplifier CS1 and CS2 substrate bias.
Fig. 5 is referred to, this is the embodiment two of the CMOS power amplifier of the high linearity that the application is provided.The embodiment
Two include the CG1 of the cathode-input amplifier one and EvDt1 of envelope detector one.The CG1 of cathode-input amplifier one receives input signal in, to it
Carry out output signal output out after power amplification.The source electrode of the CG1 of cathode-input amplifier one connects power amplifier by the C1 of electric capacity one
Input.On the one hand the drain electrode of the CG1 of cathode-input amplifier one connects the output end of power amplifier, the opposing party by the C2 of electric capacity two
Face receives supply voltage VDD by the L1 of inductance one.The grid of the CG1 of cathode-input amplifier one receives gate bias electricity by the R1 of resistance one
Press two Vg2.The C1 of electric capacity one and the C2 of electric capacity two play a part of blocking and impedance matching.The R1 of resistance one is big resistance, by resistance
It is the power loss for preventing AC signal that one R1 provides gate bias.The L1 of inductance one plays a part of impedance matching.Envelope
The envelope of the input signal in of the EvDt1 of detector one detection power amplifiers produces a voltage signal to be referred to as envelope signal one
As the substrate bias of the CG1 of cathode-input amplifier one after Ev1, the envelope signal one Ev1 output.
In the embodiment two, when the amplitude increase of the input signal in of power amplifier is that power increases, envelope signal
One Ev1 also increases therewith, and the underlayer voltage of the CG1 of cathode-input amplifier one is also increased, and threshold voltage is also decreased.It is now defeated
The time for entering the cut-off region that signal is operated in MOS transistor within unit period reduces, and is correspondingly operated in MOS transistor
Time of linear zone increased, being exaggerated the non-linear of signal will reduce, so as to improve the linearity of power amplifier.
In the embodiment two, when the amplitude increase of the input signal in of power amplifier is that power increases, envelope signal
One Ev1 also increases therewith, and the underlayer voltage of the CS1 of common-source amplifier one is also increased, and threshold voltage is also decreased.Now cross
Driving voltage is raised so that the gain of MOS transistor becomes big, improves the efficiency of power amplifier.It is defeated when power amplifier
When the amplitude for entering signal in reduces i.e. power reduction, the Ev1 of envelope signal one also reduces therewith, the substrate of the CS1 of common-source amplifier one
Voltage is also decreased, and threshold voltage is also increased.Now overdrive voltage reduction so that the conducting electric current of MOS transistor
Reduce, so as to improve the efficiency of power amplifier.
In embodiment two shown in Fig. 5, the CG1 of cathode-input amplifier one is the single-ended structure of single ended input, Single-end output, also may be used
The differential configuration of Differential Input, difference output is changed to, as shown in Figure 6.CMOS power amplifier shown in Fig. 6 includes that input is matched
Network, difference cathode-input amplifier, output matching network and the EvDt1 of envelope detector one.
The input matching network is, for example, the Tin of transformer one, and the input for realizing power amplifier is total to difference
Impedance matching between the input of source amplifier, while single-ended signal is converted into differential signal.The output matching network
The for example, Tout of transformer two, for realizing the resistance between the output end of difference common-source amplifier and the output end of power amplifier
Anti- matching, while differential signal is converted into single-ended signal.Input matching network, the circuit structure of output matching network and company
Connect relation identical with Fig. 4, will not be repeated here.
The difference cathode-input amplifier includes two-way, and a pair of differential input signals in1 and in2 are carried out into power amplification respectively
After export a pair of differential output signals out1 and out2.The first via of difference cathode-input amplifier is the CG1 of cathode-input amplifier one, second
Road is the CG2 of cathode-input amplifier two.The grid of this two-way cathode-input amplifier CG1 and CG2 connects the gate bias voltage of common gate transistor
Vg2。
The EvDt1 of the envelope detector one can using a pair of differential input signal in1 of the Tin of transformer one outputs and
Any one of in2 exemplarily uses in1 as input, in Fig. 6 as the input of the EvDt1 of envelope detector one.Envelope is examined
The envelope for surveying the EvDt1 of device one detection radio-frequency input signals produces a voltage signal to be referred to as the Ev1 of envelope signal one, the envelope signal
One Ev1 output after as difference cathode-input amplifier two-way cathode-input amplifier CG1 and CG2 substrate bias.
Fig. 7 is referred to, this is the embodiment three of the CMOS power amplifier of the high linearity that the application is provided.The embodiment
Three include common source and common grid amplifier and two envelope detectors EvDt1, EvDt2.
The common source and common grid amplifier is made up of the CS1 of the common-source amplifier one and CG1 of cathode-input amplifier one cascades.Common source amplifies
The CS1 of device one receives input signal in, and M signal mid is exported after power amplification is carried out to it.During the CG1 of cathode-input amplifier one is received
Between signal mid, output signal output out after power amplification is carried out to it.The grid of the CS1 of common-source amplifier one is on the one hand by electricity
Hold the input that a C1 connects power amplifier, the Vg1 of gate bias voltage one is on the other hand received by the R1 of resistance one.Common source is put
The source electrode of drain electrode connection cathode-input amplifier one CG1 of the big CS1 of device one.The source ground of the CS1 of common-source amplifier one.Cathode-input amplifier
On the one hand the drain electrode of one CG1 connects the output end of power amplifier by the C2 of electric capacity two, is on the other hand received by the L1 of inductance one
Supply voltage VDD.The grid of the CG1 of cathode-input amplifier one receives the Vg2 of gate bias voltage two by the R1 of resistance two.The C1 of electric capacity one and
The C2 of electric capacity two plays a part of blocking and impedance matching.The R1 of resistance one and the R2 of resistance two are big resistance, by the R1 of resistance one or
It is the power loss for preventing AC signal that the R2 of resistance two provides gate bias.The L1 of inductance one plays a part of impedance matching.
The envelope of the input signal in of the EvDt1 of the envelope detector one detection power amplifiers produces a voltage signal
As the substrate bias of the CS1 of common-source amplifier one after the referred to as Ev1 of envelope signal one, the envelope signal one Ev1 output.
The envelope of the EvDt2 of the envelope detector two detection M signals mid produces a voltage signal to be referred to as envelope letter
As the substrate bias of the CG1 of cathode-input amplifier one after number two Ev2, the envelope signal two Ev2 output.
In the embodiment three, employ two envelope detectors EvDt1, EvDt2 and detect two power transistors respectively
The envelope of the input signal of CS1, CG1 simultaneously carrys out two underlayer voltages of power transistor CS1, CG1 of dynamic regulation with this.It is specific and
Speech, the envelope of the EvDt1 of envelope detector one detection input signals in is simultaneously electric in this, as the Substrate bias of the CS1 of common-source amplifier one
Pressure.The EvDt2 of envelope detector two detects the envelope of M signal mid and in this, as the Substrate bias of the CG1 of common gate transistor one
Voltage.Due to there is 180 ° of phase difference between the output signal mid and input signal in of the CS1 of common-source amplifier one, it is therefore desirable to
Detect that the envelope of input signal in and M signal mid obtains envelope and believes respectively using two envelope detectors EvDt1 and EvDt2
A number Ev1 also has 180 ° of phase difference with envelope signal two Ev2, the Ev2 of envelope signal two and the Ev1 of envelope signal one.This is just caused
The CG1 underlayer voltages Ev2 of cathode-input amplifier one and its input signal mid keeps Phase synchronization.
In the embodiment three, when the amplitude increase of the input signal in of power amplifier is that power increases, envelope signal
One Ev1 also increases therewith with the Ev2 of envelope signal two, the underlayer voltage of the CS1 of common-source amplifier one and the CG1 of cathode-input amplifier one with
Rising, threshold voltage decreases.Now input signal is operated in cutting for two power transistors within unit period
Only the time in area reduce, the time for being correspondingly operated in two linear zones of power transistor increased, and be exaggerated signal
It is non-linear to reduce, so as to improve the linearity of power amplifier.
In the embodiment three, when the amplitude increase of the input signal in of power amplifier is that power increases, envelope signal
One Ev1 also increases therewith with the Ev2 of envelope signal two, the underlayer voltage of the CS1 of common-source amplifier one and the CG1 of cathode-input amplifier one with
Rising, threshold voltage decreases.Now overdrive voltage is raised so that two gains of power transistor become big, carry
The efficiency of power amplifier high.When the amplitude reduction of the input signal in of power amplifier is power reduction, envelope signal
One Ev1 also reduces therewith with the Ev2 of envelope signal two, the underlayer voltage of the CS1 of common-source amplifier one and the CG1 of cathode-input amplifier one with
Reduction, threshold voltage increases.Now overdrive voltage reduction so that the conducting electric current of two power transistors subtracts
It is small, so as to improve the efficiency of power amplifier.
In embodiment three shown in Fig. 7, common source and common grid amplifier is the single-ended structure of single ended input, Single-end output, also may be used
The differential configuration of Differential Input, difference output is changed to, as shown in Figure 8.CMOS power amplifier shown in Fig. 8 includes that input is matched
Network, difference cascode amplifier, output matching network and two envelope detectors EvDt1, EvDt2.
The input matching network is, for example, the Tin of transformer one, and the input for realizing power amplifier is total to difference
Impedance matching between the input of source cathode-input amplifier, while single-ended signal is converted into differential signal.The output matching
Network is, for example, the Tout of transformer two, for realizing between the output end of difference common-source amplifier and the output end of power amplifier
Impedance matching, while differential signal is converted into single-ended signal.Input matching network, output matching network circuit structure with
And annexation is identical with Fig. 4, will not be repeated here.
The difference cascode amplifier includes two-way, and a pair of differential input signals in1 and in2 are carried out into power respectively
A pair of differential output signals out1 and out2 are exported after amplification.The first via of difference cascode amplifier includes the common source of cascade
The CS1 of the amplifier one and CG1 of cathode-input amplifier one, the second tunnel includes the CS2 of common-source amplifier two and cathode-input amplifier two of cascade
CG2.Two-way the common-source amplifier CS1 and CS2 of difference cascode amplifier receive a pair of differential input signal in1 and in2, defeated
Go out a pair of differential intermediate signals mid1 and mid2.Two-way the cathode-input amplifier CG1 and CG2 of difference cascode amplifier receive one
To differential intermediate signal mid1 and mid2, a pair of differential output signals out1 and out2 are exported.This two-way cathode-input amplifier CG1 and
The grid of CG2 meets the gate bias voltage Vg2 of common gate transistor.It is anti-that the R1 of resistance one and the C1 of electric capacity one of cascade constitute the first via
Feedback, first via feedback is in parallel with the first via of common source and common grid amplifier.The R2 of resistance two and the C2 of electric capacity two of cascade constitute second
Road is fed back, and the second tunnel feedback is in parallel with the second tunnel of common source and common grid amplifier.Two-way feedback is used for improving the steady of power amplifier
It is qualitative.
The EvDt1 of the envelope detector one can using a pair of differential input signal in1 of the Tin of transformer one outputs and
Any one of in2 exemplarily uses in1 as input, in Fig. 8 as the input of the EvDt1 of envelope detector one.Envelope is examined
The envelope for surveying the EvDt1 of device one detection radio-frequency input signals produces a voltage signal to be referred to as the Ev1 of envelope signal one, the envelope signal
One Ev1 output after as difference cascode amplifier two-way common-source amplifier CS1 and CS2 substrate bias.
The EvDt2 of the envelope detector two can using difference cascode amplifier two-way common-source amplifier CS1 and
Any one of a pair of differential intermediate signals mid1 and mid2 of CS2 outputs are exemplarily made in Fig. 8 as input using mid1
It is the input of the EvDt2 of envelope detector two.The envelope of the EvDt2 of envelope detector two detection radio frequency M signals produces a voltage
Signal is referred to as the Ev2 of envelope signal two, and the common grid of two-way after the envelope signal two Ev2 outputs as difference cascode amplifier are put
The substrate bias of big device CG1 and CG2.
It has been specifically designed in CMOS power amplifier shown in Fig. 8 from the output end of difference cascode amplifier to input
The feedback channel at end, for improving the stability of power amplifier.Based on same principle, the CMOS power amplifications in Fig. 3 to Fig. 7
Device can increase from the output end of amplifier unit to the feedback channel of input.The increased feedback channel of institute constitutes negative-feedback
Power amplifier system, can be effectively reduced voltage gain, increase the loop bandwidth of system.Cause power amplifier unstable
Fixed factor is mainly output end to the coupled capacitor of input, and this coupled capacitor is due to Miller effect (Miller
Effect the amplification with the same multiple of amplifier) is obtained, therefore reduction gain can improve the stability of power amplifier.Pass through
Negative-feedback reduces gain, can also improve the linearity of power amplifier.
Each embodiment of summary is it can be found that the application is by increasing input of the envelope detector to power transistor
Signal is detected and is obtained envelope signal, and recycling envelope signal carrys out the underlayer voltage of the dynamic regulation power transistor, this
Can be described as dynamic underlayer voltage biasing technique (dynamic body bias, be abbreviated as DBB).Existing power amplifier is defeated
Enter power it is excessive when be easily caused nonlinear problem, the application is improved this.In order to improve the linear of power amplifier
Degree, prior art understands sacrificial section power output mostly, and this brings the efficiency of power amplifier, and the application is to this
It has been also carried out improving.Due to needing the underlayer voltage to MOS transistor to carry out dynamic regulation, it finds particular application to have depth
The standard CMOS process of n traps (DNW) technique, the MOS transistor of deep n traps technique manufacture has independent substrate layer and underlayer voltage
Bias terminal thus can easily change Substrate bias voltage.
Fig. 9 is referred to, this is that the result emulated to conventional power amplifier and the application power amplifier is illustrated
Figure.Abscissa therein is power output Pout, and ordinate is third order intermodulation distortion IMD3, and this is one for characterizing the linearity
Index.Curve one represents the conventional power amplifier for being provided without dynamic underlayer voltage biasing technique, and curve two is represented and employed
The application power amplifier of dynamic underlayer voltage biasing technique.Compared with curve one, curve two has a Dou JiangVXing area
Domain.The V-type region representation in the output power range, the nonlinear properties very little that power amplifier is produced, i.e. harmonic signal
Weaker, mixing generation third order intermodulation distortion mutually will reduce.The reason for producing V-type region is power transistor in input power
When larger, preferably, the application is believed the linearity in a certain specific input power and biasing by the input of power transistor again
Number adjust its underlayer voltage so that CMOS power transistors diminish due to the distortion that big signal input causes, so as to reduce three
Rank crosstalk.Just can be with the V-type region of steep drop in forming curves two when harmonic component is minimum in output signal.In curve
In one, if to power transistor one than relatively low biasing, it can be seen that this V bottoms, it is done so that can cause that power is brilliant
The ratio of gains of body pipe is relatively low.And the dynamic underlayer voltage biasing technique that the application is provided is employed, will not be reduced when V bottoms are produced
Gain.
Compared with existing CMOS power amplifier, the application mainly has following technique effect.
First, in order to improve the linearity of power amplifier, it is brilliant that prior art adjusts power using envelope signal mostly
The grid voltage and/or supply voltage of body pipe, the application are then the underlayer voltages that power transistor is adjusted using envelope signal.
Compared with the grid voltage and/or supply voltage of regulation power transistor, it is non-linear smaller that the application is introduced, to the linearity
Improve more effective.
Second, the application is adjusted by the underlayer voltage to power transistor, can effectively be improved due to input
Nonlinear problem caused by power is excessive, and the efficiency of power amplifier is improved to a certain extent.
3rd, the application provide dynamic underlayer voltage biasing technique go for common-source amplifier, cathode-input amplifier,
Common source and common grid amplifier etc., while suitable for single-ended structure or the amplifier unit of differential configuration.Can using differential configuration
To suppress the common-mode signal and noise on the passages such as signal, power supply, the performance indications of power amplifier are further improved.
The preferred embodiment of the application is these are only, is not used to limit the application.Come for those skilled in the art
Say, the application there can be various modifications and variations.It is all any modifications within spirit herein and principle, made, equivalent
Replace, improve etc., should be included within the protection domain of the application.
Claims (12)
1. a kind of CMOS power amplifier of high linearity, it is characterized in that, including amplifier unit and envelope detected unit；Put
Big device unit includes one or more power transistors, and output signal is obtained after carrying out power amplification to input signal；Envelope is examined
Unit is surveyed to detect the input signal of each power transistor and produce envelope signal as the Substrate bias of corresponding power transistor
Voltage.
2. the CMOS power amplifier of high linearity according to claim 1, it is characterized in that, the amplifier unit is common
Source amplifier one, common-source amplifier a pair of input signals obtains output signal after carrying out power amplification；
The envelope detected unit is envelope detector one, and the envelope of the detection input signal of envelope detector one produces envelope signal
One, the envelope signal one as common-source amplifier one Substrate bias voltage.
3. the CMOS power amplifier of high linearity according to claim 2, it is characterized in that, the grid of common-source amplifier one
On the one hand the input of power amplifier is connected by electric capacity one, gate bias voltage one is on the other hand received by resistance one；
On the one hand the drain electrode of common-source amplifier one connects the output end of power amplifier by electric capacity two, is on the other hand connect by inductance one
Receive supply voltage；The source ground of common-source amplifier one.
4. the CMOS power amplifier of high linearity according to claim 1, it is characterized in that, the amplifier unit is common
Grid amplifier one, cathode-input amplifier a pair of input signals obtains output signal after carrying out power amplification；
The envelope detected unit is envelope detector one, and the envelope of the detection input signal of envelope detector one produces envelope signal
One, the envelope signal one as cathode-input amplifier one Substrate bias voltage.
5. the CMOS power amplifier of high linearity according to claim 4, it is characterized in that, the source electrode of cathode-input amplifier one
The input of power amplifier is connected by electric capacity one；On the one hand the drain electrode of cathode-input amplifier one connects power and puts by electric capacity two
The output end of big device, on the other hand receives supply voltage by inductance one；The grid of cathode-input amplifier one is received by resistance one
Gate bias voltage two.
6. the CMOS power amplifier of high linearity according to claim 1, it is characterized in that, the amplifier unit is common
Source cathode-input amplifier, by common-source amplifier one and the cascaded series of cathode-input amplifier one into；Common-source amplifier a pair of input signals is carried out
M signal is obtained after power amplification；A pair of M signals of cathode-input amplifier obtain output signal after carrying out power amplification；
The envelope detected unit envelope envelope detector one and envelope detector two；The detection input signal of envelope detector one
Envelope produce envelope signal one, the envelope signal one as common-source amplifier one Substrate bias voltage；Envelope detector two is examined
Survey M signal envelope produce envelope signal two, the envelope signal two as cathode-input amplifier one Substrate bias voltage.
7. the CMOS power amplifier of high linearity according to claim 6, it is characterized in that, the grid of common-source amplifier one
On the one hand the input of power amplifier is connected by electric capacity one, gate bias voltage one is on the other hand received by resistance one；
The source electrode of the drain electrode connection cathode-input amplifier one of common-source amplifier one；The source ground of common-source amplifier one；Cathode-input amplifier one
Drain electrode on the one hand by electric capacity two connect power amplifier output end, on the other hand by inductance one receive supply voltage；
The grid of cathode-input amplifier one receives gate bias voltage two by resistance two.
8. the CMOS power amplifier of the high linearity according to any one of claim 2,4,6, it is characterized in that, it is described to put
Big device unit is single ended input, the single-ended structure of Single-end output, or is Differential Input, the differential configuration of difference output.
9. the CMOS power amplifier of high linearity according to claim 1, it is characterized in that, the CMOS power amplifier
Also include from the output end of amplifier unit to the feedback channel of input, every feedback channel is by resistance and electric capacity cascade structure
Into.
10. the CMOS power amplifier of high linearity according to claim 1, it is characterized in that, the CMOS power amplifications
Device is manufactured using the standard CMOS process with depth n trap techniques, and the MOS transistor of deep n traps technique manufacture has independent substrate
Voltage bias terminal.
The CMOS power amplifier of 11. high linearities according to claim 1, it is characterized in that, it is defeated when power amplifier
When the amplitude for entering signal increases i.e. power increase, each envelope signal also increases therewith, the underlayer voltage of each power transistor
Increase, threshold voltage is decreased；Now input signal is operated in each power transistor within unit period
Time of cut-off region reduce, the time for being correspondingly operated in the linear zone of each power transistor increased, and be exaggerated letter
Number it is non-linear will reduce, so as to improve the linearity of power amplifier.
The CMOS power amplifier of 12. high linearities according to claim 1, it is characterized in that, it is defeated when power amplifier
When the amplitude for entering signal increases i.e. power increase, each envelope signal one also increases therewith, the substrate electricity of each power transistor
Pressure is increased, and threshold voltage is decreased；Now overdrive voltage is raised so that the gain of each power transistor becomes
Greatly, improve the efficiency of power amplifier；
When the amplitude reduction of the input signal of power amplifier is power reduction, each envelope signal also reduces therewith, each
The underlayer voltage of power transistor is decreased, and threshold voltage is increased；Now overdrive voltage reduction so that each
The conducting electric current of power transistor reduces, so as to improve the efficiency of power amplifier.
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