CN106711102A - Semiconductor device, corresponding methods of production and use and corresponding apparatus - Google Patents
Semiconductor device, corresponding methods of production and use and corresponding apparatus Download PDFInfo
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- CN106711102A CN106711102A CN201610877351.XA CN201610877351A CN106711102A CN 106711102 A CN106711102 A CN 106711102A CN 201610877351 A CN201610877351 A CN 201610877351A CN 106711102 A CN106711102 A CN 106711102A
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- quadrangle
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 68
- 238000000034 method Methods 0.000 title claims description 17
- 238000004519 manufacturing process Methods 0.000 title claims description 7
- 238000005538 encapsulation Methods 0.000 claims description 59
- 238000005520 cutting process Methods 0.000 claims description 26
- 238000000465 moulding Methods 0.000 claims description 16
- 238000003466 welding Methods 0.000 claims description 15
- 238000009434 installation Methods 0.000 claims description 14
- 239000000758 substrate Substances 0.000 claims description 14
- 230000005611 electricity Effects 0.000 description 6
- 150000001875 compounds Chemical class 0.000 description 4
- 238000003698 laser cutting Methods 0.000 description 3
- 239000000463 material Substances 0.000 description 3
- 230000008859 change Effects 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 238000004080 punching Methods 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- UAOUIVVJBYDFKD-XKCDOFEDSA-N (1R,9R,10S,11R,12R,15S,18S,21R)-10,11,21-trihydroxy-8,8-dimethyl-14-methylidene-4-(prop-2-enylamino)-20-oxa-5-thia-3-azahexacyclo[9.7.2.112,15.01,9.02,6.012,18]henicosa-2(6),3-dien-13-one Chemical compound C([C@@H]1[C@@H](O)[C@@]23C(C1=C)=O)C[C@H]2[C@]12C(N=C(NCC=C)S4)=C4CC(C)(C)[C@H]1[C@H](O)[C@]3(O)OC2 UAOUIVVJBYDFKD-XKCDOFEDSA-N 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 230000009471 action Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000002305 electric material Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 238000007639 printing Methods 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 229920005989 resin Polymers 0.000 description 1
- 239000011347 resin Substances 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
- H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4825—Connection or disconnection of other leads to or from flat leads, e.g. wires, bumps, other flat leads
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4821—Flat leads, e.g. lead frames with or without insulating supports
- H01L21/4842—Mechanical treatment, e.g. punching, cutting, deforming, cold welding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
- H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
- H01L21/4853—Connection or disconnection of other leads to or from a metallisation, e.g. pins, wires, bumps
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/561—Batch processing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
- H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
- H01L21/565—Moulds
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/4952—Additional leads the additional leads being a bump or a wire
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49517—Additional leads
- H01L23/49524—Additional leads the additional leads being a tape carrier or flat leads
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49541—Geometry of the lead-frame
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Ceramic Engineering (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
A semiconductor device includes a quadrilateral package with a first pair of opposed sides and a second pair of opposed sides. Both sides of the first pair of opposed sides are provided with electrical contact leads. Only one side of the second pair of opposed sides is provided with electrical contact leads. The side of the second pair of opposed sides without electrical contact leads is a leadless side. That side is not a molded side of the package, but rather is defined by a cut surface.
Description
Cross-Reference to Related Applications
This application claims the disclosures in Italian patent application No.102015000073934 for coming from the submission of on November 18th, 2015
Priority, the disclosure of which is incorporated by reference into.
Technical field
This specification is related to semiconductor devices.
One or more embodiments can for example be applied to integrated circuit (IC).
Background technology
The such as various applications of the semiconductor devices of integrated circuit (IC) can include using quad flat package (QFP).
This encapsulation can be included in the electrical contact lead at the every side in four sides of quadrangle encapsulation.
Now, for example the various electronic systems in automotive field may can be used in different editions, for example, cover from low
Digital content vehicle to advanced vehicle scope, without related difference, except the quantity or computing capability level of such as interface.
For example, different envelopes can be utilized for the different platform of same application (such as passenger stock air bag system)
Size and different package layouts is filled to manage.
Additionally, these platforms can be due to for example solving their different target of low digital content or digital content high
And entity (ECU) is connected including such as special external, increase with encapsulation therefore and ECU costs.
Some solutions can include using the concentric area of coverage for being suitable for different packaging body sizes
(footprint)。
This can promote ECU to standardize and cost savings, and infringement is routing the signals to install substrate (for example, printing electricity
Road plate-PCB) flexibility and Electro Magnetic Compatibility-EMC performances.
Even these solutions can not be such that ultimate consumer exempts using the special ECU for each platform for identical
Using wherein each ECU is designed using special encapsulation combination and the different areas of coverage.
On the other hand, ultimate consumer may face reduce the quantity of different ECU with cover various types of vehicles and by
The need for the PCB space that each IC area of coverage is used.
The content of the invention
According to one or more embodiments, there is provided a kind of semiconductor devices.
One or more embodiments can also relate to produce and use the method for such device and for for example in vapour
The corresponding device used in car field (only lifts non-limiting example：In passenger stock air bag system).
One or more embodiments can provide the encapsulation with the side without lead (without lead).
In one or more embodiments, such encapsulation can be by that may be considered as that standard is sealed in other side
The encapsulation of dress carries out midway cutting, for example, be cut by laser and obtain so that two " half encapsulates " (may be equal to each other) can be from
May be obtained in the encapsulation that other side is considered as single standard QFP.
The need for one or more embodiments can exempt to special circuit, hence in so that can reduce and cutting (example
Such as laser equipment) existing assembling circuit is used in the case of related investment.
The additional advantage provided by one or more embodiments can include：Improve the assembly line the utilization/saturation on road, reduces
Cost in encapsulation assembling, the various materials that reduction is related to, and reduce the machine setting time.
In embodiment, a kind of semiconductor devices includes：Quadrangle is encapsulated, and it includes the first side and the second side and also bag
The 3rd side and the 4th side are included, wherein first side and second side are opposite sides and are provided with electrical contact lead, its
Described in the 3rd side and the 4th side be opposite side, and wherein described 3rd side is provided with electrical contact lead, and wherein
4th side is that, without lead side, and wherein described first side is to the molding side that the 3rd side is quadrangle encapsulation,
And the 4th side is the non-molding side limited by cutting surfaces of the quadrangle encapsulation.
In embodiment, a kind of semiconductor devices includes：Lead frame, it includes the first die pad and the weldering of the second nude film
Disk, first die pad and second die pad are by the bridging in the opposite end of the intermediate space being longitudinally extended
Connect the connection of device part；First IC chip, it is installed to first die pad；Second IC chip, its
It is installed to second die pad；Quadrangle is encapsulated, and it is to the lead frame, first IC chip and institute
The second IC chip is stated to be encapsulated and including the first side and the second side and also including the 3rd side and the 4th side, wherein
First side and second side are opposite sides, and first side includes being coupled to the first of first IC chip
Electrical contact lead and the second electrical contact lead for being coupled to second IC chip, second side includes being coupled to institute
The 3rd electrical contact lead for stating the first IC chip and the 4th electrical contact for being coupled to second IC chip are drawn
Line, wherein the 3rd side and the 4th side are opposite sides, the 3rd side includes being coupled to first ic core
5th electrical contact lead of piece, the 4th side includes being coupled to the 6th electrical contact lead of second IC chip；
The intermediate space of wherein described Longitudinal extending is configured as supporting that quadrangle encapsulation is cut into the first half encapsulation and second
Half encapsulates, wherein the first half encapsulation includes that first die pad, the first IC chip and first electricity connect
Lead, the 3rd electrical contact lead and the 5th electrical contact lead are touched, and the second half encapsulation includes described second
Die pad, the second IC chip and the second electrical contact lead, the 4th electrical contact lead and the 6th electricity
Contact lead-wire.
In embodiment, a kind of method for producing semiconductor devices includes：Quadrangle lead frame, the quadrangle are provided
Lead frame includes the first leadframe portion and the second leadframe portion with mid-plane in-between, wherein described
First leadframe portion and second leadframe portion include corresponding die pad welding zone, wherein electrical contact lead
Set is arranged on all sides of the quadrangle lead frame, and the first semiconductor die and the second semiconductor die are arranged in
On the corresponding die pad welding zone of first leadframe portion and second leadframe portion, by Encapsulation Moulds
Make with first semiconductor die being disposed thereon and the quadrangle lead frame of second semiconductor die
On frame, and there is first semiconductor die and second semiconductor being disposed thereon along mid-plane cutting
The quadrangle lead frame of nude film and the molding encapsulation thereon, thus produces and is separated at the mid-plane
Paired semiconductor devices.
In embodiment, a kind of method includes：Semiconductor devices is installed to installation substrate, the installation substrate is provided with
At least one quadrangle external connection entity, has electric contact structure on all sides of the quadrangle external connection entity,
Wherein described semiconductor devices includes quadrangle encapsulation, and quadrangle encapsulation includes the first side and the second side and also including the
Three sides and the 4th side, wherein first side and second side are opposite sides and are provided with electrical contact lead, wherein institute
It is opposite side to state the 3rd side and the 4th side, and wherein described 3rd side is provided with electrical contact lead, and wherein described
4th side is that, without lead side, and wherein described first side is to the molding side that the 3rd side is quadrangle encapsulation, and
4th side is the non-molding side limited by cutting surfaces of the quadrangle encapsulation, and the semiconductor devices is connected into institute
State at least one quadrangle external connection entity, wherein the electrical contact lead of the 3rd side with outside described at least one
The electric contact structure on the side of portion's connection entity makes electrical contact with, and the electricity of first side and second side connects
Lead is touched to be made electrical contact with the electric contact structure being arranged on two of at least one external connection entity other sides.
In embodiment, a kind of electronic installation includes：Substrate is installed, it includes at least one quadrangle external connection reality
Body, with electric contact structure on all sides of the external connection entity, semiconductor devices, it is installed to described installation and serves as a contrast
Bottom, the semiconductor devices includes quadrangle encapsulation, and quadrangle encapsulation includes the first side and the second side and also including the
Three sides and the 4th side, wherein first side and second side are opposite sides and are provided with electrical contact lead, wherein institute
It is opposite side to state the 3rd side and the 4th side, and wherein described 3rd side is provided with electrical contact lead, and wherein described
4th side is that, without lead side, and wherein described first side is to the molding side that the 3rd side is quadrangle encapsulation, and
4th side is the non-molding side limited by cutting surfaces of the quadrangle encapsulation, wherein, the semiconductor devices is connected
Be connected at least one quadrangle external connection entity, wherein the electrical contact lead of the 3rd side with it is described at least
On one side of external connection entity the electric contact structure electrical contact, and first side and second side institute
Electrical contact lead is stated to be made electrical contact with the electric contact structure being arranged on two of at least one external connection entity other sides.
Brief description of the drawings
One or more embodiments are only described by example referring now to accompanying drawing, wherein：
Fig. 1 is directed to the example of the general plotting of the encapsulation of semiconductor devices；
The example of the step of Fig. 2 to Fig. 4 is the method for manufacturing；And
Fig. 5 and Fig. 6 (including being designated as a) and two parts b)) it is the possible example for using.
It will be recognized that for the ease of representing, each accompanying drawing can not be what is be drawn in the same proportion.
Specific embodiment
In the following description, it is illustrated that one or more details, it is desirable to provide to the deep reason of the example of embodiment
Solution.Obtained in the case of one or more details that embodiment can in no detail, or utilize other
Method, part, material, etc. obtain.In other cases, not diagram or description known structure, material or operation in detail,
To cause that some aspects of embodiment will not will be made smudgy.
Reference to " embodiment " or " one embodiment " in the framework of this specification is intended to refer to be included at least one
The particular configuration relatively described with the embodiment, structure or characteristic in individual embodiment.Therefore, it can be present in this explanation
In a point in book or multiple points such as " in embodiment " or " in one embodiment " word be not necessarily referring to it is same
Individual embodiment.Additionally, can in any suitable manner combine specific conformation, structure or spy in one or more embodiments
Property.
Reference used herein is provided only for convenient and does not therefore limit the scope or embodiment of protection
Scope.
The semiconductor devices of such as integrated circuit is extensive technical field, including various types of substrates, device and dress
Put.
Such as United States Patent (USP) No.5,237,485A, No.7,256,479B2 and No.7,996,987B2 are (all by application
Be incorporated to) document be correlation technique example.Disclose and cause for producing to have for example, United States Patent (USP) No.7,996,987B2
Consumer can neatly select power model size without causing the common footprint of the cost being laid out again of system design
Family's power model system and method.
Fig. 1 is referred to now.One or more embodiments are included with the side 10a without lead (without lead)
The encapsulation of semiconductor devices (for example, integrated circuit), encapsulation 10 has conventional structure in other side.
One or more embodiments of such as " half flat package " HFP can be by that may be considered as in other side
The encapsulation that standard quadrilateral (for example, square or rectangle) encapsulates 100 (for example, with reference to the QFP of such as Fig. 1) is for example cut halfway
Cut to produce, therefore produce " without the lead " side for exempting electrical contact lead, it is such to include cutting encapsulation without lead side
Obtained from cutting surfaces.
Laser cutting LC is suitable for the technology of this cutting according to one or more embodiments.
In this way it is possible to obtain two different " partly " encapsulation 10 by single standard packaging (such as QFP 100) (can
Can be equal to each other).
Fig. 2 is the example of the design of lead frame (LF) 20.Standard leadframes manufacturing process (etching or punching press) and lead
Electric material (such as copper) can be used to produce such lead frame 20 in the case of without any modification.
In one or more embodiments, such lead frame can include two parts 20a, 20b, two parts
20a, 20b are relative to central plane A-A ' (or axles, it is assumed that lead frame 20 and resulting final semiconductor packages
In the case of global planarity) arranged on the opposite sides by (for example, specular).
In one or more embodiments, two parts 20a, 20b can include corresponding die pad welding zone or area
22a、22b。
In one or more embodiments, two parts 20a, 20b can be with (for example, in die pad welding zone 22a, 22b
Place) by means of for example extending across the intermediate space 26 between die pad welding zone 22a, 22b on axle A-A ' co-extensives
Bridge-type attachment structure 24 be linked mechanically each other.
In one or more embodiments, attachment structure 24 is (for example, the two of the opposite end of engagement die pad 22a, 22b
Individual structure) stability and rigidity of lead frame structure can be provided.
Fig. 2 to 4 shows in one or more embodiments in addition, " " center " lead, i.e., in the close envelope of lead frame 20
Lead at the region of dress center line (axle A-A ') can be omitted for example so as not to disturb cutting as described below.
Fig. 3 is the schematic example of (having for any of type of the purpose) die attached processing step,
By means of the die attached processing step：
- the first nude film 30a is placed on the die pad welding zone 22a of left side.
- the second nude film 30b is placed on the die pad welding zone 22b of right side.
In one or more embodiments, the second nude film 30b can have with the first nude film 30a identical types, in quilt
180 ° of rotation is placed on the die pad welding zone 22b of right side afterwards.
Certainly, to the reference of " first " and " second " nude film and " left side " and " right side " welding zone only for the purposes of explaining：
In one or more embodiments, the order/position of placement can be inverted relative to those of example.
Standard assemble flow (change/modification without types of equipment) can be used for forming lead, and it is more in one or Europe
Can include being formed for each part 20a, 20b of lead frame 20 in individual embodiment：
- along part 20a, 20b (more long here) side relative to each other first group of lead 201a, 201b；
- along each part 20a, 20b two lead 202a, 202b two groups of other (shorter here) sides relative and
203a、203b。
In one or more embodiments, can be formed along the side facing with each other of part 20a, 20b without lead, i.e.,
Limit the side in gap 26 in-between.
One or more embodiments can be included (the epoxy resin mould produced compounds EMC of any appropriate type, such as)
Encapsulation mold compound 28 is molded into lead frame 20 and is attached to nude film 30a, 30b upper (referring to Fig. 4) thereon.
In one or more embodiments, assemble flow can include for example being formed and encapsulation singualtion between in lead
Encapsulation cutting step.
In one or more embodiments, such cutting (for example, the laser cutting LC as illustrated in Fig. 1 schematically)
Can be carried out along the center line (axle A-A ') of encapsulation.
In one or more embodiments, such cutting can be on moulding unit (for example, solidifying it in mold compound
Carry out afterwards) so that be completely removed along the mold compound resin of laser path, and (for example, 24 only between die pad
Place) metal connection be maintained.
These connection 24 can after for example by encapsulate singulation step during for example by means of special bicker
The mechanical action that is such as punched cuts off.
Therefore one or more embodiments can cause production semiconductor devices 10 (for example, integrated circuit or IC), its bag
Include quadrangle encapsulation, quadrangle encapsulation include second pair of opposite side be provided with electric contact structure (for example, lead 202a,
202b, 203a, 203b) first pair of opposite side, wherein the only side of the second centering is provided with electric contact structure (for example, lead
201a, 201b), and remaining side (for example, the 10a in Fig. 1,5 and 6) does not have, that is, be not provided with any electric contact structure, therefore
It is without lead.In one or more embodiments, it is this to include cutting surfaces without lead side, for example it is not from encapsulation
Molded surface that molding process is obtained but cut (such as by mold compound by carrying out (such as laser) to molded package
Thing is cut) produce surface (it can for example be detected by checking surface) surface.
Consider the laser beam and the HFP square packages with the side that length is X of a diameter of " d ", two rectangles " partly " encapsulation
(HPG) obtained by cutting after, it has the size equal to (X/2-d/2) and X.
In addition it will be recognized that one or more embodiments are not in any way limited to be carried out by " complete " square package
Cut to produce rectangle " partly " to encapsulate.One or more embodiments can be actually resulted in for example by elongated " complete " rectangle
Encapsulation is cut to produce square " partly " to encapsulate.Therefore one or more embodiments can include being similar to by " complete "
Quadrangle (that is, four edges, square or rectangle) encapsulation cut to produce quadrangle " partly " encapsulation.
In one or more embodiments, such semiconductor devices can be produced by following operation：
- quadrangle lead frame (for example, 20) is provided, it includes in-between with mid-plane (such as A-A ') the
One leadframe portion (for example, 20a, 20b), wherein first leadframe portion and the second leadframe portion bag
The set (201a, 202a, 202b, 201b, 203a, 203b) by the way that lead will be made electrical contact with is included to provide in the quadrangle lead frame
Corresponding die pad welding zone (for example, 22a, 22b) on all sides of frame,
- the first semiconductor die and the second semiconductor die (for example, 30a, 30b) are arranged in first lead frame
On the corresponding die pad welding zone of part and second leadframe portion,
- (for example, 28) will be encapsulated be molded into first semiconductor die that is disposed thereon and described the second half
On the quadrangle lead frame of semiconductor die, and
- there is first semiconductor die and second semiconductor being disposed thereon along mid-plane cutting
The quadrangle lead frame of nude film, thus produces separate (paired) at the mid-plane as illustrated in hereinbefore
Semiconductor devices 10.
In one or more embodiments, the cutting can include laser cutting.
One or more embodiments can include：
- provided across the mid-plane in first leadframe portion and described the to the quadrangle lead frame
The coupled structure (for example, 24) that bridge-type extends between two leadframe portions；And
- (for example, by punching) cuts off the coupled structure to make the paired semiconductor device at the mid-plane
Part is separated.
In one or more embodiments, the mid-plane can be the mesion (example of the quadrangle lead frame
Such as, center line), alternatively wherein described first leadframe portion and second leadframe portion are relative to the centre
Plane specular.
In one or more embodiments, first semiconductor die and second semiconductor die can be identical
Nude film, on the corresponding die pad welding zone of first leadframe portion and second leadframe portion
It is arranged to 180 ° mutually rotating.
Fig. 5 and Fig. 6 show or many for example in terms of external connection entity (ECU) standard by way of comparing
The flexibility of individual embodiment.
The left part being appointed as in Fig. 5 and Fig. 6 a) illustrates conventional arrangement, wherein two of such as certain semiconductor devices
(for example, it may be possible to provide two integrated circuits of identical function in electric vehicle, its difference is such as size to different editions
And/or quantity and/or computing capability the level aspect of interface) by using on 100 (for example, QFP) of " complete " encapsulation
Different types of (special) external connection entity (referred to as ECU) (for example, one kind of a kind of ECU1 of " larger " and " smaller "
ECU2) be accommodated on substrate (for example, printed circuit board (PCB)) PCB, it is larger and it is less be installed in it is two distinct types of
Special external is connected physically.
The right part being appointed as in Fig. 5 and Fig. 6 b) illustrates the increased flexibility provided by one or more embodiments.
For example, the part b) of Fig. 5 shows to show to connect in a) of part and with for example two distinct types of outside
The identical PCB for meeting entity ECU1 and ECU2 can be used for connecting the encapsulation 100 of larger " complete " installed in larger outside
In meeting entity ECU1, and less external connection entity ECU2 can be used for installation " partly " flat package 10 as being exemplified above,
Each " partly " flat package 10 is the version of the further diminution that the complete package 100 at ECU2 is arranged in routinely arrangement.
For example, the part b) of Fig. 6 shows that the PCB of the external connection entity (such as ECU1) including single type can be used
" complete " encapsulation 100 of larger type is installed at for example in these entities, and is remained as outside its of ECU1 types
Portion's connection entity can be used for installing " partly " flat package 10, and each is complete package 100 " partly " size version.
One or more embodiments hence in so that single ECU board can be designed for into different application races, with supplying
Answer the reduction of ECU costs therefore at business end, it may be possible to provide the easy interchangeability of different product/be encapsulated on identical ECU board.
The right part of Fig. 5 and Fig. 6 is the side of the use semiconductor devices as illustrated in in the method for comprising the following steps
The illustration of method or one or more embodiments：
- provide and substrate (such as PCB) is installed, it is provided with least one quadrangle external connection entity, on four side
There is electric contact structure on all sides of shape external connection entity：ECU1, ECU2 are see, for example, it is entirely to be connect with four groups of electricity
(such as square) of the quadrangle of structure is touched, for one group of every side of quadrangle form,
- " half is flat " semiconductor devices 10 is installed at least one quadrangle external connection physically, wherein half
Conductor device 10 with the electric contact structure electricity on the side for having without the relative side in lead side with the external connection entity
Contact its electrical contact lead (for example, with reference to 201a, the 201b in Fig. 4), and first pair of opposite side have and set
Put on two of the external connection entity other sides electric contact structure electrical contact their electrical contact lead (for example,
Referring to 202a, 202b, 203a, the 203b in Fig. 4).
The example of the right part of Fig. 5 and Fig. 6 or electronic installation in electric vehicle (for example, for for example using
Processor or controller)：
- substrate is installed, it is provided with least one quadrangle external connection entity (for example, ECU1, ECU2), described outer
There is electric contact structure on all sides of portion's connection entity,
- semiconductor devices 10, as illustrated in above, it is installed at least one quadrangle external connection reality
On body (for example, ECU1, ECU2), wherein semiconductor devices has and the external connection reality with without the relative side in lead side
Its electrical contact lead (for example, with reference to 201a, the 201b in Fig. 4) of the electric contact structure electrical contact on the side of body, and
First pair of opposite side has and the electric contact structure electrical contact being arranged on two of the external connection entity other sides
Their electrical contact lead (for example, with reference to 202a, 202b, 203a, the 203b in Fig. 4).
The similar example of Fig. 5 and the right part of Fig. 6 still (for example, as considered above) electronic installation, its
Middle installation substrate (such as PCB) is provided with least one other quadrangle external connection entity, in the external connection entity
(ECU1) there is electric contact structure, wherein other " complete " semiconductor devices 100 (has on all its sides on all sides
Have electrical contact lead) made electrical contact with the electric contact structure on all sides of the external connection entity：See, for example, Fig. 5's
Two semiconductor devices 100 on the left side of part b) or Fig. 6 part b) the upper left corner semiconductor devices 100.
In the case where potential principle is not influenceed, details and embodiment can be in the case of the scopes for not departing from protection
Even significantly change relative to the details and embodiment for only having been described by example.
The scope of protection is limited by appended claims.
Claims (13)
1. a kind of semiconductor devices, including：
Quadrangle is encapsulated, including the first side and the second side and also including the 3rd side and the 4th side, wherein first side and institute
Stating the second side is opposite side and is provided with electrical contact lead, wherein the 3rd side and the 4th side are opposite sides, and
And wherein described 3rd side is provided with electrical contact lead, and wherein described 4th side is without lead side and wherein described
Side is to the molding side that the 3rd side is quadrangle encapsulation, and the 4th side is the quadrangle encapsulation by cutting
Cut the non-molding side of surface restriction.
2. semiconductor devices according to claim 1, also including the lead frame being encapsulated in the quadrangle encapsulation,
The lead frame is included in being longitudinally extended parallel to the 4th side in the lead frame at the 4th side
Gap.
3. semiconductor devices according to claim 2, wherein the lead frame is additionally included in the opposite end in the gap
The bridging device capable of being connected part cut off by the cutting surfaces at place.
4. a kind of semiconductor devices, including：
Lead frame, including the first die pad and the second die pad, first die pad and second nude film are welded
Disk is connected by the bridging device capable of being connected part in the opposite end of the intermediate space being longitudinally extended；
First IC chip, is installed to first die pad；
Second IC chip, is installed to second die pad；
Quadrangle is encapsulated, and the lead frame, first IC chip and second IC chip are carried out
Encapsulate and including the first side and the second side and also including the 3rd side and the 4th side, wherein first side and second side
It is opposite side, first side includes being coupled to the first electrical contact lead of first IC chip and is coupled to described
Second electrical contact lead of the second IC chip, second side includes being coupled to the of first IC chip
Three electrical contact leads and the 4th electrical contact lead of second IC chip is coupled to, wherein the 3rd side and described
4th side is opposite side, and the 3rd side includes being coupled to the 5th electrical contact lead of first IC chip, described
4th side includes being coupled to the 6th electrical contact lead of second IC chip；
The intermediate space of wherein described Longitudinal extending be configured as supporting by quadrangle encapsulation cut into the first half encapsulation and
The second half encapsulation, wherein the first half encapsulation includes first die pad, the first IC chip and described first
Electrical contact lead, the 3rd electrical contact lead and the 5th electrical contact lead, and the second half encapsulation include it is described
Second die pad, the second IC chip and the second electrical contact lead, the 4th electrical contact lead and described the
Six electrical contact leads.
5. a kind of method for producing semiconductor devices, including：
Quadrangle lead frame is provided, the quadrangle lead frame includes the first lead frame with mid-plane in-between
Frame part and the second leadframe portion, wherein first leadframe portion and second leadframe portion include phase
The die pad welding zone answered, wherein the set of electrical contact lead is arranged on all sides of the quadrangle lead frame,
First semiconductor die and the second semiconductor die are arranged in first leadframe portion and second lead
On the corresponding die pad welding zone of frame part,
To encapsulate and be molded into described in first semiconductor die and second semiconductor die being disposed thereon
On quadrangle lead frame, and
There is first semiconductor die and second semiconductor die being disposed thereon along mid-plane cutting
And the quadrangle lead frame of the molding encapsulation thereon, thus produce at the mid-plane it is separate into
To semiconductor devices.
6. method according to claim 5, wherein the cutting includes being cut by laser.
7. method according to claim 5, including：
There is provided to the quadrangle lead frame and extended to across the mid-plane in first leadframe portion and institute
State the coupled structure of the bridge between the second leadframe portion；And
Wherein cutting includes the cut-out coupled structure to be divided into the paired semiconductor devices at the mid-plane.
8. method according to claim 5, wherein the mid-plane is the mid-plane of the quadrangle lead frame,
Wherein described first leadframe portion and second leadframe portion are relative to the mid-plane specular.
9. method according to claim 5, wherein first semiconductor die and second semiconductor die are phases
Same nude film, in first leadframe portion and the corresponding die pad welding zone of second leadframe portion
On be arranged to 180 ° mutually rotating.
10. method according to claim 5, including：
The intermediate space of the Longitudinal extending alignd with the mid-plane is provided to the quadrangle lead frame；And
Wherein cutting includes cutting off the intermediate space of the Longitudinal extending.
A kind of 11. methods, including：
Semiconductor devices is installed to installation substrate, the installation substrate is provided with least one quadrangle external connection entity,
There is electric contact structure on all sides of the quadrangle external connection entity,
Wherein described semiconductor devices is encapsulated including quadrangle, and the quadrangle encapsulation includes the first side and the second side and also bag
The 3rd side and the 4th side are included, wherein first side and second side are opposite sides and are provided with electrical contact lead, its
Described in the 3rd side and the 4th side be opposite side, and wherein described 3rd side is provided with electrical contact lead, and wherein
4th side is that, without lead side, and wherein described first side is to the molding side that the 3rd side is quadrangle encapsulation,
And the 4th side is the non-molding side limited by cutting surfaces of the quadrangle encapsulation,
The semiconductor devices is connected at least one quadrangle external connection entity, wherein the 3rd side is described
Electrical contact lead and the electric contact structure electrical contact on the side of at least one external connection entity, and it is described
The electrical contact lead of the first side and second side be arranged on two of at least one external connection entity other
Electric contact structure electrical contact on side.
A kind of 12. electronic installations, including：
Substrate, including at least one quadrangle external connection entity are installed, are had on all sides of the external connection entity
Electric contact structure,
Semiconductor devices, is installed to the installation substrate, and the semiconductor devices is encapsulated including quadrangle, the quadrangle envelope
Dress includes the first side and the second side and also including the 3rd side and the 4th side, wherein first side and second side are relative
Side and electrical contact lead is provided with, wherein the 3rd side and the 4th side are opposite sides, and the wherein described 3rd
Side is provided with electrical contact lead, and wherein described 4th side is that, without lead side, and wherein described first side is to the described 3rd
Side is the molding side of quadrangle encapsulation, and the 4th side be the quadrangle encapsulation by cutting surfaces limit it is non-
Molding side,
Wherein, the semiconductor devices is connected at least one quadrangle external connection entity, wherein the 3rd side
The electrical contact lead with the side of at least one external connection entity the electric contact structure electrical contact, and
And the electrical contact lead of first side and second side be arranged on the two of at least one external connection entity
Electric contact structure electrical contact on individual other sides.
13. electronic installations according to claim 12, wherein the installation substrate also includes at least one four other sides
Shape external connection entity, has electric contact structure on all sides of described at least one other external connection entity, and
Also include：
Other semiconductor devices, it has all sides of the external connection entity other with described at least one on all sides
On the electric contact structure electrical contact electrical contact lead.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| IT102015000073934 | 2015-11-18 | ||
| ITUB2015A005696A ITUB20155696A1 (en) | 2015-11-18 | 2015-11-18 | SEMICONDUCTOR DEVICE, CORRESPONDING PRODUCTION PROCEDURES AND USE AND CORRESPONDING EQUIPMENT |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN106711102A true CN106711102A (en) | 2017-05-24 |
| CN106711102B CN106711102B (en) | 2019-09-06 |
Family
ID=55410122
Family Applications (2)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621102365.6U Withdrawn - After Issue CN206059373U (en) | 2015-11-18 | 2016-09-30 | Semiconductor device and electronic installation |
| CN201610877351.XA Active CN106711102B (en) | 2015-11-18 | 2016-09-30 | Semiconductor devices, corresponding production and the method used and corresponding device |
Family Applications Before (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201621102365.6U Withdrawn - After Issue CN206059373U (en) | 2015-11-18 | 2016-09-30 | Semiconductor device and electronic installation |
Country Status (3)
| Country | Link |
|---|---|
| US (2) | US9698087B2 (en) |
| CN (2) | CN206059373U (en) |
| IT (1) | ITUB20155696A1 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| ITUB20155696A1 (en) * | 2015-11-18 | 2017-05-18 | St Microelectronics Srl | SEMICONDUCTOR DEVICE, CORRESPONDING PRODUCTION PROCEDURES AND USE AND CORRESPONDING EQUIPMENT |
| US10896869B2 (en) | 2018-01-12 | 2021-01-19 | Amkor Technology Singapore Holding Pte. Ltd. | Method of manufacturing a semiconductor device |
| US11611170B2 (en) | 2021-03-23 | 2023-03-21 | Amkor Technology Singapore Holding Pte. Ltd | Semiconductor devices having exposed clip top sides and methods of manufacturing semiconductor devices |
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| US5587883A (en) * | 1992-12-03 | 1996-12-24 | Motorola, Inc. | Lead frame assembly for surface mount integrated circuit power package |
| US20060223238A1 (en) * | 2004-03-30 | 2006-10-05 | Koh Kwang W | Leadless semiconductor package and manufacturing method thereof |
| CN102117753A (en) * | 2010-01-05 | 2011-07-06 | 飞思卡尔半导体公司 | Method for packaging semiconductor device |
| CN206059373U (en) * | 2015-11-18 | 2017-03-29 | 意法半导体股份有限公司 | Semiconductor device and electronic installation |
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| US5237485A (en) | 1985-04-26 | 1993-08-17 | Sgs Microelettronica S.P.A. | Apparatus and method for improved thermal coupling of a semiconductor package to a cooling plate and increased electrical coupling of package leads on more than one side of the package to a circuit board |
| CN1659698A (en) * | 2002-06-06 | 2005-08-24 | 皇家飞利浦电子股份有限公司 | Quad flat non-leaded package comprising a semiconductor device |
| US7256479B2 (en) | 2005-01-13 | 2007-08-14 | Fairchild Semiconductor Corporation | Method to manufacture a universal footprint for a package with exposed chip |
| US7996987B2 (en) | 2006-10-17 | 2011-08-16 | Broadcom Corporation | Single footprint family of integrated power modules |
| WO2009036604A1 (en) * | 2007-09-20 | 2009-03-26 | Asat Limited | Etching isolation of lpcc/qfn strip |
| US8329509B2 (en) * | 2010-04-01 | 2012-12-11 | Freescale Semiconductor, Inc. | Packaging process to create wettable lead flank during board assembly |
| US8163601B2 (en) | 2010-05-24 | 2012-04-24 | Alpha & Omega Semiconductor, Inc. | Chip-exposed semiconductor device and its packaging method |
| JP5618873B2 (en) * | 2011-03-15 | 2014-11-05 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| JP5959386B2 (en) * | 2012-09-24 | 2016-08-02 | エスアイアイ・セミコンダクタ株式会社 | Resin-sealed semiconductor device and manufacturing method thereof |
| JP6143468B2 (en) * | 2013-01-11 | 2017-06-07 | 株式会社三井ハイテック | Lead frame |
| JP6129671B2 (en) * | 2013-07-19 | 2017-05-17 | ルネサスエレクトロニクス株式会社 | Manufacturing method of semiconductor device |
| JP2015060876A (en) * | 2013-09-17 | 2015-03-30 | ルネサスエレクトロニクス株式会社 | Method of manufacturing semiconductor device |
-
2015
- 2015-11-18 IT ITUB2015A005696A patent/ITUB20155696A1/en unknown
-
2016
- 2016-05-23 US US15/161,617 patent/US9698087B2/en active Active
- 2016-09-30 CN CN201621102365.6U patent/CN206059373U/en not_active Withdrawn - After Issue
- 2016-09-30 CN CN201610877351.XA patent/CN106711102B/en active Active
-
2017
- 2017-01-26 US US15/416,546 patent/US9893001B2/en active Active
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| US5587883A (en) * | 1992-12-03 | 1996-12-24 | Motorola, Inc. | Lead frame assembly for surface mount integrated circuit power package |
| US20060223238A1 (en) * | 2004-03-30 | 2006-10-05 | Koh Kwang W | Leadless semiconductor package and manufacturing method thereof |
| CN102117753A (en) * | 2010-01-05 | 2011-07-06 | 飞思卡尔半导体公司 | Method for packaging semiconductor device |
| CN206059373U (en) * | 2015-11-18 | 2017-03-29 | 意法半导体股份有限公司 | Semiconductor device and electronic installation |
Also Published As
| Publication number | Publication date |
|---|---|
| CN206059373U (en) | 2017-03-29 |
| US20170140944A1 (en) | 2017-05-18 |
| US9698087B2 (en) | 2017-07-04 |
| US20170141019A1 (en) | 2017-05-18 |
| CN106711102B (en) | 2019-09-06 |
| US9893001B2 (en) | 2018-02-13 |
| ITUB20155696A1 (en) | 2017-05-18 |
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