CN106682268B - Programmable logic device configuration method and equipment - Google Patents
Programmable logic device configuration method and equipment Download PDFInfo
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Abstract
The embodiment of the invention discloses a configuration method and equipment of a programmable logic device, which are used for realizing design files by generating a PLD (programmable logic device) model file containing a device model and an operator model and a PLD (programmable logic device); mapping a target function module and a connection relation in a design file of a PLD (programmable logic device) to the top layer of a device model in the PLD model file, and configuring a corresponding grid point element on the top layer; traversing and extracting configuration parameters of each lattice point element on the top layer to generate a configuration file; and writing the configuration file into the PLD to be configured. The method can realize the precise configuration process of the PLD, and is beneficial to the development and the test of designers on the PLD. The invention can configure the basic elements forming the PLD, thereby realizing the maximization of the resource utilization of the PLD chip, and simultaneously, flexibly setting the internal structure of the lattice point elements and the connection relation among the lattice point elements, and effectively solving the problem of accurate control of the critical path.
Description
Technical Field
The invention relates to the technical field of digital electronics, in particular to a programmable logic device configuration method and equipment.
Background
A Programmable Logic Device (PLD) is an electronic Device that can change its Logic function at any time according to actual needs. PLDs are generally classified into Programmable Read Only Memories (PROMs), erasable Programmable memories (EPROMs), Programmable Logic Arrays (PLAs), Programmable Array Logics (PALs), General Array Logics (GALs), Field Programmable Gate Arrays (FPGAs), Complex Programmable Logic Devices (CPLDs), and the like.
In the field of digital electronics, the circuitry of fixed logic devices is permanent and cannot be changed once manufactured, and can only perform a corresponding logic function or group of logic functions. The PLD has high flexibility, and the logic function of the PLD can be changed at any time according to actual requirements in the design process by a programming method, so that more choices are provided for users and designers; meanwhile, in the design process, designers only need to use a cheap software tool to develop, simulate and debug the design of the PLD, and can realize different logic functions without changing the physical structure of the PLD, so that the cost input of the designers and manufacturers in the design and development process is greatly reduced, and the PLD is widely applied.
In the prior art, configuration and debugging processes of PLDs are various, and usually a Design logic is described using a hardware Description Language such as Verilog HDL (Verilog hardware Description Language), VHDL (Very-High-Speed-Integrated circuit hardware Description Language), and then a configuration file is generated by using an EDA (electronic Design Automation) tool through steps such as automatic layout and routing, and then the configuration file is downloaded to the PLD for debugging. However, due to the limitation of the placement and routing algorithm, the above method cannot achieve the maximum utilization of PLD resources, and cannot achieve precise control of critical paths, which may cause a problem that the above method cannot be applied in some special situations.
Disclosure of Invention
The invention provides a programmable logic device configuration method and equipment, which are used for solving the problems that the conventional PLD configuration method cannot realize accurate control on a critical path and achieves higher PLD resource utilization rate.
To this end, an embodiment of the present invention provides a method for configuring a programmable logic device, including:
generating a programmable logic device model file, wherein the programmable logic device model file comprises a device model and an operator model; the device model comprises basic elements of the programmable logic device at the bottom layer, lattice point elements at the middle layer and a lattice point system at the top layer, wherein the lattice point elements consist of at least one basic element, and the lattice point system consists of at least one lattice point element; the operator model comprises functional modules for realizing all functions, and one functional module is realized by connecting and combining basic elements in the lattice point elements;
selecting a corresponding target function module from the operator model according to the function of the programmable logic device to be configured, and determining the connection relation among the target function modules to generate a programmable logic device implementation design file;
mapping a target function module and a connection relation in the programmable logic device implementation design file to the top layer of a device model in the programmable logic device model file, and configuring a corresponding lattice point element on the top layer;
traversing and extracting configuration parameters of each lattice point element on the top layer to generate a configuration file;
and writing the configuration file into the programmable logic device to be configured.
Further, the device model includes identification information for uniquely identifying the device model, function parameter configuration information of the implemented function, and corresponding interface information;
the lattice element includes configuration description information describing a position, graphic description information performing graphic representation, and structure description information describing an internal structure.
Further, the functional module includes module identification information for uniquely identifying the functional module, parameter configuration information of the implemented function, corresponding interface information, and description information of all implementation manners for implementing the functional module.
Further, the generating a programmable logic device implementation design file includes:
determining and defining each input/output interface according to the connection relation;
for each target function module, generating an internal implementation description statement describing each target function module to obtain a target function module example;
and generating description sentences of each routing path according to the connection relation, and identifying and constraining the key routing paths to obtain a network cable example.
Further, mapping the target function module and the connection relation in the programmable logic device implementation design file to the top layer, and configuring the corresponding lattice point element on the top layer includes:
sequentially compiling the device model from the bottom layer to the top layer to obtain a top layer grid model of the device model, storing the top layer grid model in a model compiling library, and compiling and storing each functional module in the operator model in the model compiling library;
compiling the programmable logic device implementation design file to obtain a target function module example and a network cable example;
finding out respective corresponding functional modules from the model compiling library according to the target functional module examples, and configuring the corresponding functional modules according to the parameters of the target functional module examples to obtain parameter configuration functional modules;
and mapping each parameter configuration function module to a grid corresponding to the top grid model according to the network cable example and the implementation mode of each parameter configuration function module, and configuring grid elements on the corresponding grid according to the parameters of each parameter configuration function module.
An embodiment of the present invention further provides a programmable logic device configuration apparatus, including:
the model generation module is used for generating a programmable logic device model file, and the programmable logic device model file comprises a device model and an operator model; the device model comprises basic elements of the programmable logic device at the bottom layer, lattice point elements at the middle layer and a lattice point system at the top layer, wherein the lattice point elements consist of at least one basic element, and the lattice point system consists of at least one lattice point element; the operator model comprises functional modules for realizing all functions, and one functional module is realized by connecting and combining basic elements in the lattice point elements;
the design generation module is used for selecting a corresponding target function module from the operator model according to the function of the programmable logic device to be configured, and determining the connection relation among the target function modules to generate a programmable logic device implementation design file in a Valence language format;
the processing module is used for mapping the target function module and the connection relation in the programmable logic device implementation design file to the top layer of the device model in the programmable logic device model file and configuring the corresponding lattice point element on the top layer; and the configuration file is also used for traversing and extracting the configuration parameters of each lattice point element on the top layer to generate a configuration file, and writing the configuration file into the programmable logic device to be configured.
Further, the device model includes identification information for uniquely identifying the device model, function parameter configuration information of the implemented function, and corresponding interface information;
the lattice element includes configuration description information describing a position, graphic description information performing graphic representation, and structure description information describing an internal structure.
Further, the functional module includes module identification information for uniquely identifying the functional module, parameter configuration information of the implemented function, corresponding interface information, and description information of all implementation manners for implementing the functional module.
Further, the design generation module is configured to determine and define each input/output interface according to the connection relationship, generate, for each target function module, an internal implementation description statement describing each target function module to obtain a target function module example, generate a description statement describing each routing path according to the connection relationship, and perform identification constraint on a key routing path to obtain a network cable example.
Further, the processing module comprises:
the compiling submodule is used for compiling the device models from the bottom layer to the top layer in sequence to obtain top layer grid models of the device models and storing the top layer grid models in a model compiling library, and compiling and storing each functional module in the operator models in the model compiling library; the programmable logic device is also used for compiling the programmable logic device implementation design file to obtain a target function module example and a network cable example;
the mapping submodule is used for finding out the corresponding functional module from the model compiling library according to the target functional module example and configuring the corresponding functional module according to the parameter of each target functional module example to obtain a parameter configuration functional module; and mapping each parameter configuration function module to a grid corresponding to the top grid model according to the network cable example and the implementation mode of each parameter configuration function module, and configuring grid elements on the corresponding grid according to the parameters of each parameter configuration function module.
Advantageous effects
According to the method and the equipment for configuring the programmable logic device, provided by the embodiment of the invention, a Programmable Logic Device (PLD) model file containing a device model and an operator model is generated; the device model comprises PLD basic elements at a bottom layer, lattice point elements at a middle layer and a lattice point system at a top layer, wherein the lattice point elements consist of at least one basic element, and the lattice point system consists of at least one lattice point element; the operator model comprises functional modules for realizing all functions, and one functional module is realized by connecting and combining basic elements in the lattice point elements; selecting a corresponding target function module from the operator model according to the function to be realized by the PLD to be configured, and determining the connection relation among the target function modules to generate a PLD realization design file in a Valence language format; mapping the target function module and the connection relation in the PLD implementation design file to the top layer of a device model in the PLD model file, and configuring the corresponding grid point element on the top layer; traversing and extracting configuration parameters of each lattice point element on the top layer to generate a configuration file; and writing the configuration file into the PLD to be configured. The invention can realize the configuration of the basic elements forming the PLD, thereby realizing the maximization of the resource utilization of the PLD chip, and simultaneously, can flexibly set the internal structure of the lattice point elements and the connection relation among the lattice point elements, thereby being beneficial to the development and the test of the PLD by designers and promoting the development of the PLD technology.
Drawings
Fig. 1 is a schematic flowchart of a PLD configuration method according to an embodiment of the invention;
fig. 2 is a schematic structural diagram of a lattice system in a device model according to an embodiment of the present invention;
FIG. 3 is a schematic diagram illustrating the composition of a PLD implementation design file according to an embodiment of the invention;
fig. 4 is a schematic flowchart of a mapping configuration method of a PLD device model according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of a configuration device of a programmable logic device according to a second embodiment of the present invention;
fig. 6 is a schematic structural diagram of another configuration device for a programmable logic device according to a second embodiment of the present invention.
Detailed Description
The following describes embodiments of the present invention in further detail with reference to the accompanying drawings.
The first embodiment is as follows:
the embodiment of the invention provides a method for realizing a configuration process of a programmable logic device based on a Valence language, so as to achieve the purpose of configuring and debugging a PLD, and the configuration process is efficient, convenient and fast, thereby being beneficial to development and test of a design personnel on the logic function of the PLD and promoting the development of a PLD technology.
Referring to fig. 1, fig. 1 is a schematic flow chart of a PLD configuration method according to an embodiment of the present invention, including:
s11: generating a PLD model file, wherein the PLD model file comprises a device model and an operator model; the device model comprises PLD basic elements at a bottom layer, lattice point elements at a middle layer and a lattice point system at a top layer, wherein the lattice point elements consist of at least one basic element, and the lattice point system consists of at least one lattice point element; the operator model comprises functional modules for realizing all functions, and one functional module is realized by connecting and combining the basic elements in the lattice point elements.
And modeling the PLD to be configured by generating a PLD model file, wherein the PLD model file generated by modeling comprises a device model. The Device model includes PLD basic elements (which may be referred to as Prim devices) in the bottom layer, lattice elements (which may be referred to as Grid devices) in the middle layer, and a lattice system (which may be referred to as architecture devices) in the top layer. The basic elements of the bottom layer are abstract minimum working units, the lattice point elements of the middle layer are composed of 1 or at least two basic elements, and when at least two basic elements exist in one lattice point element, all the basic elements can be different, part of the basic elements can be different, and all the basic elements can be the same. The composition and/or number of the basic elements in the lattice element can be flexibly set in particular according to the logic function of the PLD to be configured. The lattice point system at the top layer is formed by arranging the lattice point elements according to a certain rule. The lattice system consists of at least one lattice element, usually of a plurality of lattice elements, which may be, for example, tens, hundreds or even thousands of lattice elements on a large scale. For better understanding of the present invention, please refer to fig. 2, and fig. 2 is a schematic structural diagram of a lattice point system in a device model according to an embodiment of the present invention. Comprising a grid system of the top layer, grid elements of the middle layer and elementary elements of the bottom layer. The lattice point system is composed of a plurality of regularly arranged lattice point elements, each lattice point element is composed of at least one basic element, and the basic elements in each lattice point element can be the same or different.
The generated device model should also include identification information uniquely identifying the device model, function parameter configuration information of the implemented function, and corresponding interface information. It should be understood that the identification information uniquely identifying the device model may be the name of the model device; the configuration information of the functional parameters may be specifically set according to the logic function implemented by the PLD to be configured.
In generating the device model, the functional structure of each component for generating the PLD device model to be configured should be described, so as to form a complete device model. Each model individual may be referred to as a component (Device), and in particular may be a base element, a grid element, and a grid system, which may be referred to as a component. The component should include a name of a corresponding component, interface information, and configuration parameters, where the name of the component can be used as unique identification information of the component, the interface is mainly used for signal connection, and the configuration parameters determine specific functions implemented by the component.
In this embodiment, the description language of the above structure format (for example, PLD model file or PLD implementation design file) is referred to as Valence language.
The description of each component based on the Valence language can be performed from multiple aspects, including a structural description (Structure View), a Configuration description (Configuration View), and a graphical description (schema View). The structural description is used for defining the internal structure of the assembly, for example, a lattice point element is formed by combining and connecting a plurality of basic elements, and the configuration parameter value of each basic element and the connection relation between the basic elements are defined in the structural description. It should be understood that since the basic elements are the smallest basic units of abstraction, there is no structural description of the basic elements. Configuration description is used for defining configuration points (Config bits, which correspond to physical switches in the PLD device one-to-one) and configuration values (Config values) of the components, and since the arrangement of the lattice elements in the top-level lattice system is regular, all the Config bits can be completely planned in the lattice elements, so that the position of a certain Config Bit in the whole PLD device can be conveniently located. The graphic description is used for defining the graphics of the assembly, and is mainly used for drawing.
For example, the lattice element is described from the above three aspects, so as to obtain the lattice element including configuration description information describing a position, graphic description information performing graphic representation, and structure description information describing an internal structure. The configuration description information includes specific coordinate values of the lattice point element, which may be expressed as: (a, 1, 4), wherein "a" indicates that the lattice element belongs to lattice system a, and "1, 4" indicates that the specific position of the lattice element in lattice system a is in row 1, column 4. The graphic description information includes a graphic for representing the lattice point element, and the graphic can be specifically set based on the logic function to be realized by the lattice point element. The structure description information is used to describe the internal structure of the lattice element, and specifically, what basic elements the lattice element is composed of and the connection relationship between the basic elements.
When a PLD device to be configured is modeled through a Valence language, the PLD model file also contains an operator model, the operator model contains functional modules (namely operators) for realizing all functions, one functional module is realized by connecting and combining basic elements in lattice point elements, and different basic elements can form different functional modules through different connecting modes to realize different logic functions. Specifically, the functional module includes, but is not limited to, an adder, a multiplier, a comparator, a flip-flop, and the like, and may be referred to as a functional module.
The functional module comprises module identification information for uniquely identifying the functional module, parameter configuration information of the realized function, corresponding interface information and description information of all realization modes for realizing the functional module. It should be noted that the specific function of a functional module is not unique in implementation, and there may be many different implementations, and some of them may be reasonably selected in the subsequent configuration process based on the actual use scenario.
S12: and selecting a corresponding target function module from the operator model according to the function of the PLD to be configured, and determining the connection relation among the target function modules to generate a PLD implementation design file in a Valence language format.
Specifically, each input/output interface may be determined according to a connection relationship of each target function module; for each target function module, generating an internal implementation description sentence for describing each target function module; and generating description sentences of the routing paths according to the connection relation of the target function modules, and identifying and constraining the key routing paths. Finally, a PLD implementation design file in the Valence language format is generated.
For better understanding of the present invention, please refer to fig. 3, and fig. 3 is a schematic diagram illustrating a PLD implementation design file according to an embodiment of the present invention. The PLD implementation design file mainly comprises three statement blocks: interface definition statement block, internal realization statement block and routing path definition statement block.
The interface definition statement block comprises a description statement used for defining a design name and defining related parameters of the design, and an input/output interface statement; the input/output port can be simply understood as the input and output of the module in the Verilog language, and the main role of the input/output port is the interaction between the PLD device and external signals, such as clock signals input into the PLD device. The internal implementation statement block includes an internal structure description statement of the design, and specifically, instantiates and connects a specific function module to implement a corresponding function. When writing the internal structure, not only the existing functional module may be used, but also a special functional module may be designed according to actual requirements, and even the lattice element or the basic element may be directly configured and connected, for example, the position of the functional module and/or the component in the whole PLD to be configured may be directly specified, and the position of the used functional module and/or the component may be specifically constrained by coordinates of each lattice point in the lattice point system.
The trace path definition statement block includes description statements of each trace path, and is used for identifying and constraining the critical trace path of the PLD, so as to realize accurate control of the critical trace path. The key routing path in this embodiment may be any network cable (a network cable may be understood as a wire in Verilog language, and is used to connect ports of two functional modules to implement data transmission), ports of the functional modules connected to two ends of one network cable are determined in an internal structure description statement, a routing path definition statement only restricts a path of the key network cable, and a network cable that is not restricted may be routed by using a routing algorithm during subsequent processing. For example, when writing, firstly, a net wire is constrained by using a wiring constraint keyword identifier, then each node of the net wire from a starting point to an end point is connected by using a connection symbol according to the front-back sequence, and finally, the writing is finished by a semicolon.
S13: and mapping the target function module and the connection relation in the design file of the PLD to the top layer of the device model in the PLD model file, and configuring the corresponding grid point element on the top layer.
After the PLD model file in the value language format and the PLD implementation design file are written and generated, the configuration of the PLD device model can be realized by reading the target function module, the mutual connection relationship, and the top layer model in the device model, and mapping the target function module and the connection relationship in the PLD implementation design file to the top layer of the device model in the PLD model file.
For better understanding of the present invention, the following detailed description of the mapping and configuration process of the PLD device model refers to fig. 4, and fig. 4 is a schematic flow chart of a mapping configuration method of the PLD device model according to an embodiment of the present invention, including:
s131: compiling the PLD model file, and storing the compiling result in a model compiling library.
Because the PLD model file comprises the device model and the operator model, the top grid model of the device model can be obtained after the device model is compiled, and can be stored in a model compiling library; for the operator model, functional modules in the operator model can be compiled and stored in a model compiling library.
S132: and compiling the design file of the PLD to obtain a target function module example and a network cable example.
When the PLD implementation design file is compiled, a target function module example is obtained based on internal implementation description sentences for describing each target function module, a network cable example is generated according to the connection relation among the function modules, and the key path is constrained according to the routing path description sentences. The target function module instance and the network cable instance obtained by compiling the PLD implementation design file can be stored in a Work library (Work Lib). The network cable example has unique identification of each target function module example connected with the network cable example, and the network cable example which is restrained by using the routing path definition statement block also stores the specific routing path.
S133: and finding out the corresponding functional module from the model compiling library according to the target functional module example, and configuring the corresponding functional module according to the parameter of each target functional module example to obtain a parameter configuration functional module.
S134: and mapping each parameter configuration function module to a grid corresponding to the top grid model according to the network cable example and the implementation mode of each parameter configuration function module, and configuring grid elements on the corresponding grid according to the parameters of each parameter configuration function module.
And taking out the network cable example in the working library, taking out the top grid model of the PLD device from the model compiling library, mapping each parameter configuration function module to a specific grid point corresponding to the top grid model, and configuring the current grid point element according to the configuration parameters of each current parameter configuration function module. And according to the extracted network cable example, allocating an appropriate routing path for each network cable by using a routing algorithm. And for the specific defined routing path, wiring is carried out according to the routing path.
The specific implementation mode of each parameter configuration functional module can be manually written into a PLD implementation design file or can be automatically selected through compiling software.
S14: and traversing and extracting the configuration parameters of each lattice point element on the top layer to generate a configuration file.
And finally, reading the configuration information and writing the configuration information into a file by traversing each lattice element in the top lattice element system of the PLD, and generating the configuration file of the PLD after the configuration of all lattice elements is finished.
S15: and writing the configuration file into the PLD to be configured.
After the configuration file of the PLD is generated, the configuration file can be written into the PLD to be configured through writing software. After writing, the operation test can be carried out to verify whether the logic function and the stability condition to be realized are achieved. If the expected effect is not achieved, the method can be achieved by modifying the corresponding program file, and is convenient and quick without investing higher design cost.
The embodiment of the invention provides a configuration method of a programmable logic device, which comprises the steps of generating a PLD model file containing a device model and an operator model in a Valence language format; the device model comprises PLD basic elements at a bottom layer, lattice point elements at a middle layer and a lattice point system at a top layer, wherein the lattice point elements consist of at least one basic element, and the lattice point system consists of at least one lattice point element; the operator model comprises functional modules for realizing all functions, and one functional module is realized by connecting and combining basic elements in the lattice point elements; selecting a corresponding target function module from the operator model according to the function to be realized by the PLD to be configured, and determining the connection relation among the target function modules to generate a PLD realization design file in a Valence language format; mapping the target function module and the connection relation in the PLD implementation design file to the top layer of a device model in the PLD model file, and configuring the corresponding grid point element on the top layer; traversing and extracting configuration parameters of each lattice point element on the top layer to generate a configuration file; and writing the configuration file into the PLD to be configured. The method can realize the precise configuration process of the PLD, and is beneficial to the development and the test of designers on the PLD. The invention can configure the basic elements forming the PLD, thereby realizing the maximization of the resource utilization of the PLD chip, and simultaneously, flexibly setting the internal structure of the lattice point elements and the connection relation among the lattice point elements, and effectively solving the problem of accurate control of the critical path.
Example two:
the embodiment of the invention provides a programmable logic device configuration device, which is used for realizing the programmable logic device configuration method in the embodiment I. Referring to fig. 5, fig. 5 is a schematic structural diagram of a configuration device of a programmable logic device according to a second embodiment of the present invention, where the configuration device 5 of the programmable logic device includes: a model generation module 51, a design generation module 52, and a processing module 53, wherein:
the model generation module 51 is configured to generate a PLD model file, where the PLD model file includes a device model and an operator model; the device model comprises PLD basic elements at a bottom layer, lattice point elements at a middle layer and a lattice point system at a top layer, wherein the lattice point elements consist of at least one basic element, and the lattice point system consists of at least one lattice point element; the operator model comprises functional modules for realizing all functions, and one functional module is realized by connecting and combining the basic elements in the lattice point elements.
The PLD model file generated by the model generation module 51, that is, the PLD to be configured, is modeled, and the generated PLD model file includes the device model. The device model comprises PLD basic elements at the bottom layer, lattice point elements at the middle layer and a lattice point system at the top layer. The basic elements of the bottom layer are abstract minimum working units, the lattice point elements of the middle layer are formed by combining and connecting one or more basic elements, and the lattice point system of the top layer is formed by arranging the lattice point elements according to a certain rule.
The device model generated by the model generation module 51 should further include identification information uniquely identifying the device model, function parameter configuration information of the implemented function, and corresponding interface information. It should be understood that the identification information uniquely identifying the device model may be the name of the model device; the configuration information of the functional parameters may be specifically set according to the logic function implemented by the PLD to be configured.
In the process of generating the device model by the model generating module 51, the model generating module is further configured to describe the functional structures of the components for generating the PLD device model to be configured, so as to form a complete device model. The components comprise PLD basic elements at the bottom layer, lattice elements at the middle layer and lattice system at the top layer.
The description of the various components by the model generation module 51 may be made in a number of ways, including structural descriptions, configuration descriptions, and graphical descriptions. The structural description is used for defining the internal structure of the assembly, for example, a lattice point element is formed by combining and connecting a plurality of basic elements, and the configuration parameter value of each basic element and the connection relation between the basic elements are defined in the structural description. It should be understood that since the basic elements are the smallest basic units of abstraction, there is no structural description of the basic elements. The configuration description is used for defining configuration points and configuration values of the components, and as the arrangement of the lattice elements in the top-level lattice system is regular, all the Config bits can be completely planned in the lattice elements, so that the position of one Config Bit in the whole PLD device can be conveniently positioned. The graphic description is used for defining the graphics of the assembly, and is mainly used for drawing.
When the model generation module 51 models the PLD device to be configured, the PLD model file further includes an operator model, the operator model includes functional modules for implementing each function, one functional module is implemented by connecting and combining basic elements in the lattice element, and different basic elements can form different functional modules through different connection modes to implement different logic functions. Specifically, the functional module includes, but is not limited to, an adder, a multiplier, a comparator, a flip-flop, and the like, and may be referred to as a functional module.
The functional module comprises module identification information for uniquely identifying the functional module, parameter configuration information of the realized function, corresponding interface information and description information of all realization modes for realizing the functional module. It should be noted that the specific function of a functional module is not unique in implementation, and there may be many different implementations, and some of them may be reasonably selected in the subsequent configuration process based on the actual use scenario.
In this embodiment, the programmable logic device configuration apparatus 5 further includes a design generation module 52, configured to select a corresponding target function module from the operator model according to the function of the PLD to be configured, and determine a connection relationship between the target function modules to generate a PLD implementation design file in a Valence language format.
Specifically, the design generation module 52 may determine each input/output interface according to the function required to be implemented by the design; for each target function module, generating an internal implementation description sentence for describing each target function module; and generating description sentences of the routing paths according to the connection relation of the target function modules, and identifying and constraining the key routing paths. And finally generating a PLD implementation design file in a Valence language format.
The PLD implementation design file in the Valence language format generated by the design generation module 52 mainly includes three statement blocks: interface definition statement block, internal realization statement block and routing path definition statement block.
The interface definition statement block comprises a description statement used for defining a design name and defining related parameters of the design, and an input/output interface statement; the input/output port can be simply understood as the input and output of the module in the Verilog language, and the main role of the input/output port is the interaction between the PLD device and external signals, such as clock signals input into the PLD device. The internal implementation statement block includes an internal structure description statement of the design, and specifically, instantiates and connects a specific function module to implement a corresponding function. When writing the internal structure, not only the existing functional module may be used, but also a special functional module may be designed according to actual requirements, and even the lattice element or the basic element may be directly configured and connected, for example, the position of the functional module and/or the component in the whole PLD to be configured may be directly specified, and the position of the used functional module and/or the component may be specifically constrained by coordinates of each lattice point in the lattice point system.
The trace path definition statement block includes description statements of each trace path, and is used for identifying and constraining the critical trace path of the PLD, so as to realize accurate control of the critical trace path. The key routing path in this embodiment may be any network cable (a network cable may be understood as a wire in Verilog language, and is used to connect ports of two functional modules to implement data transmission), ports of the functional modules connected to two ends of one network cable are determined in an internal structure description statement, a routing path definition statement only restricts a path of the key network cable, and a network cable that is not restricted may be routed by using a routing algorithm during subsequent processing.
In this embodiment, the description language for generating the file format may be referred to as a value language, where the design file is implemented by the PLD model file generated by the model generating module 51 and the PLD generated by the design generating module 52.
The processing module 53 is configured to map the target function module and the connection relationship in the PLD implementation design file onto a top layer of a device model in the PLD model file, and configure a corresponding lattice element on the top layer; and traversing and extracting the configuration parameters of each lattice point element on the top layer to generate a configuration file, and writing the configuration file into the PLD to be configured.
After the model generating module 51 generates the PLD model file in the Valence language format and the design generating module 52 generates the PLD implementation design file, the processing module 53 may read the target function module, the connection relationship between the target function module and the device model, and map the target function module and the connection relationship in the PLD implementation design file to the top layer of the device model in the PLD model file, thereby implementing configuration of the PLD device model.
The processing module 53 may further include a compiling sub-module 531 and a mapping sub-module 532. Referring to fig. 6, fig. 6 is a schematic structural diagram of another configuration device for a programmable logic device according to a second embodiment of the present invention. The compiling submodule 531 is configured to sequentially compile the device models from a bottom layer to a top layer to obtain top layer grid models of the device models, store the top layer grid models in a model compiling library, compile each function module in the operator model, and store the compiled function modules in the model compiling library; and the PLD implementation design file is compiled to obtain a target function module example and a network cable example.
When compiling the PLD model file, the compiling submodule 531 may obtain a top grid model of the device model after compiling the device model because the PLD model file includes the device model and the operator model, and may store the top grid model in the model compiling library; for the operator model, the compiling sub-module 531 may also compile and store each functional module therein in the model compiling library.
When compiling the PLD implementation design file, the compiling submodule 531 obtains a target function module instance based on the internal implementation description statement therein, which describes each target function module, generates a network cable instance according to the connection relationship between each function module, and constrains the critical path according to the routing path description statement. Target function module examples and network cable examples obtained after compiling design files of PLD can be stored in a working library. The network cable example has unique identification of each target function module example connected with the network cable example, and the network cable example which is restrained by using the routing path definition statement block also stores the specific routing path.
It should be understood that the compiling result of the compiling submodule 531 for the PLD model file and the PLD implementation design file is not limited to be stored in the model compiling library and the work library, and may be stored in other storage spaces where the compiling result may be stored.
The mapping sub-module 532 is used for finding out the corresponding functional module from the model compiling library according to the target functional module instance, and configuring the corresponding functional module according to the parameter of each target functional module instance to obtain a parameter configuration functional module; and mapping each parameter configuration function module to a grid corresponding to the top grid model according to the network cable example and the implementation mode of each parameter configuration function module, and configuring grid elements on the corresponding grid according to the parameters of each parameter configuration function module.
The embodiment of the present invention provides a programmable logic device configuration apparatus 5, which generates a PLD model file in a Valence language format by using a model generation module 51, where the PLD model file includes a device model and an operator model, the device model includes a basic element located at a bottom layer, a lattice point element located at a middle layer, and a lattice point system located at a top layer, the lattice point element includes at least one basic element, and the lattice point system includes at least one lattice point element; the operator model comprises functional modules for realizing all functions, and one functional module is realized by connecting and combining basic elements in the lattice point elements; the design generation module 52 is configured to select a corresponding target function module from the operator model according to a function to be implemented by the PLD to be configured, and determine a connection relationship between the target function modules to generate a PLD implementation design file in a Valence language format; the processing module 53 is configured to map the target function module and the connection relationship in the PLD implementation design file onto a top layer of a device model in the PLD model file, and configure a corresponding lattice element on the top layer; traversing and extracting configuration parameters of each lattice point element on the top layer to generate a configuration file; and writing the configuration file into the PLD to be configured. The configuration equipment of the programmable logic device can realize the accurate configuration of the PLD, and effectively solves the problems that the critical path cannot be accurately controlled and the utilization rate of the PLD chip resources cannot be increased. Meanwhile, the internal structure of the lattice element and the connection relation between the lattice elements can be flexibly set, and the development and the test of a designer on the PLD logic function are facilitated.
It will be apparent to those skilled in the art that the modules or steps of the embodiments of the invention described above may be implemented in a general purpose computing device, they may be centralized on a single computing device or distributed across a network of multiple computing devices, and alternatively, they may be implemented in program code executable by a computing device, such that they may be stored on a computer storage medium (ROM/RAM, magnetic disk, optical disk) and executed by a computing device, and in some cases, the steps shown or described may be performed in an order different than that described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple ones of them may be fabricated into a single integrated circuit module. Thus, the present invention is not limited to any specific combination of hardware and software.
The foregoing is a more detailed description of embodiments of the present invention, and the present invention is not to be considered limited to such descriptions. For those skilled in the art to which the invention pertains, several simple deductions or substitutions can be made without departing from the spirit of the invention, and all shall be considered as belonging to the protection scope of the invention.
Claims (10)
1. A method for configuring a programmable logic device, comprising:
generating a programmable logic device model file in a Valence language format, wherein the programmable logic device model file comprises a device model and an operator model; the device model comprises basic elements of the programmable logic device at the bottom layer, lattice point elements at the middle layer and a lattice point system at the top layer, wherein the lattice point elements consist of at least one basic element, and the lattice point system consists of at least one lattice point element; the operator model library comprises functional modules for realizing all functions, and one functional module is realized by connecting and combining basic elements in the lattice element;
selecting a corresponding target function module from the operator model according to the function of the programmable logic device to be configured, and determining the connection relation among the target function modules to generate a programmable logic device implementation design file in a Valence language format; generating description sentences of each routing path according to the connection relation, and identifying and constraining the key routing paths;
mapping a target function module and a connection relation in the programmable logic device implementation design file to the top layer of a device model in the programmable logic device model file, and configuring a corresponding lattice point element on the top layer;
traversing and extracting configuration parameters of each lattice point element on the top layer to generate a configuration file;
and writing the configuration file into the programmable logic device to be configured.
2. The programmable logic device configuration method of claim 1, wherein the device model includes identification information for uniquely identifying the device model, functional parameter configuration information of the implemented function, and corresponding interface information;
the lattice element includes configuration description information describing a position, graphic description information performing graphic representation, and structure description information describing an internal structure.
3. The programmable logic device configuration method according to claim 2, wherein the functional module includes module identification information for uniquely identifying the functional module, parameter configuration information of the implemented function, corresponding interface information, and all implementation description information for implementing the functional module.
4. The programmable logic device configuration method of claim 3, wherein said generating a programmable logic device implementation design file comprises:
determining and defining each input/output interface according to the connection relation;
for each target function module, generating an internal implementation description statement describing each target function module to obtain a target function module example;
and generating description sentences of each routing path according to the connection relation, and identifying and constraining the key routing paths to obtain a network cable example.
5. The method for configuring a programmable logic device according to claim 4, wherein mapping the target function module and the connection relation in the implementation design file of the programmable logic device onto the top layer, and configuring the corresponding lattice point element on the top layer comprises:
sequentially compiling the device model from the bottom layer to the top layer to obtain a top layer grid model of the device model, storing the top layer grid model in a model compiling library, and compiling and storing each functional module in the operator model in the model compiling library;
compiling the programmable logic device implementation design file to obtain a target function module example and a network cable example;
finding out respective corresponding functional modules from the model compiling library according to the target functional module examples, and configuring the corresponding functional modules according to the parameters of the target functional module examples to obtain parameter configuration functional modules;
and mapping each parameter configuration function module to a grid corresponding to the top grid model according to the network cable example and the implementation mode of each parameter configuration function module, and configuring grid elements on the corresponding grid according to the parameters of each parameter configuration function module.
6. A programmable logic device configuration apparatus, comprising:
the model generation module is used for generating a programmable logic device model file in a Valence language format, and the programmable logic device model file comprises a device model and an operator model; the device model comprises basic elements of the programmable logic device at the bottom layer, lattice point elements at the middle layer and a lattice point system at the top layer, wherein the lattice point elements consist of at least one basic element, and the lattice point system consists of at least one lattice point element; the operator model library comprises functional modules for realizing all functions, and one functional module is realized by connecting and combining basic elements in the lattice element;
the design generation module is used for selecting a corresponding target function module from the operator model according to the function of the programmable logic device to be configured, and determining the connection relation among the target function modules to generate a programmable logic device implementation design file in a Valence language format; generating description sentences of each routing path according to the connection relation, and identifying and constraining the key routing paths;
the processing module is used for mapping the target function module and the connection relation in the programmable logic device implementation design file to the top layer of the device model in the programmable logic device model file and configuring the corresponding lattice point element on the top layer; and the configuration file is also used for traversing and extracting the configuration parameters of each lattice point element on the top layer to generate a configuration file, and writing the configuration file into the programmable logic device to be configured.
7. The programmable logic device configuration apparatus of claim 6, wherein the device model includes identification information for uniquely identifying the device model, functional parameter configuration information of the implemented function, and corresponding interface information;
the lattice element includes configuration description information describing a position, graphic description information performing graphic representation, and structure description information describing an internal structure.
8. The programmable logic device configuration apparatus of claim 7, wherein the functional module includes module identification information for uniquely identifying the functional module, parameter configuration information of the implemented function, corresponding interface information, and all implementation description information for implementing the functional module.
9. The configuration device of claim 8, wherein the design generation module is configured to determine and define each input/output interface according to the connection relationship, generate, for each target function module, an internal implementation description statement describing each target function module to obtain a target function module instance, generate a description statement describing each routing path according to the connection relationship, and perform identification constraint on a key routing path to obtain a network cable instance.
10. The programmable logic device configuration apparatus of claim 9, wherein the processing module comprises:
the compiling submodule is used for compiling the device models from the bottom layer to the top layer in sequence to obtain top layer grid models of the device models and storing the top layer grid models in a model compiling library, and compiling and storing each functional module in the operator models in the model compiling library; the programmable logic device is also used for compiling the programmable logic device implementation design file to obtain a target function module example and a network cable example;
the mapping submodule is used for finding out the corresponding functional module from the model compiling library according to the target functional module example and configuring the corresponding functional module according to the parameter of each target functional module example to obtain a parameter configuration functional module; and the grid element configuration module is also used for mapping each parameter configuration function module to the grid corresponding to the top grid model according to the network cable example and the implementation mode of each parameter configuration function module, and configuring the grid element on the corresponding grid according to the parameters of each parameter configuration function module.
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