CN106663402B

CN106663402B - Refreshing multiple regions of a display device simultaneously using multiple different refresh rates

Info

Publication number: CN106663402B
Application number: CN201580041805.3A
Authority: CN
Inventors: 王超昊; 李思贤; P·萨凯托; 张世昌; 黄俊尧; P·S·德尔泽克
Original assignee: Apple Inc
Current assignee: Apple Inc
Priority date: 2014-08-05
Filing date: 2015-07-15
Publication date: 2020-05-19
Anticipated expiration: 2035-07-15
Also published as: KR101965079B1; EP3178083A1; CN111462710A; KR20170024106A; CN106663402A; EP3178083A4; CN111462710B

Abstract

The present invention relates to a method and apparatus for refreshing a display device at various frequencies. In particular, multiple regions of the display device may be refreshed simultaneously at different frequencies. In this way, when static content is being displayed in particular regions of a display device, those particular regions may be refreshed at a lower rate than regions displaying dynamic content, such as video or animation. By refreshing at a lower rate, the energy consumed by the display device and subsystems associated with the display device may be reduced. Further, a process for reducing flicker when refreshing a display device at different refresh rates is disclosed herein.

Description

Refreshing multiple regions of a display device simultaneously using multiple different refresh rates

Technical Field

The described embodiments relate generally to modifying a refresh rate of a display device. More particularly, the present embodiments relate to methods and apparatus for refreshing multiple regions of a display device simultaneously at different rates.

Background

Recent advances in computing devices have allowed visually impressive graphics to be displayed on many lightweight and often portable computing devices. Graphics may be provided by a variety of systems including a graphics processor and a display monitor. Many graphics processors may interact with a display monitor to provide images and video that may be updated or refreshed without the display monitor user perceiving any interruptions. However, during extended periods of time, both data transmission and light emission from the display monitor require a significant amount of energy that is not typically available when implemented in portable computing devices. Typically, this energy is dedicated to the conversion between the color and brightness levels of the display, and thus designing a display that does not provide the optimal conversion may degrade the user experience of the computing device. As a result, manufacturers must often choose between providing a more impressive visual display or conserving energy in order to provide a longer battery life for the computing device.

Many computing devices are used primarily for internet browsing, which may often require the display of various graphics. For example, some web pages are dedicated to streaming video and, therefore, may require a significant amount of effort from the graphics processor of the computing device. To provide a smooth video stream, the display monitor should be refreshed at a rate that allows the video to be presented smoothly on the display monitor. However, because typically the entire area of the display monitor is refreshed regardless of the size of the video being displayed, maintaining a high refresh rate may be inefficient with respect to energy consumption. Thus, even if a user of a computing device streams small videos on a large display monitor, the refresh rate will be dynamic relative to the video size. Because the hardware of many computing devices is not designed to adjust the refresh rate according to the application being executed, users are typically left with devices that cannot maintain a charge during frequent media playback periods. Thus, users are generally discouraged from displaying media streams until they can plug their computing device into a charging port, or until they know that they will not require battery life for other applications at a particular point in the day. Furthermore, while many processes of an application occur on a cloud server rather than a computing device, an idle screen displaying animations of various applications can also consume energy in a wasteful manner. In this way, in some cases, the application may consume more energy for aesthetic purposes only, rather than the primary purpose of the application.

Disclosure of Invention

Various embodiments are described herein that relate to methods and apparatus for controlling a refresh rate of a display device. In some embodiments, display devices such as Liquid Crystal Displays (LCDs) or Light Emitting Diode (LED) displays are listed. The display device may include: the display device includes a pixel array, a gate driver operatively coupled to the pixel array, and a data driver operatively coupled to the pixel array. The display device may further include a control circuit operatively coupled to the gate driver. The control circuit may be configured to: providing a normal refresh signal to the gate driver when the row of the first frame data set is different from the row of the second frame data set; and providing the modified refresh signal to the gate driver when the row of the first frame data set is the same as the row of the second frame data set.

In other embodiments, methods are listed for refreshing multiple regions of a display device simultaneously at different refresh rates. The method may include generating a first data frame and a second data frame, and comparing a plurality of rows of the first data frame to a plurality of rows of the second data frame. The method may also include determining a modified row of the second data frame, where the modified row is a different data row in the second data frame than a corresponding data row in the first data frame. Further, the method may comprise: a first portion of the display device corresponding to the modified row of the second data frame is caused to refresh at a first refresh rate, and a second portion of the display device adjacent to the first portion of the display device is caused to refresh at a second refresh rate.

In yet other embodiments, a machine-readable non-transitory storage medium is listed. The storage medium may store instructions that, when executed by a processor included in a computing device, cause the computing device to perform steps comprising: a first data frame and a second data frame corresponding to image data to be displayed on a display device are received. This step may also include comparing the first set of rows of the first data frame with the second set of rows and the third set of rows in the second data frame. Further, the step may include determining that a first subset of rows of the first set of rows is not the same as a first subset of rows of the second set of rows, and determining that a second subset of rows of the first set of rows is the same as a second subset of rows of the third set of rows. Further, the step may include: causing a first set of driver circuits corresponding to the second set of rows to transition to a high state and causing a second set of driver circuits corresponding to the third set of rows to transition to a low state.

Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the embodiments.

Drawings

The present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings, wherein like reference numerals designate like structural elements.

FIG. 1 illustrates a computing device having a display including multiple regions, where the displayed graphics are static or dynamic.

Fig. 2 illustrates a system diagram for controlling a display device according to some embodiments discussed herein.

Fig. 3 shows a diagram of a display device having an array of Light Emitting Diodes (LEDs) connected to a gate driver and a data driver.

Fig. 4A to 4B show a gate driver circuit having a unit circuit and an output selector circuit.

Fig. 5 shows a diagram listing how multiple rows and regions of an LED array may be refreshed at different rates based on the operation of the gate driver circuit.

Fig. 6A-6B illustrate problems and solutions associated with providing multiple refresh rates to an LED array.

FIG. 7 shows a diagram for performing multi-bank and multi-parameter gamma distributions in order to mitigate flicker and ripple issues at refresh boundaries.

Fig. 8 illustrates a method for modifying the refresh rate of a row or group of rows based on the difference between frames provided to an LED array.

FIG. 9 illustrates a method for adjusting the refresh rate of one or more rows of an LED array based on the blinking content of one or more frames or images to be displayed by the LED array.

FIG. 10 illustrates a method for refreshing one or more rows of an LED array based on the amount of time that one or more rows have remained static or unchanged.

FIG. 11 is a block diagram of a computing device that may represent components of various embodiments discussed herein.

Detailed Description

This section describes representative applications of the methods and apparatus according to the present patent application. These examples are provided solely to add context and aid in the understanding of the described embodiments. It will thus be apparent to one skilled in the art that the embodiments may be practiced without some or all of these specific details. In other instances, well known process steps have not been described in detail in order to avoid unnecessarily obscuring the embodiments. Other applications are possible, such that the following examples should not be considered limiting.

In the following detailed description, reference is made to the accompanying drawings which form a part hereof, and in which is shown by way of illustration specific embodiments in accordance with the embodiments. Although these embodiments are described in sufficient detail to enable those skilled in the art to practice the embodiments, it is to be understood that these examples are not limiting, such that other embodiments may be utilized and that modifications may be made without departing from the spirit and scope of the embodiments.

Embodiments discussed herein relate to a display device configured to refresh at different rates based on content to be displayed by the display device. Many computing devices have displays that typically display both still images and moving images over various periods of use. Still images and moving images may generally be displayed simultaneously on a display of a computing device. According to embodiments discussed herein, a lower refresh rate may be assigned to portions of a display that are displaying static images, and a normal refresh rate may be assigned to portions of the display that are displaying dynamic images. These differences in refresh rates may be implemented in part by output selector circuitry that may prevent updating one or more rows of the display. In particular, the display may include an array of LEDs having a plurality of rows, and each row may be connected to a gate driver, which may be prevented from allowing refresh of the respective row based on the action of the output selector circuit. In some cases, the data driver provides updated frame data to the LED array, and the gate driver may prevent refreshing one or more rows of the LED array if the updated frame data is the same for two or more refreshes. For example, when an LED array is outputting a static image at a portion of the LED array, a control signal may be provided to an output selector that prevents the portion of the LED array from being refreshed at a rate equal to other portions of the LED array. A single row or multiple sets of rows may be refreshed differently than other portions of the LED array, such that at least two refresh rates are used to provide output from the LED array. In some embodiments, the refresh rate assigned to a portion of the LED array may be based on the flashing content of one or more images to be output by the LED array. For example, when an image contains high flicker content, a corresponding portion of the LED array may be assigned a low refresh rate. Furthermore, when an image contains low flicker content, the corresponding portion of the LED array may be assigned a very low refresh rate. Furthermore, during each refresh, polarity changes may be performed in order to mitigate wear of the LEDs of the LED array.

When multiple refresh rates are used simultaneously on a display device, the ripple may be visible by a user of the computing device to which the display device is attached. The ripple may be caused by the boundary between two adjacent portions of the display that operate at different refresh rates. To mitigate and prevent the occurrence of ripple, compensation methods are discussed herein. In one embodiment, a digital compensation method is used. The digital compensation method allows at least 2-bit spatial dithering to be performed on the data presented at the display boundary in question. In another embodiment, an interpolation process is used that interpolates at least two gamma curves based on the refresh rate of the line or lines in question. The interpolation results are output to the line or lines in question to adjust the gamma of the image to be displayed at the line or lines for making any ripple effect imperceptible.

These and other embodiments are discussed below with reference to fig. 1-11; however, those skilled in the art will readily appreciate that the detailed description given herein with respect to these figures is for explanatory purposes only and should not be construed as limiting.

FIG. 1 illustrates a computing device 100 having a display 102 that includes multiple regions, where the displayed graphics are static or dynamic. In particular, the display 102 of the computing device 100 includes a header row 104 and a dynamic icon row 106 that are continuously updated according to a cycle or period programmed within the computing device 100. The display 102 also includes a static area 108 that is not constantly updated but remains static until input is received from a user, a network connection, or other suitable input source of the computing device 100. The header line 104 may include indicators of wireless signal strength, clock time, and battery life, which may typically change at any given time. For this purpose, the header line 104 must display different values and adjust according to the dynamic changes that occur. The dynamic icon row 106 may also be modified according to the updates that occur at the dynamic icon 110. The dynamic icon 110 may display current date and clock time that is constantly changing and updated. In this way, the dynamic icon 110 should be refreshed more frequently than the static area 108 to reduce energy consumption, as discussed further herein. For example, during operation of an application on computing device 100, a display manager stored in computing device 100 may determine whether one or more lines currently presented on display 102 include dynamic data. Following this and as discussed further herein, the display manager may assign a higher refresh rate for rows that include dynamic data than rows that do not include dynamic data.

Fig. 2 illustrates a system diagram 200 for controlling a display device 210 according to some embodiments discussed herein. In particular, fig. 2 illustrates how the computing device 202 disclosed herein interacts with the display device 210 to simultaneously assign different refresh rates to various regions of the display device 210, thereby conserving battery life of the computing device 202. The computing device 202 may include a memory 204 that stores a display manager 206 for transferring display data between a processor 208 and a display device 210. The display device 210 may include a data driver 216 for providing display data to a Light Emitting Diode (LED) array 214. The LED array 214 may include any suitable type of LEDs for display at the display device 210. For example, the LED array 214 may be an organic light emitting diode array. The gate driver 212 may be responsible for providing power to the individual LEDs of the display device 210 and scanning the rows and/or columns of the LED array 214 according to the refresh rate provided from the display manager 206. The display device may include a plurality of gate drivers 212, a plurality of data drivers 216, and a plurality of LED arrays 214 arranged in any manner suitable for operating the display device 210. The data driver 216 and the gate driver 212 may be configured to control the brightness of each LED pixel on the display device 210. Further, the display device 210 may be any display monitor suitable for use by a computing device, such as a desktop computer, a mobile device, a media player, or any other computer-related apparatus. In some embodiments, display device 210 is a Liquid Crystal Display (LCD) with an LED backlight. The LED backlight may be decoupled from the gate driver 212 and the data driver 216, and the gate driver 212 and the data driver 216 may be used to control the transmittance of the liquid crystal for passing LED light from the LED backlight. In this manner, the LEDs of the liquid crystal or LED arrays discussed herein may be used as a pixel array to provide a channel or source for light projected from the display device 210.

Fig. 3 shows a diagram 300 of a display device 210 having an LED array 214 connected to a gate driver 212 and a data driver 216. As discussed further herein, the gate driver 212 may include a plurality of gate output controllers that provide power and scan data outputs to each row and/or each column of the LED array. According to embodiments discussed herein, each gate output 302 may be limited by the refresh rate of each individual row or group of rows. In this manner, one or more gate outputs 302 may be refreshed at a rate different from one or more other gate outputs 302. Further, the data driver 216 may include a plurality of data outputs 304 for updating and transmitting signals to the LED array 214. In some embodiments, one or more of the data outputs 304 may be stopped or transitioned to a low output state to reduce power consumption while the LED array 214 is displaying a static image on the screen. Further, when the data output 304 is stopped or in a low state, the refresh rate corresponding to the gate output 302 may be reduced in a region affecting a portion of the LED array 214 displaying a static image.

Fig. 4A to 4B show a gate driver circuit 400 having a unit circuit 410 and an output selector 412. The gate driver circuit 400 includes a control circuit 408 connected to a plurality of transistors and inputs for allowing the control circuit 408 to scan updates from the data driver 216. One or more of the plurality of transistors may be an oxide transistor (e.g., an oxide thin film transistor) that provides a very low off-state current, allowing for less power consumption when a low refresh rate is applied to the LED array 214, as discussed further herein. Furthermore, by using oxide transistors in combination with the LED array 214 of organic LEDs, a significant reduction in power consumption can be achieved compared to displays using low temperature polysilicon. Thus, the apparatus and methods discussed herein may be implemented using a gate driver circuit 400 having one or more oxide thin film transistors connected to an LED array 214 of organic LEDs. Furthermore, in some embodiments, a gate driver circuit 400 may be incorporated into each gate output 302 to simultaneously scan one or more rows based on one or more clock signals provided to the gate driver circuit 400. An output selector 412 is incorporated into the gate driver circuit 400 to prevent scanning based on the control input 402. For example, as shown in FIG. 4A, a scan signal 414 may be provided to the output selector 412 and prevented from being output from the selector output 404 by the absence of the control input 402. When the control input 402 is not provided to the output selector 412, a no signal or low voltage signal may be output from the selector output 404. Fig. 4B shows an example when a control signal 416 is received at the control input 402 of the output selector 412. Due to the control signal 416, a conductive path is formed at the transistor between the control input 402 and the selector output 404, allowing the scan signal 414 to be output from the selector output 404. In the context of logic circuits to which the scan signal is provided, the scan signal 414 may be a high voltage to indicate an "on" or "high" state of operation. Thus, although the scan signal 414 may be constantly applied throughout the gate driver circuit 400, the scan signal 414 will not be output from the selector output 404 until the control signal 416 is received at the control input 402. In this manner, because the gate driver circuit 400 may be incorporated at each gate output 302, one or more rows of gate outputs may be prevented from outputting scan signals 414, or caused to output "off" or "low" signals, simply by applying control signals 416 to one or more gate driver circuits 400.

Fig. 5 shows a graph 500 listing how multiple rows and regions of LED array 214 may be refreshed at different rates based on the operation of gate driver circuit 400. Specifically, fig. 5 lists an example when a first refresh rate is assigned to a first region 508 of LED array 214 that is greater than a second refresh rate assigned to a second region 510 of LED array 214. At frame 1, both the first region 508 and the second region 510 are refreshed based on the scanning performed on all rows of the LED array 214 due to both the first refresh rate and the second refresh rate. For purposes of explanation, the first region 508 may be streaming video and the second region 510 may be a still image that abuts the streaming video. From the second frame to the "N + 3" frame, the first refresh rate is such that the rows corresponding to the first region 508 are refreshed at each frame to allow the streaming video to be updated at each frame. However, the second refresh rate is such that rows corresponding to the second region 510 are not refreshed and remain static because the second refresh rate is lower than the first refresh rate. At an "N + 4" frame, the first region 508 and the second region 510 are refreshed simultaneously again after the second region 510 has remained unrefreshed for a plurality of consecutive frames. In this way, rather than refreshing the entire LED array 214 at the same rate, energy is conserved by refreshing portions of the LED array 214 at different refresh rates. In some embodiments, any suitable number of refresh rates may be applied to the LED array 214. For example, at least three different refresh rates may be applied to the LED array 214. Further, a minimum refresh rate for one or more rows of LED array 214 may be determined. The minimum refresh rate may be the lowest refresh rate that prevents flickering of the image displayed by the LED array 214. Further, the polarity change may be performed during each refresh performed at a respective area or row of the LED array 214.

Fig. 6A-6B illustrate problems and solutions associated with providing multiple refresh rates to LED array 214. In particular, fig. 6A illustrates a representation of a refresh boundary 608 that may be visible to a user when a refresh rate of the first region 508 is greater than a refresh rate of the second region 510. A representation of the refresh boundary 608 can be seen in FIG. 6A, where the average refresh line 606 is shown. The average refresh line 606 is an example as follows: when the first refresh rate 602 is greater than the second refresh rate 604 and two refresh rates are simultaneously exhibited adjacent to the refresh boundary 608. Due to the average refresh line 606, flicker or brightness ripple will be visible unless the refresh boundary 608 is compensated. To address the problems of flicker and ripple, solutions are listed in fig. 6B and 7. In particular, fig. 6B illustrates how compensation for the refresh boundary 608 can be performed in the digital domain using a set of pixels 610, the set of pixels being interchangeable over the refresh boundary 608 based on the refresh rate. For example, each pixel block 612 shown in pixel set 610 may be ordered and/or alternated for each set of at least 2 x 2 pixels that traverses refresh boundary 608. This technique (sometimes referred to as spatial dithering) may be performed to provide a visually smooth transition between two regions having different refresh rates.

Fig. 7 illustrates a system diagram 700 for performing multi-bank and multi-parameter gamma distributions in order to mitigate the flicker and ripple problem at the refresh boundary 608. In particular, fig. 7 shows an analog solution for applying gamma switching to rows or row blocks in order to correct for flicker and ripple. The system diagram 700 includes a first library 702 storing a first gamma curve and a second library 704 storing a second gamma curve. Each of the first and second gamma curves is associated with one of two refresh rates that may be respectively applied to the LED array 214. During compensation operations using gamma switching, the first and second gamma curves are input into the interpolation module 708 along with the row block refresh rate 706. After which the first and second gamma curves are interpolated. The interpolation method may be of any suitable form for interpolating image data. The interpolation results of the first and second gamma curves may be scaled or otherwise modified according to the row block refresh rate 706 provided to the interpolation module 708. Thus, the row block gamma 710 is output from the interpolation module 708 as a curve to provide an analog solution to hide the refresh boundary 608. Depending on the severity of the flicker and ripple occurring at the refresh boundary 608, the row block gamma 710 may be applied to one or more rows of the LED array 214 simultaneously.

Fig. 8 illustrates a method 800 for modifying the refresh rate of a row or group of rows based on differences between frames provided to the LED array 214. Specifically, the method 800 includes step 802: the first data frame and the second data frame are generated by the display manager 206. The first and second data frames may be generated at the computing device 202 or the display device 210 by one or more software modules within one or both respective devices. At step 804, the display manager 206 compares each first frame line (i.e., the line of the first data frame) to each second frame line (i.e., the line of the second data frame). The comparison of step 804 may be done sequentially for each row or one at a time, or the comparison of all rows may be performed simultaneously. At step 806, the display manager 206 determines whether the first frame line is different from the second frame line. If the first frame row is different than the second frame row, at step 808, the display manager 206 causes the array rows associated with the second frame row to be refreshed according to the normal refresh rate. If the first frame row is the same as the second frame row, at step 810, the display manager 206 causes the array rows associated with the second frame row to be refreshed according to a low refresh rate. In this way, the frame lines that remain static over multiple consecutive frames can be kept at a low refresh rate to conserve energy. For example, the normal refresh rate may be 30 hertz or 60 hertz, the low refresh rate may be 10 hertz or 2 hertz, and the very low refresh rate may be 1 Hz. The normal refresh rate, the low refresh rate, and the very low refresh rate may be one or more arbitrary values suitable for a given display device. As discussed further herein, the normal refresh rate may be greater than the low refresh rate, and the low refresh rate may be greater than the very low refresh rate.

Fig. 9 illustrates a method 900 for adjusting the refresh rate of one or more rows of LED array 214 based on the blinking content of one or more frames or images to be displayed by LED array 214. Flicker content or flicker refers to the amount or severity of an apparent transition from frame to frame that a user may perceive when viewing a display of a computing device. The method 900 includes step 902, wherein the display manager 206 generates a first data frame and a second data frame. Each of the first and second data frames includes one or more rows of data to be provided to the LED array 214. At step 904, the display manager 206 compares each first frame line of the first frame with each second frame line of the second frame. Thereafter, at step 906, the display manager 206 determines whether the first frame line is different from the second frame for one or more of the first frame lines of the first frame and one or more of the second frame lines of the second frame. If any of the first frame lines are different from the corresponding second frame lines, at step 908, the display manager 206 may refresh one or more corresponding second frame lines according to the normal refresh rate. If any of the first frame lines are the same as the corresponding second frame lines, the display manager 206 may proceed to step 910. At step 910, the display manager 206 may determine whether any second frame lines include high flicker content. If any of the second frame lines include high flicker content (e.g., content that would cause the user to notice flicker from the LED array 214), the display manager 206 may refresh the second frame lines according to a low refresh rate at step 912. The refresh rates provided herein may be assigned to one or more transitions between frames such that a next transition may be delayed according to the corresponding refresh rate. If any of the second frame lines do not contain high flicker content, at step 914, the display manager 205 may refresh the corresponding second frame line according to the very low refresh rate. In this way, the row or rows assigned to the very low refresh rate may remain static longer to save energy. Any of the methods discussed herein may analyze a single row at a time, iteratively, or multiple rows simultaneously, in order to effectively determine the refresh rate applicable to one or more rows of LED array 214.

Fig. 10 shows a method 1000 for refreshing one or more rows of LED array 214 based on the amount of time that one or more rows have remained static or unchanged. Method 1000 includes step 1002, where display manager 206 determines how long one or more rows of LED array 214 have been static. At step 1004, the display manager 206 compares the static time or the time that one or more rows have remained static or have not changed to a predetermined threshold time. The threshold time may be a value set by a user or manufacturer that remains constant throughout the life of the LED array 214 or that changes based on hardware changes of a computing device associated with the LED array 214. At step 1006, the display manager 206 determines whether the static time is greater than a threshold time. If the static time is greater than the threshold time, at step 1010, the display manager 206 may prevent refreshing one or more rows. In this manner, the refresh rate of one or more rows of LED array 214 will be based on the amount of time that one or more rows have been in a quiescent state. If the static time is less than or equal to the threshold time, at step 1008, the display manager 206 may allow one or more rows to be refreshed. After

steps

1008 and 1010, at step 1012, the display manager 206 may analyze the next line or lines of the current frame or a subsequent frame. For example, method 1000 may be performed for each frame of data provided to LED array 214 and for each row of each frame. When all frames have been analyzed according to method 1000, display manager 206 may proceed to the next frame to be provided to LED array 214. It should be noted that any of the methods or embodiments discussed herein may be combined and performed in any order or arrangement suitable to mitigate energy consumption of a display device.

Fig. 11 is a block diagram of a computing device 1100 that may represent components of computing device 100 and/or computing device 202. It should be understood that the components, devices, or elements shown in fig. 11 and described with respect to fig. 11 may not be necessary, and thus some of them may be omitted in certain embodiments. The computing device 1100 may include a processor 1102, which represents a microprocessor, a coprocessor, circuitry, and/or a controller for controlling the overall operation of the computing device 1100. Although shown as a single processor, it is to be understood that the processor 1102 may comprise a plurality of processors. The multiple processors may be in operative communication with each other and may be collectively configured to perform one or more functions of the computing device 1100 as described herein. In some embodiments, the processor 1102 may be configured to execute instructions that may be stored at the computing device 1100 and/or otherwise accessible to the processor 1102. As such, whether configured by hardware or a combination of hardware and software, the processor 1102 is capable of performing operations and actions in accordance with the embodiments described herein.

Computing device 1100 can also include a user input device 1104 that allows a user of computing device 1100 to interact with computing device 1100. For example, user input device 1104 may take various forms, such as buttons, keypads, dials, touch screens, audio input interfaces, visual/image capture input interfaces, input in the form of sensor data, and so forth. Still further, the computing device 1100 may include a display 1108 (screen display) that is controllable by the processor 1102 to display information to a user. The controller 1110 may be used to interact with and control various devices via a device control bus 1112. Computing device 1100 can also include a network/bus interface 1114 coupled to a data link 1116. The data link 1116 may allow the computing device 1100 to couple to a host computer or an accessory device. The data link 1116 may be provided by a wired connection or a wireless connection. For wireless connectivity, the network/bus interface 1114 may include a wireless transceiver.

The computing device 1100 may also include a storage device 1118, which may have a single disk or multiple disks (e.g., hard disk drives), and a storage management module that manages one or more partitions (also referred to herein as "logical volumes") within the storage device 1118. In some embodiments, storage 1120 may include flash memory, semiconductor (solid state) memory, and the like. Still further, the computing device 1100 may include Read Only Memory (ROM)1122, Random Access Memory (RAM)1124, and the like. The ROM 1122 may store programs, code, instructions, utilities or processes to be executed in a non-volatile manner. RAM1124 can provide volatile data storage and store instructions related to components of a storage management module configured to perform the various techniques described herein. The computing device may also include a data bus 1126. The data bus 1126 may facilitate data and signal transfer between at least the processor 1102, the controller 1110, the network interface 1114, the storage device 1118, the ROM 1122, and the RAM 1124.

The various aspects, embodiments, implementations, or features of the described embodiments may be used alone or in any combination. Various aspects of the described implementations may be implemented in software, hardware, or a combination of hardware and software. The embodiments may also be embodied as computer readable code on a computer readable medium for controlling a production operation or as computer readable code on a computer readable medium for controlling a production line. The computer readable storage medium is any data storage device that can store data which can thereafter be read by a computer system. Examples of the computer readable storage medium include read-only memory, random-access memory, CD-ROMs, HDDs, DVDs, magnetic tapes, and optical data storage devices. The computer readable storage medium can also be distributed over network coupled computer systems so that the computer readable code is stored and executed in a distributed fashion. In some embodiments, the computer-readable storage medium may be non-transitory.

The foregoing description, for purposes of explanation, used specific nomenclature to provide a thorough understanding of the embodiments described. It will be apparent, however, to one skilled in the art that these specific details are not required in order to practice the embodiments. Thus, the foregoing descriptions of specific embodiments have been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the embodiments to the precise form disclosed. It will be apparent to those skilled in the art that many modifications and variations are possible in light of the above teaching.

Claims

1. A method for operating a display device, the method comprising:

receiving a first data frame and a second data frame corresponding to image data to be displayed on the display device;

comparing a first set of rows of the first data frame to both a second set of rows and a third set of rows in the second data frame;

determining that a first subset of rows of the first set of rows is different from the second set of rows;

determining that a second subset of rows of the first set of rows is the same as the third set of rows;

causing a first set of driver circuits corresponding to the second set of rows to refresh the second set of rows using a first refresh rate;

determining whether the third set of rows corresponds to a content type selected from a group comprising high flicker content or low flicker content;

causing a second set of driver circuits corresponding to the third set of rows to refresh the third set of rows with a second refresh rate when the third set of rows correspond to the high flickering content, the second refresh rate being lower than the first refresh rate; and

causing the second set of driver circuits corresponding to the third set of rows to refresh the third set of rows with a third refresh rate when the third set of rows correspond to the low flicker content, the third refresh rate being lower than a second refresh rate.

2. The method of claim 1, wherein causing the first set of driver circuits to refresh with a first refresh rate comprises allowing drive signals to be output to the second set of rows, and causing the second set of driver circuits to refresh with a second refresh rate or with a third refresh rate prevents drive signals from being output to the third set of rows.

3. The method of claim 1, further comprising:

performing a dithering process at a boundary between the second set of rows and the third set of rows.

4. The method of claim 1, further comprising:

performing an interpolation of two gamma curves to compensate for a difference between at least two refresh rates corresponding to the second set of rows and the third set of rows.

5. The method of claim 1, further comprising:

receiving a third data frame;

comparing a fourth set of rows in a third data frame with the third set of rows in a second data frame;

when the fourth set of rows is different from the third set of rows, causing the second set of driver circuits to refresh the fourth set of rows.

6. A display device, comprising:

an array of pixels;

a first set of gate drivers and a second set of gate drivers, each of the first set of gate drivers and the second set of gate drivers operatively coupled to the pixel array;

a data driver operatively coupled to the pixel array to provide frame data to the pixel array; and

a control circuit operatively coupled to the gate drivers in the first group or the second group, wherein the control circuit is configured to:

providing a normal refresh signal to the gate driver when one row of the first frame data set is different from one row of the second frame data set;

providing a modified refresh signal to the gate driver when the one row of the first frame data set is the same as the one row of the second frame data set and when the one row of the second frame data set includes high flicker content; and

providing a third refresh signal to the gate driver when the row of the first frame data set is the same as the row of the second frame data set and when the row of the second frame data set includes low flicker content;

wherein the control circuit is configured to (i) cause the first set of gate drivers to refresh a first portion of the pixel array at a normal refresh rate, (ii) cause the second set of gate drivers to refresh a second portion of the pixel array at a modified refresh rate or at a third refresh rate, and (iii) perform compensation on the frame data to mitigate perception of ripple at refresh boundaries when different refresh signals are used simultaneously in the pixel array,

wherein the modified refresh rate is lower than the normal refresh rate and the third refresh rate is lower than the modified refresh rate.

7. The display device of claim 6, wherein the normal refresh signal is provided to the gate driver when the control circuit receives a control signal, and the control signal causes circuit components to form a conductive path through which the normal refresh signal passes.

8. The display device of claim 6, wherein the normal refresh signal causes the pixel array to be refreshed at the normal refresh rate, the modified refresh signal causes the pixel array to be refreshed at the modified refresh rate, and the third refresh signal causes the pixel array to be refreshed at the third refresh rate.

9. The display device of claim 6, further comprising:

a plurality of control circuits configured to simultaneously provide the normal refresh signal and at least one of the modified refresh signal and the third refresh signal to the pixel array; and is

Wherein the pixel array comprises:

a plurality of liquid crystals configured to control transmission of light from a Light Emitting Diode (LED) backlight, or

A plurality of organic LEDs.

10. The display apparatus of claim 6, wherein the compensation comprises a row compensation operation within a frame at the refresh boundary, the refresh boundary being a result of the pixel array concurrently presenting the normal refresh rate at the first portion and the modified refresh rate or the third refresh rate at the second portion.

11. The display apparatus of claim 10, wherein the row compensation operation comprises performing a dithering operation across rows of the pixel array.

12. The display apparatus of claim 10, wherein the row compensation operation comprises performing interpolation between at least two gamma curves associated with at least one of the normal refresh rate and the modified refresh rate.

13. A computing device, comprising:

a display device, the display device comprising:

an array of pixels;

a control circuit operatively coupled to the gate driver, wherein the control circuit is configured to:

simultaneously supplying a plurality of different scan signals to the gate driver when one row of a first frame data set is the same as a corresponding first row in a second frame data set and is different from a second row in the second frame data set; and

wherein the control circuit is configured to (i) cause the first set of gate drivers to refresh a first portion of the pixel array at a normal refresh rate, (ii) cause the second set of gate drivers to refresh a second portion of the pixel array at a modified refresh rate when the second row in the second frame data set includes high flicker content, (iii) cause the second set of gate drivers to refresh the second portion of the pixel array at a third refresh rate when the second row in the second frame data set includes low flicker content, and (iv) perform compensation on the frame data to mitigate perception of ripple at refresh boundaries when different refresh signals are simultaneously used in the pixel array

14. The computing device of claim 13, wherein when the control circuit receives a control signal, a scan signal is provided to the gate driver, and the control signal causes a transistor to form a conductive path through which the scan signal passes.

15. The computing device of claim 13, wherein the plurality of different scan signals includes a normal scan signal and at least one of a modified scan signal and a third scan signal, wherein the normal scan signal corresponds to the normal refresh rate, the modified scan signal corresponds to the modified refresh rate, and the third scan signal corresponds to the third refresh rate.

16. The computing device of claim 15, further comprising:

a plurality of control circuits configured to simultaneously provide the normal scan signal and at least one of the modified scan signal and the third scan signal to the pixel array; and is

Wherein the pixel array comprises:

A plurality of organic LEDs.

17. The computing device of claim 13, wherein the compensation comprises a row compensation operation within a frame at the refresh boundary, the refresh boundary being a result of the pixel array concurrently presenting the normal refresh rate at the first portion and the modified refresh rate or the third refresh rate at the second portion.

18. The computing apparatus of claim 17, wherein the row compensation operation comprises performing interpolation between at least two gamma curves associated with the normal refresh rate and the modified refresh rate.