CN106653998A - Hall element and preparation method thereof - Google Patents
Hall element and preparation method thereof Download PDFInfo
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- CN106653998A CN106653998A CN201610707556.3A CN201610707556A CN106653998A CN 106653998 A CN106653998 A CN 106653998A CN 201610707556 A CN201610707556 A CN 201610707556A CN 106653998 A CN106653998 A CN 106653998A
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- indium arsenide
- arsenide layer
- hall element
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N52/00—Hall-effect devices
- H10N52/101—Semiconductor Hall-effect devices
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N50/00—Galvanomagnetic devices
- H10N50/80—Constructional details
- H10N50/85—Magnetic active materials
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N52/00—Hall-effect devices
- H10N52/01—Manufacture or treatment
Abstract
The invention relates to the field of sensing technology. A Hall element comprises a substrate, a P-type indium arsenide layer and an N-type indium arsenide layer, wherein the substrate, the P-type indium arsenide layer and the N-type indium arsenide layer are successively laminated. Because the indium arsenide layer is in an N-type doped manner and the P-type indium arsenide layer is a transition layer, a spatial charge area is formed at an interface between the N-type indium arsenide layer and the P-type indium arsenide layer. A metal electrode in the Hall element only contacts with an N-type area, and therefore the P-type indium arsenide layer is not conducted in the operation process of the Hall element. Accordingly, defects in the P-type indium arsenide layer do not affect performance of the Hall element. The N-type indium arsenide layer directly grows on the P-type N-type indium arsenide layer. Density of the defects is greatly reduced, thereby greatly increasing mobility of a material. Furthermore sensitivity of the Hall element is greatly improved. A preparation method of the Hall element has advantages of mature process, simple operation and high reliability.
Description
Technical field
The present invention relates to sensory field, and in particular to a kind of high sensitivity indium arsenide Hall element and preparation method thereof.
Background technology
Hall element is a kind of Magnetic Sensor based on Hall effect, is generally used for detecting magnetic field and its change.Hall unit
The sensitivity of part is closely related with the mobility of material.In order to further lift the sensitivity of Hall element, people adopt chemical combination
Thing semiconductor substituted for silicon, obtains the very excellent Hall element of performance.
Indium antimonide Hall unit sensitivity highest, the mobility of its body material reaches 78000cm2/ Vs, but indium antimonide
Energy gap is narrow, and the temperature coefficient of its Hall element can be caused excessively poor, limits its range of application.And GaAs Hall is first
In contrast, its temperature coefficient is very excellent, but sensitivity is low for part.Indium arsenide Hall element, then have both concurrently a little,
So as to extensively attract the concern of people.
However, when preparing indium arsenide film using epitaxy method, it is difficult because lacking the inexpensive substrate of Lattice Matching therewith
To prepare high-quality film, so as to cause indium arsenide film mobility low, and then the sensitivity of Hall element is reduced.In order to
The indium arsenide film of high mobility is obtained, conventional method adopts gallium arsenide substrate, the indium arsenide material of doping is grown thereon, can
To obtain mobility more than 12000cm2The film of/Vs, so as to substantially meet the application demand of indium arsenide Hall element.But,
Because GaAs and indium arsenide material have 7% lattice mismatch, in the region close to GaAs and indium arsenide interface, deposit
In substantial amounts of misfit dislocation, the overall mobility of material is reduced.
The content of the invention
For this purpose, to be solved by this invention is in existing indium arsenide Hall element, because indium arsenide mobility is low it to be affected
The problem of performance.
To solve above-mentioned technical problem, the technical solution used in the present invention is as follows：
The present invention provides a kind of Hall element, including the substrate, p-type indium arsenide layer, the N-type indium arsenide that are cascading
Layer.
Alternatively, the thickness of the p-type indium arsenide layer is 20nm～1000nm；
Alternatively, the N-type indium arsenide thickness degree is 100nm-1000nm.
Alternatively, the doped chemical of the N-type indium arsenide layer is silicon and/or tellurium and/or sulphur；
Alternatively, the substrate is gallium arsenide substrate.
The present invention also provides a kind of preparation method of described Hall element, comprises the steps：
P-type indium arsenide layer is formed on substrate；
N-type indium arsenide layer is formed on the p-type indium arsenide layer.
Alternatively, the p-type indium arsenide layer is prepared by epitaxial growth technology or chemical vapor deposition method.
Alternatively, the growing method of the p-type indium arsenide layer is：With arsine (AsH3) or tert-butyl group arsenic (TBAs) be arsenic
Source, trimethyl indium (TMIn) are indium source, diethyl zinc (DEZn) or two luxuriant magnesium (Cp2Mg it is) doped source, hydrogen (H2) it is to carry
Gas, growth temperature is 450 DEG C -600 DEG C, and pressure is 20-500mbar, and V/III, than being 5-200, is grown.
Alternatively, the growing method of the p-type indium arsenide layer is：With solid-state arsenic (As4) for arsenic source, solid indium be indium source,
Solid-state beryllium or solid zinc or solid-state magnesium are doped source, and 300 DEG C -550 DEG C of growth temperature, pressure is 1E-10Torr, and V/III ratio is
1-100, is grown.
Alternatively, the N-type indium arsenide layer is prepared by epitaxial growth technology or chemical vapor deposition method.
Alternatively, the growing method of the N-type indium arsenide layer is：With arsine (AsH3) or tert-butyl group arsenic (TBAs) be arsenic
Source, trimethyl indium (TMIn) are indium source, silane (SiH4) or disilane (Si2H6) be doped source, hydrogen (H2) it is carrier gas, grow
Temperature is 450 DEG C -600 DEG C, and pressure is 20-500mbar, and V/III, than being 5-200, is grown.
Alternatively, the growing method of the N-type indium arsenide layer is：With solid-state arsenic (As4) it is arsenic source, solid indium is indium source,
Solid-state silicon is doped source, and 300 DEG C -550 DEG C of growth temperature, background pressure is 1E-10Torr, and V/III, than being 1-100, is given birth to
It is long.
The above-mentioned technical proposal of the present invention has compared to existing technology advantages below：
1st, the embodiment of the present invention provides a kind of Hall element, including the substrate, p-type indium arsenide layer, the N-type that are cascading
Indium arsenide layer.Because indium arsenide layer is n-type doping, p-type indium arsenide layer is transition zone, so as to form a sky in both interfaces
Between charged region, and the electrode in Hall element only contacts N-type region domain, therefore, in the Hall element course of work, p-type indium arsenide
Layer is not involved in conducting.So as to the defect in p-type indium arsenide layer does not interfere with device performance.And N-type functional layer direct growth
On p-type indium arsenide layer, defect concentration significantly reduces, and so as to the mobility of material is significantly increased, and then causes Hall element spirit
Sensitivity is greatly improved.
2nd, the embodiment of the present invention also provides a kind of preparation method of described Hall element, comprises the steps：In substrate
Upper formation p-type indium arsenide layer；N-type indium arsenide layer is formed on the p-type indium arsenide layer.Alternatively, the p-type indium arsenide layer leads to
Cross epitaxial growth technology preparation；Technical maturity, method is simple, reliable.
Description of the drawings
In order that present disclosure is more likely to be clearly understood, the specific embodiment below according to the present invention is simultaneously combined
Accompanying drawing, the present invention is further detailed explanation, wherein
Fig. 1 is the Hall element structural representation described in the embodiment of the present invention；
Fig. 2 is the Hall element top view described in the embodiment of the present invention；
Reference is expressed as in figure：1- substrates, 2-P type indium arsenide layers, 3-N type indium arsenide layers, 4- electrodes.
Specific embodiment
In order that the object, technical solutions and advantages of the present invention are clearer, below in conjunction with reality of the accompanying drawing to the present invention
The mode of applying is described in further detail.
The present invention can be embodied in many different forms, and should not be construed as limited to embodiment set forth herein.
On the contrary, there is provided these embodiments so that the disclosure will be thorough and complete, and will the present invention design be fully conveyed to
Those skilled in the art, the present invention will only be defined by the appended claims.In the accompanying drawings, for clarity, Ceng He areas can be exaggerated
The size and relative size in domain.It should be appreciated that when element such as layer, region or substrate are referred to as " being formed in " or " arrange
" another element " on " when, the element can be arranged directly on another element, or can also there is intermediary element.
Conversely, when element is referred to as on " being formed directly into " or " being set directly at " another element, there is no intermediary element.
Embodiment
The present embodiment provides a kind of Hall element, as depicted in figs. 1 and 2：Including the substrate 1, p-type arsenic that are cascading
Change indium layer 2, N-type indium arsenide layer 3, and the electrode 4 being formed on N-type indium arsenide layer 3.
Because N-type indium arsenide layer 3 is n-type doping, p-type indium arsenide layer 2 is transition zone, so as to form one in both interfaces
Individual space-charge region, and the electrode in Hall element only contacts N-type region domain, therefore, in the Hall element course of work, p-type arsenic
Change indium layer 2 and be not involved in conducting.So as to the defect in p-type indium arsenide layer 2 does not interfere with device performance.And N-type functional layer is straight
Connect and be grown on p-type indium arsenide layer 2, defect concentration significantly reduces, so as to the mobility of material is significantly increased, and then cause Hall
Element sensitivity is greatly improved.
The thickness of p-type indium arsenide layer 2 is 20nm～1000nm；The thickness of N-type indium arsenide layer 3 is 100nm-1000nm.N-type arsenic
The doped chemical for changing indium layer 3 is silicon and/or tellurium and/or sulphur；Substrate 1 is gallium arsenide substrate；Electrode 4 is metal electrode or Graphene
Electrode.
Used as one embodiment of the present of invention, in the present embodiment, the thickness of p-type indium arsenide layer 2 is 100nm；N-type indium arsenide
3 thickness of layer are 500nm；The doped chemical of N-type indium arsenide layer 3 is silicon；Electrode 4 is Mo electrodes.
The present embodiment also provides a kind of preparation method of Hall element, comprises the steps：
S1, on substrate 1 formation p-type indium arsenide layer 2；
Substrate 1 is gallium arsenide substrate, and p-type indium arsenide layer 2 is prepared by epitaxial growth technology or chemical vapor deposition method,
Such as molecular beam epitaxial process (MBE) or metal organic chemical vapor deposition technique (MOCVD).
Used as one embodiment of the present of invention, in the present embodiment, p-type indium arsenide layer 2 is heavy using Metallo-Organic Chemical Vapor
Prepared by product technique, growing method is：With arsine (AsH3) or tert-butyl group arsenic (TBAs) be arsenic source, trimethyl indium (TMIn) be indium
Luxuriant magnesium (the Cp of source, diethyl zinc (DEZn) or two2Mg it is) doped source, hydrogen (H2) it is carrier gas, growth temperature is 450 DEG C -600
DEG C, pressure is 20-500mbar, and V/III, than being 5-200, is grown.
Used as the convertible embodiment of the present invention, the preparation method of p-type indium arsenide layer 2 can also be：With solid-state arsenic (As4)
It is that indium source, solid-state beryllium or solid zinc or solid-state magnesium are doped source, 300 DEG C -550 DEG C of growth temperature for arsenic source, solid indium, pressure is
1E-10Torr, V/III, than being 1-100, is grown.
S2, form on p-type indium arsenide layer 2 N-type indium arsenide layer 3.
N-type indium arsenide layer 3 is prepared by epitaxial growth technology or chemical vapor deposition method, such as molecular beam epitaxial process
Or metal organic chemical vapor deposition technique (MOCVD) etc. (MBE).
Used as one embodiment of the present of invention, in the present embodiment, the growing method of N-type indium arsenide layer 3 is：With arsine
(AsH3) or tert-butyl group arsenic (TBAs) be arsenic source, trimethyl indium (TMIn) be indium source, silane (SiH4) or disilane (Si2H6) be
Doped source, hydrogen (H2) it is carrier gas, growth temperature is 450 DEG C -600 DEG C, and pressure is 20-500mbar, and V/III than being 5-200,
Grown.
Used as the convertible embodiment of the present invention, the preparation method of p-type indium arsenide layer can also be：With solid-state arsenic (As4)
For arsenic source, solid indium is indium source, and solid-state silicon is doped source, 300 DEG C -550 DEG C of growth temperature, and background pressure is 1E-10Torr,
V/III, than being 1-100, is grown.
The preparation method of the Hall element that the present embodiment is provided, also includes：
S3, by mesa etch process, p-type indium arsenide layer 2 and N-type indium arsenide layer 3 are patterned, formed Hall unit
Part pattern.
S4, on N-type indium arsenide layer 3 electrode 4 is formed, and be passivated.
S5, carry out device encapsulation.
, compared with technology, the present embodiment is repeated no more for step S3, S4, S5.
N-type indium arsenide layer 3 in the present embodiment is tested, mobility is 16500cm2/Vs。
Comparative example
This comparative example provides a kind of Hall element, its structure and the same embodiment of preparation method, it is unique unlike, this contrast
P-type indium arsenide layer is not provided with Hall element described in example.
N-type indium arsenide layer in this comparative example is tested, mobility is 11000cm2/Vs。
Obviously, above-described embodiment is only intended to clearly illustrate example, and not to the restriction of embodiment.It is right
For those of ordinary skill in the art, can also make on the basis of the above description other multi-forms change or
Change.There is no need to be exhaustive to all of embodiment.And the obvious change thus extended out or
Among changing still in protection scope of the present invention.
Claims (10)
1. a kind of Hall element, it is characterised in that including the substrate, p-type indium arsenide layer, the N-type indium arsenide layer that are cascading.
2. Hall element according to claim 1, it is characterised in that the thickness of the p-type indium arsenide layer be 20nm～
1000nm；The N-type indium arsenide thickness degree is 100nm-1000nm.
3. Hall element according to claim 1 and 2, it is characterised in that the doped chemical of the N-type indium arsenide layer is silicon
And/or tellurium and/or sulphur；The substrate is gallium arsenide substrate.
4. the preparation method of the Hall element described in a kind of any one of claim 1-3, it is characterised in that comprise the steps：
P-type indium arsenide layer is formed on substrate；
N-type indium arsenide layer is formed on the p-type indium arsenide layer.
5. the preparation method of Hall element according to claim 4, it is characterised in that the p-type indium arsenide layer is by outer
It is prepared by growth process or chemical vapor deposition method.
6. the preparation method of Hall element according to claim 5, it is characterised in that the growth of the p-type indium arsenide layer
Method is：With arsine (AsH3) or tert-butyl group arsenic (TBAs) be arsenic source, trimethyl indium (TMIn) be indium source, diethyl zinc (DEZn)
Or two luxuriant magnesium (Cp2Mg it is) doped source, hydrogen (H2) it is carrier gas, growth temperature is 450 DEG C -600 DEG C, and pressure is 20-
500mbar, V/III, than being 5-200, is grown.
7. the preparation method of Hall element according to claim 5, it is characterised in that the growth of the p-type indium arsenide layer
Method is：With solid-state arsenic (As4) for arsenic source, solid indium be indium source, solid-state beryllium or solid zinc or solid-state magnesium be doped source, growth temperature
300 DEG C -550 DEG C of degree, pressure is 1E-10Torr, and V/III, than being 1-100, is grown.
8. the preparation method of the Hall element according to any one of claim 4-7, it is characterised in that the N-type indium arsenide
Layer is prepared by epitaxial growth technology or chemical vapor deposition method.
9. the preparation method of Hall element according to claim 8, it is characterised in that the growth of the N-type indium arsenide layer
Method is：With arsine (AsH3) or tert-butyl group arsenic (TBAs) be arsenic source, trimethyl indium (TMIn) be indium source, silane (SiH4) or second
Silane (Si2H6) be doped source, hydrogen (H2) it is carrier gas, growth temperature is 450 DEG C -600 DEG C, and pressure is 20-500mbar, V/
III, than being 5-200, is grown.
10. the preparation method of Hall element according to claim 8, it is characterised in that the growth of the N-type indium arsenide layer
Method is：With solid-state arsenic (As4) it is arsenic source, solid indium is indium source, and solid-state silicon is doped source, and 300 DEG C -550 DEG C of growth temperature is carried on the back
Scape pressure is 1E-10Torr, and V/III, than being 1-100, is grown.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201610707556.3A CN106653998A (en) | 2016-08-23 | 2016-08-23 | Hall element and preparation method thereof |
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| CN201610707556.3A CN106653998A (en) | 2016-08-23 | 2016-08-23 | Hall element and preparation method thereof |
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Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5198795A (en) * | 1990-04-04 | 1993-03-30 | Asahi Kasei Kogyo Kabushiki Kaisha | Magnetoelectric transducer and process for producing the same |
| US20050067629A1 (en) * | 2003-01-13 | 2005-03-31 | Woodall Jerry M. | Semimetal semiconductor |
| CN102313563A (en) * | 2010-07-05 | 2012-01-11 | 精工电子有限公司 | Hall element |
-
2016
- 2016-08-23 CN CN201610707556.3A patent/CN106653998A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5198795A (en) * | 1990-04-04 | 1993-03-30 | Asahi Kasei Kogyo Kabushiki Kaisha | Magnetoelectric transducer and process for producing the same |
| US20050067629A1 (en) * | 2003-01-13 | 2005-03-31 | Woodall Jerry M. | Semimetal semiconductor |
| CN102313563A (en) * | 2010-07-05 | 2012-01-11 | 精工电子有限公司 | Hall element |
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