CN106653725A - 一种引线框架 - Google Patents

一种引线框架 Download PDF

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Publication number
CN106653725A
CN106653725A CN201510740373.7A CN201510740373A CN106653725A CN 106653725 A CN106653725 A CN 106653725A CN 201510740373 A CN201510740373 A CN 201510740373A CN 106653725 A CN106653725 A CN 106653725A
Authority
CN
China
Prior art keywords
lead frame
chip
insulation
base island
frame base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CN201510740373.7A
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English (en)
Inventor
马丙乾
刘桂芝
付强
段世峰
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
WUXI LINLI TECHNOLOGY Co Ltd
Original Assignee
WUXI LINLI TECHNOLOGY Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by WUXI LINLI TECHNOLOGY Co Ltd filed Critical WUXI LINLI TECHNOLOGY Co Ltd
Priority to CN201510740373.7A priority Critical patent/CN106653725A/zh
Publication of CN106653725A publication Critical patent/CN106653725A/zh
Pending legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Led Device Packages (AREA)

Abstract

本发明公开了一种引线框架，包括引线框架基岛，所述引线框架基岛上涂覆有基岛绝缘镀层，所述基岛绝缘镀层设置有绝缘装片胶，所述绝缘装片胶上封装有通过引线与所述引线框架基岛连接的芯片。本发明在引线框架基岛上镀一层绝缘层，可以保证芯片底部与引线框架的基岛不会因为绝缘装片胶过薄导致芯片与框架基岛发生短路，具有良好的绝缘性能，提高了产品的良率和可靠性。

Description

一种引线框架
技术领域
本发明涉及一种引线框架。
背景技术
目前，现在常用集成电路封装结构如图1所示，该引线框架包括引线框架基岛1、基岛银镀层21、绝缘装片胶3和芯片4。芯片4通过绝缘装片胶3与引线框架基岛1粘连。
在引线框架基岛1上设置绝缘装片胶3，然后将芯片4放置在绝缘装片胶3上，芯片4通过引线41与集成电路外引脚进行连接。当需要芯片4与引线框架基岛1之间绝缘时，通常会使用绝缘装片胶3来粘连芯片4与引线框架基岛1。由于现有框架基岛的镀层多为镀银等导电金属，框架基岛镀层表面不够平整，当绝缘装片胶的厚度过薄时，引线框架基岛上的镀层颗粒可能与芯片发生短路，从而出现漏电流。
发明内容
本发明目的是针对现有技术存在的缺陷提供一种引线框架。
本发明为实现上述目的，采用如下技术方案：一种引线框架，包括引线框架基岛，所述引线框架基岛上涂覆有基岛绝缘镀层，所述基岛绝缘镀层设置有绝缘装片胶，所述绝缘装片胶上封装有通过引线与所述引线框架基岛连接的芯片。
进一步的，所述基岛绝缘镀层的厚度在2-3mm之间。
本发明的有益效果：本发明在引线框架基岛上镀一层绝缘层，可以保证芯片底部与引线框架的基岛不会因为绝缘装片胶过薄导致芯片与框架基岛发生短路，具有良好的绝缘性能，提高了产品的良率和可靠性。
附图说明
图1传统的引线框架结构示意图。
具体实施方式
图1所示，为本发明的一种引线框架，包括引线框架基岛1，所述引线框架 基岛1上涂覆有基岛绝缘镀层22，所述基岛绝缘镀层22设置有绝缘装片胶3，所述绝缘装片胶3上封装有通过引线41与所述引线框架基岛1连接的芯片4。这样芯片4底部与引线框架基岛1就不会因为绝缘装片胶3过薄导致芯片4与引线框架基岛1之间发生短路了。其中，为了达到最好效果，可将所述基岛绝缘镀层22的厚度设置在2-3mm之间。
以上所述仅为本发明的较佳实施例，并不用以限制本发明，凡在本发明的精神和原则之内，所作的任何修改、等同替换、改进等，均应包含在本发明的保护范围之内。

Claims (2)

1.一种引线框架，其特征在于，包括引线框架基岛，所述引线框架基岛上涂覆有基岛绝缘镀层，所述基岛绝缘镀层设置有绝缘装片胶，所述绝缘装片胶上封装有通过引线与所述引线框架基岛连接的芯片。
2.如权利要求1所述的一种引线框架，其特征在于，所述基岛绝缘镀层的厚度在2-3mm之间。
CN201510740373.7A 2015-11-03 2015-11-03 一种引线框架 Pending CN106653725A (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201510740373.7A CN106653725A (zh) 2015-11-03 2015-11-03 一种引线框架

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201510740373.7A CN106653725A (zh) 2015-11-03 2015-11-03 一种引线框架

Publications (1)

Publication Number Publication Date
CN106653725A true CN106653725A (zh) 2017-05-10

Family

ID=58850970

Family Applications (1)

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Country Status (1)

Country Link
CN (1) CN106653725A (zh)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1581473A (zh) * 2003-08-07 2005-02-16 富士通株式会社 引线框架及其制造方法以及半导体器件
US20110189821A1 (en) * 2007-06-04 2011-08-04 Infineon Technologies Ag Semiconductor device
CN205452272U (zh) * 2015-11-03 2016-08-10 无锡麟力科技有限公司 一种引线框架

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1581473A (zh) * 2003-08-07 2005-02-16 富士通株式会社 引线框架及其制造方法以及半导体器件
US20110189821A1 (en) * 2007-06-04 2011-08-04 Infineon Technologies Ag Semiconductor device
CN205452272U (zh) * 2015-11-03 2016-08-10 无锡麟力科技有限公司 一种引线框架

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